Advanced Features of the ispmach 4000ZE Family
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1 ispmach 4000ZE Family April 2008 Technical Note TN1174 Introduction This technical note describes the architectural features of the ispmach 4000ZE ultra low power devices and how they can be implemented using Lattice's isplever Classic design software. The features discussed in this document include: 1. On-chip oscillator and timer 2. Power Guard 3. Individual I/O bus maintenance On-Chip Oscillator An internal oscillator and timer is provided for use in miscellaneous housekeeping functions such as watchdog heartbeats, digital de-glitch circuits and control state machines. The oscillator is disabled by default to save power. The oscillator and timer primitive can be used directly in schematic, or instantiated using HDL (ABEL, Verilog, or VHDL). Figure 1illustrates the functional block diagram of the oscillator and timer. Figure 1. Oscillator and Timer 128 OSCOUT DYNOSCDIS Timer TIMEROUT TIMERRES TIMER_DIV The software oscillator primitive (OSCTIMER) is shown in Figure 2. Figure 2. Software Oscillator Primitive DYNOSCDIS TIMERRES OSCTIMER OSCOUT TIMEROUT Table 1. OSCTIMER Signals Signal Name I/O Description OSCOUT Output Oscillator out (nominal frequency 5MHz +/- 30%) TIMEROUT Output Oscillator frequency divided by an attribute TIMER_DIV = (128, 1024, ), default is 128. TIMERRES Input Resets the timer. DYNOSCDIS Input Disables the oscillator. Saves AC power Note: At least one of the two outputs are required 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 1 tn1174_01.1
2 On-Chip Oscillator HDL Usage Below are Verilog, VHDL, and ABEL definitions of the OSCTIMER. For additional information on designs that use the oscillator, reference examples are included with the isplever Classic design tool. Verilog OSCTIMER Declaration: module osctimer(dynoscdis, TIMERRES, OSCOUT, TIMEROUT); parameter TIMER_DIV = 128 ; input DYNOSCDIS; input TIMERRES; output OSCOUT; output TIMEROUT; endmodule OSCTIMER Parameter Declaration and Instantiation: VHDL defparam I1.TIMER_DIV = 1024, osctimer I1 (.DYNOSCDIS(osc_dis),.TIMERRES(tmr_rst),.OSCOUT(osc_out),.TIMEROUT(tmr_out)); library lattice; use lattice.components.all; OSCTIMER and Attribute Declaration: component osctimer generic(timer_div : string); port( DYNOSCDIS : in std_logic; TIMERRES : in std_logic; OSCOUT : out std_logic; TIMEROUT : out std_logic); end component; OSCTIMER Instantiation: I1: OSCTIMER generic map (TIMER_DIV => 1024 ) port map ( DYNOSCDIS => osc_dis, TIMERRES => tmr_rst, OSCOUT => osc_out, TIMEROUT => tmr_out); end component; 2
3 ABEL library 'lattice'; OSCTIMER Declaration: XLAT_OSCTIMER(DYNOSCDIS, TIMERRES, OSCOUT, TIMEROUT, 128); OSCTIMER Instantiation: I1 OSCTIMER(osc_dis, rst, osc_out, tmr_out); On-Chip Oscillator in the Constraint Editor The isplever Classic Constraint Editor includes an OSCTIMER Attribute Sheet. This sheet gives the user the ability to view signals, connected to the oscillator and set the divider value (TIMER_DIV). Table 2. Oscillator in the Constraint Editor Type Oscillator Clock Timer Clock Oscillator Disable Timer Reset Timer Divide OSCTIMER TOUT_c TOUT2_c RST_c RST2_c 128 On-Chip Oscillator in the Report File The OSCTIMER section of the report file includes all connections and properties of the oscillator. OSCTIMER_Summary ~~~~~~~~~~~~~~~~ OSCTIMER: OSCTIMER Instance Name Dynamic Disable Signal Timer Reset Signal Oscillator Output Clock Timer Output Clock Pin/Node I1 osc_rst osc_rst2 mfb A-15 TOUT_c mfb G-15 TOUT2_c Oscillator Output Clock Frequency MHz Timer Output Clock Frequency KHz Timer Divider 128 Power Guard During the system inactive state, ignoring the CPLD array logic from external input signal changes based on a system inactive signal is an excellent way to reduce power and increase battery life. This feature is called Power Guard in the ispmach 4000ZE family. When all the inputs have Power Guard turned on the power consumption of the device is close to standby current of the device. The Power Guard can be used directly in schematic entry, or instantiated using HDL (ABEL, Verilog or VHDL). A bus with Power Guard can be generated using the Module Manager. Figure 3 shows a detailed architectural view of the I/O cell including the Power Guard block. 3
4 Figure 3. ispmach 4000ZE I/O Cell GOE 0 GOE 1 GOE 2 GOE 3 From ORP VCC I/O Bus Maintenance VCCO From ORP Power Guard To Macrocell To GRP 0 1 Power Guard Disable Fuse (PGDF) Block Input Enable (BIE) (From Block PT) The software Power Guard primitive is shown in Figure 4. Figure 4. Power Guard Primitive Power Guard D E 0 1 Q Table 3. Power Guard Signals Signal Name I/O Description D E INPUT INPUT Q OUTPUT Signal coming from an input or I/O pad. This pin cannot have any fanout and connects only between the pad and the Power Guard. The ENABLE input that is tied to BIE (Block Input Enable). The BIE signal is driven directly from an I/O or through logic such as an OE signal. This is the output of the Power Guard that drives toward the Global Routing Pool. When E=1, the output Q is driven by the input D. 4
5 Power Guard HDL Usage Below are Verilog, VHDL, and ABEL definitions of the Power Guard option. For designs that use Power Guard, refer to the examples included with the isplever Classic design tool. Verilog Power Guard Declaration: module PG_example(D, E, Q); input D; input E; output Q; endmodule Power Guard Instantiation: VHDL PG I1 (.D(Input_sig),.E(Enable_sig),.Q(Temp_sig)); library lattice; use lattice.components.all; Power Guard Declaration: component PG port( D : in std_logic; E : in std_logic; Q : out std_logic); end component; Power Guard Instantiation: I1: PG port map ( D => Input_sig, E => Enable_sig, Q => Temp_sig); ABEL "library 'lattice'; Power Guard Declaration: XLAT_PG(D, E, Q); OSCTIMER Instantiation: I1 PG(in0, ie, d0); 5
6 Power Guard Module Manager Usage The Module Manger can be used to generate a bus of Power Guard primitives, which can be instantiated in the target design. The only option is to specify the width of the Power Guard bus. Figure 5 is a screen shot of the Power Guard Module Manager GUI. Figure 5. Power Guard Module Manager GUI Power Guard Usage Rules There are several important guidelines to keep in mind when using Power Guard: 1. Within a block, the Power Guard enables must be connected to the same. 2. If the BIE signal feeds itself, the Fitter will produce an error. 3. If the BIE signal is generated via internal logic and the source of the logic is the Power Guard output, then the Fitter will produce a warning. Power Guard in the Report File I/Os which have Power Guard enabled can be identified in the Fitter Report by looking at the Power Guard Enable column. The signal in the Power Guard Enable is the logical net name which drives the Power Guard Enable port. Below is an example of the Fitter Report that includes the Power Guard information in the right-hand column: Pinout_Listing ~~~~~~~~~~~~~~ Pin Bank GLB Assigned Signal Signal PG Pin No Type Number Pad Pin I/O Type Type Name Enable TDI - 2 I_O/OE 0 A5 LVCMOS18 Input a_4_ PG_E_node 3 I_O 0 A6 LVCMOS18 Input rst 4 I_O/OE 0 A7 LVCMOS18 Input a_5_ PG_E_node 5 GNDIO0-6 VCCIO0 - Individual I/O Bus Maintenance The ispmach4000ze I/Os have individual programmable I/O bus maintenance options. The four options for the I/O are programmable pull-up, pull-down, bus keeper and off. The I/O bus maintenance can be set using the isplever Constraints Editor or using the HDL attribute PULL set to either UP, DOWN, HOLD, or OFF. 6
7 Technical Support Assistance Hotline: LATTICE (North America) (Outside North America) Internet: Revision History Date Version Change Summary April Initial release. April Updated On-board Oscillator and Timer diagram. Replaced I/O Termination with Individual I/O Bus Maintenance. 7
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GreenPAK Programmable Mixed Signal Array Features Logic & Mixed Signal Circuits Highly Versatile Macro Cells 1.8 V (±5%) to 5 V (±10%) Supply Operating Temperature Range: -40 C to 85 C RoHS Compliant /
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4421/421/4211/4221 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Features CY7C4421/421/4211/4221 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs High-speed, low-power, First-In, First-Out (FIFO) memories
PT7C4502 PLL Clock Multiplier
Features Low cost frequency multiplier Zero ppm multiplication error Input crystal frequency of 5-30 MHz Input clock frequency of 4-50 MHz Output clock frequencies up to 180 MHz Period jitter 50ps (100~180MHz)
LA-MachXO Automotive Family Data Sheet. DS1003 Version 01.5, November 2007
DS1003 Version 01.5, November 2007 Introduction April 2006 Features Non-volatile, Infinitely Reconfigurable Instant-on powers up in microseconds Single chip, no external configuration memory required Excellent
Two Op-Amps Three Op-Amps
Datasheet INSAMPV 2.2 001-13566 Rev. *G Instrumentation Amplifier Copyright 2002-2014 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks API Memory (Bytes) Digital Analog CT
ICS HIGH PERFORMANCE VCXO. Features. Description. Block Diagram DATASHEET
DATASHEET ICS3726-02 Description The ICS3726-02 is a low cost, low-jitter, high-performance designed to replace expensive discrete s modules. The ICS3726-02 offers a wid operating frequency range and high
ML Bit Data Bus Input PLL Frequency Synthesizer
4 Bit Data Bus Input PLL Frequency Synthesizer INTERFACES WITH SINGLE MODULUS PRESCALERS Legacy Device: Motorola MC145145-2 The ML145145 is programmed by a 4 bit input, with strobe and address lines. The
5V 128K X 8 HIGH SPEED CMOS SRAM
5V 128K X 8 HIGH SPEED CMOS SRAM Revision History AS7C1024B Revision Details Date Rev 1.0 Preliminary datasheet prior to 2004 Rev 1.1 Die Revision A to B March 2004 Rev 2.0 PCN issued yield issues with
Produces a selectable output voltage that is higher than the input voltage
Features Produces a selectable output voltage that is higher than the input voltage Input voltage range between 0.5 V and 3.6 V Boosted output voltage range between 1.8 V and 5.25 V Source up to 75 ma
Microprocessor Supervisory Circuits ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
Microprocessor Supervisory Circuits FEATURES Upgrade for ADM690 to ADM695, MAX690 to MAX695 Specified over temperature Low power consumption (0.7 mw) Precision voltage monitor Reset assertion down to V
Switch/ Jumper Table 1-1: Factory Settings Factory Settings (Jumpers Installed) Function Controlled Activates pull-up/ pull-down resistors on Port 0 digital P7 I/O lines Activates pull-up/ pull-down resistors