Ultrasonic Sensor Based Contactless Theremin Using Pipeline CORDIC as Tone Generator

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1 Ultrasonic Sensor Based Contactless Theremin Using Pipeline CORDIC as Tone Generator Bagus Hanindhito, Hafez Hogantara, Annisa I. Rahmah, Nur Ahmadi, Trio Adiono Department of Electrical Engineering, School of Electrical Engineering and Informatics Bandung Institute of Technology, Jl. Ganesha No. 0 Bandung, 4032, Indonesia hanindhito@bagus.my.id, tadiono@stei.itb.ac.id Abstract Theremin is an electronic musical instrument controlled without physical contact by the performer. It has two antennas to control pitch and volume. By replacing the antennas with ultrasonic sensor, a new redefined theremin is implemented. The ultrasonic sensor will control the tone generator which is implemented in FPGA Altera Cyclone II EP2C35F672C6 of DE2-70 board. The tone generator is implemented by using a pipeline CORDIC circuit. CORDIC (Coordinate Rotation Digital Computer) is a digital circuit that can be used to compute several common mathematical transcendental functions with only basic hardware requirements. It is used to generate sine wave as a tone in specific frequency and volume. It is firstly implemented in iterative structure to carry out all of optimization needed to achieve higher performance, less area consumption, and higher precision. To increase the throughput, the CORDIC circuit is modified into pipeline structure at an epense of some area consumption. Keywords FPGA, Pipelined CORDIC, Theremin, Tone Generator, Ultrasonic Sensor. I. INTRODUCTION Theremin is a contactless electronic musical instrument invented by physicist Lon Theremin ] when he was doing research on proimity sensors for the Russian government in the early 920s. Theremin consist of two circuits, the pitch circuit and the volume circuit. The pitch circuit uses two tuned oscillator, a fied oscillator and a variable oscillator. The fied oscillator generates wave at a constant frequency meanwhile the variable oscillator is capable to generate a range of frequencies and is connected to a vertical antenna. By a process called heterodyning, wave from the fied oscillator is mied with wave from variable oscillator. The miture is then amplified to produce audible musical tone. On the other hand, the volume circuit is used to control the level of tone generated by the pitch circuit. This traditional theremin is bulky in term of dimension and epensive to be built. The basic ideas on how theremin works can be modified even further. One of the possible sensor to replace the antennas in theremin is ultrasonic sensor. An ultrasonic sensors will transmit ultrasonic waves and waiting for the return echo. By measuring time needed for the wave to travel back and forth, the distance between the sensor and an object (i.e. performer s hand) can be calculated. Therefore, the distance which represents the position of performer s hand can be used to generate specific tone on specific frequency and volume. The ultrasonic sensor will be directly connected to the general purpose pin in FPGA without additional peripheral. Dedicated logic circuit such as counter and trigger will be implemented in FPGA to operate the ultrasonic sensor. By using multiple dedicated logic circuit, multiple ultrasonic sensor can be driven simultaneously thus it can achieve more performance while maintaining distance tracking capability. The main circuit to implement the tone generator responsible for generating sound wave at specific frequency and amplitude is performed by CORDIC (Coordinate Rotation Digital Computer). CORDIC is a digital circuit that can be used to compute several common mathematical transcendental function. It was proposed by Jack E. Volder in 959 2]. CORDIC circuit is usually used when there is no hardware multiplier available or hardware multiplier is too epensive to be implemented. It only requires adder, substractor, bit shifter, and very small look-up table. The CORDIC circuit will use signed Q3.3 Fied Point format so that it can represent angle between π until π with acceptable precision. At the beginning, it is implemented in iterative structure. To increase the throughput, the CORDIC circuit is then modified into pipeline structure to be used as tone generator at an epense of area. At the end of this paper, a new redefined theremin is implemented by combining the ultrasonic sensor and CORDICbased tone generator. The full circuit including the ultrasonic sensor interfacing and tone generator is implemented in FPGA Altera Cyclone II EP2C35F672C6 of DE2-70 board. The theremin can generate basic tone in specific frequency and volume depends on performer s hand position without touching the instruments. II. A. Mathematical Review THE CORDIC CIRCUIT CORDIC Circuit is built based on mathematical formula as described in 3]. It is started from the famous rotation matri as follows ] ] cos(z) sin(z) y = () sin(z) cos(z)] y The rotation matri () can be rearranged into ] ] ] tan(z) y = cos(z) tan(z) y (2)

2 The value of cos(z) can be substituted using trigonometric identities in (3) so equation (4) can be obtained. y ] = cos(z) = +tan 2 (z) +tan 2 (z) tan(z) tan(z) ] y For a very small angle α i, the value of tan(α i ) can be approimated using (5). Using n iteration steps, the angle z can be approimated in (6) where α i = ±. This is the basic idea of CORDIC where the rotation of angle z is iteratively decomposed into i numbers of smaller micro rotation of angle α i. tan(α i )=2 i (5) ] (3) (4) n z = σ i α i (6) i=0 Therefore, the rotation matri can be rewritten in each iteration step as (7) where i denotes the iteration number (i.e. i is current iteration step, i previous iteration step). i ] = y i +2 2i K = σi 2 i n K i = i=0 σ i 2 i n i=0 +2 2i ] ] i y i As the iteration step approaches infinity, the approimation becomes more precise. Moreover, the multiplication result of K converges to which makes K can be considered as a constant operand thus it will reduce arithmetic compleity in designing the hardware. The region of convergence for z is z since i=0 α i = ]. B. CORDIC Algorithm Model Basic CORDIC algorithm has two different modes of iteration based on how the directions of the micro rotation are chosen. These two modes are rotation mode and vectoring mode. In rotation mode, CORDIC uses three equations which are defined in (9). The value of σ i is determined by the value of z i where σ i = when z i < 0 and σ i =otherwise. i+ = i y i σ i 2 i y i+ = y i + i σ i 2 i z i+ = z i σ i tan (2 i ) As the iteration step approaches infinity, the end result for the equation set are defined as follows = K( 0 cos(z 0 ) y 0 sin(z 0 )) y = K(y 0 cos(z 0 )+ 0 sin(z 0 )) z =0 (7) (8) (9) (0) In vectoring mode, CORDIC uses three equations which are defined in (). The value of σ i is determined by the value of y i where σ i =when y i < 0 and σ i = otherwise. i+ = i y i σ i 2 i y i+ = y i + i σ i 2 i () z i+ = z i + σ i tan (2 i ) As the iteration step approaches infinity, the end result for the equation set are epressed as follows = K y2 0 y =0 (2) z = z 0 +tan (y 0 / 0 ) Both rotation mode and vectoring mode need to use the value of tan (2 i ) in every step of iteration. The value of tan (2 i ) can be precomputed and stored in a lookup table thus reducing arithmetic operation compleity. Moreover, at the end of iteration, both rotation mode and vectoring mode will require a normalization to eliminate the factor of K by multiplying it with /K. The value of /K can also be precomputed thus the multiplication will involve only one constant multiplicand and one variable multiplicand which will reduce arithmetic operation compleity. With these two basic modes in CORDIC, there are four mathematics operation that can be done using CORDIC: sine function, cosine function, cartesian-to-polar coordinate conversion, and polar-to-cartesian coordinate conversion. C. Defined Fied Point Format CORDIC algorithm has a region of convergence z for the angle value. Therefore, it can only be used to calculate angle in st and 4th quadrant ( π/2 z π/2). With the help of simple mapping function, the CORDIC algorithm can be etended to be used for 2nd and 3rd quadrant ( π z π). Based on this fact, 6-bit fied point format that will be used throughout the circuit is in Q3.3 format as shown in Figure where one bit represent the sign in twos complement, two bits represent the integer (digit before radi point), and thirteen bits represent the fraction (digit after radi point). With this format, the possible smallest step of real number that can be represented is The range of representation that can be achieved is It is very sufficient to handle calculation involving angle in the range of π z π. D. Defined Analysis and Synthesis Settings The CORDIC circuit and the complete circuit are implemented to Altera Cyclone II EP2C35F672C6 of DE2-70 FPGA board. This board is clocked at maimum frequency 50 MHz. Area optimization must be carried out as long as the circuit Sign Integer Fraction Fig.. Q3.3 fied point format to be used throughout the circuit.

3 Fig. 2. XOR gate with 50 inputs as reference circuit for normalization can run at 50MHz. To synthesize our design, Altera Quartus II 9.sp2 is used while the simulation and verification are performed by using MentorGraphics ModelSim. Nowadays, comparing design head-to-head is very difficult because EDA tools become more advanced to find the most optimized implementation of a design. Therefore, we turn off all of optimization features in synthesizer to make comparison better. Furthermore, as a normalization parameter, we also synthesized an XOR gate which has 50 input as shown in Figure 2. The synthesis result including total area (i.e. logic elements) and performance (i.e. clock speed) can be obtained. Based on this data, we can normalize other design which is implemented on the same FPGA and same settings. We use VHDL file from 4] to implement the 50-input XOR gate. The XOR gate has been successfully synthesized. It uses 7 Logic Elements and it has maimum frequency of MHz according to the Timing Analyzer Summary. The registers are ecluded from resource usage count. E. CORDIC Iterative Structure At first, CORDIC based iterative structure is implemented. The idea behind this structure is to use the same circuit component (e.g. adder) during each step of iterations, minimizing the total area consumption. The circuit top level block diagram is shown in Figure 3. This CORDIC Circuit can be used to perform rotation mode and vectoring mode. The mode signal is used to choose between the vectoring mode (mode=0) or the rotation mode (mode=). The new_data signal is used to indicate that there is a valid dataset which is ready to be processed so that the circuit can perform calculation. The data_valid is used to indicate that there is a valid dataset which has been processed and available as output on the net clock cycle. Basically, it requires 6 clock cycles to process one dataset before valid data appears on the output port. Additional registers, the output registers are added as output buffer to make sure that the result is not changed while the net circuit uses it. The output register add one clock cycle delay to hold the output. Quadrant Mapper: CORDIC algorithm only can be used in st and 4th quadrant due to its region of convergence. Fig. 4. The quadrant mapper circuit Therefore, to etend the CORDIC to be used in 2nd and 3rd quadrant, quadrant mapper is employed as shown in Figure 4. Quadrant mapper will map 2nd and 3rd quadrant into corresponding location in st and 4th quadrant. Quadrant mapper uses some comparators to compare value of angle. With the information of mode, the comparison result is used as multipleer selector. There are also some sign inverter and carry look-ahead adder in the circuit. With this quadrant mapper, CORDIC can be used for all quadrants with π z π. Moreover, Q3.3 fied point format gives the circuit possibilities to perform calculation in its new region of convergence. Fig. 3. Top level diagram of CORDIC iterative structure Fig. 5. The CORDIC core circuit

4 TABLE I. SINE CALCULATION USING CORDIC ITERATIVE STRUCTURE AND MATLAB CORDIC Result MATLAB Result Angle (Rad) Binary Decimal Binary Decimal Fig. 6. The normalization circuit CORDIC Core: CORDIC core as shown in Figure 5 is the heart of CORDIC circuit where iterations take place. This circuit consists of three sub circuits which handle calculation of X, Y, and Z. ROM is utilized to store the value of tan (2 i ). Actually, the number of iterations can be reduced to 4 since the two last iterations do not have significant effect to our result. Normalization: The normalization circuit as depicted in Figure 6 is the last step of calculation. It multiplies the CORDIC iteration result with constant multiplicand /K to normalize its value. The value of /K in Q3.3 Fied Point Format is or equivalent with Since the multiplication consists one constant multiplicand, we can easily replace multiplier circuit with adder and shifter. Output Register: Output register is used as an output buffer. This register will hold the data result for one cycle to guarantee that the data result will not change when the net circuit read it. CORDIC Control Unit: The control unit consists of finite state machine which responsible to generate control signal based on each processing step. It has 6 states for iteration plus additional state to hold the result. The iteration will be started as soon as the control unit receive new_data signal. The data_valid signal will be high when iterations have been done and the valid data will be available in the net clock cycle. F. Implementation of CORDIC Iterative Structure Our CORDIC Iterative Structure consumes 972 logic elements consists of 957 total combinational functions and 34 dedicated logic registers. The Normalizer Circuit consumes approimately 45% of total logic elements used while the CORDIC Core consumes approimately 35% of total logic elements. Moreover, our CORDIC iterative structure can achieve operation frequency of MHz based on timing analyzer. In Table I, we compare our CORDIC iterative structure calculation result with MATLAB R204a calculation result using the same format. The difference between our CORDIC iterative structure and MATLAB has maimum of 3 least significant bit (LSB) differences (3-bit accuracy) which is acceptable enough to achieve precision up to 4 decimal digits after radi point. The generated sinewave from simulation is shown in Figure 7. G. CORDIC Pipeline Structure Our CORDIC iterative structure works very well with desired precision with the maimum speed of MHz. However, it cannot operate in our desired frequency of 50 MHz (DE2-70 Clock Generator). Thus, the structure is modified into pipeline as shown in Figure 8 to provide more throughput with higher operating frequency. The CORDIC core remains the same ecept we remove the feedback path and register. We also remove CORDIC control unit because we do not need to count the number of iterations as the data only flow through the pipeline. The mode and valid signal will also propagate throughout the pipeline stages to provide self-control to the net pipeline stage. H. Implementation of CORDIC Core Pipeline Structure Our pipeline CORDIC consumes 2242 logic elements consists of 255 total combinational functions and 800 dedicated logic registers. The normalizer circuit consumes approimately 20% of total logic elements used while the CORDIC Core consumes approimately 70% of total logic elements. Moreover, our pipeline CORDIC can achieve operation frequency of MHz which is very sufficient to be clocked at 50 MHz in our final FPGA implementation. I. Pipeline Stage Modification to CORDIC Pipeline Structure The longest path which prevents our pipeline CORDIC to operate at higher frequency is the normalization circuit. To

5 Fig. 7. ModelSim Simulation of our CORDIC iterative structure generating sine and cosine wave Fig. 8. CORDIC pipeline structure with 6 pipeline stages configured to calculate the value of sine from specific angle. The angle is incremented with specific frequency so that full form of specific sine wave with desired frequency can be generated repeatedly. We need Numerically Controlled Oscillator to provide proper clock frequency to generate the sine wave. The generated wave form will be sent to Wolfson WM873 audio codec integrated in DE2-70 FPGA board. increase the operating frequency, we have to divide lengthy path into several processing path thus adding more pipeline stages our design. The number of area consumption will be increased because we need to add registers for the new pipeline stages. The normalization circuit is divided into two stages and three stages to compare them with one stage normalization circuit. J. CORDIC Core Circuit Comparison There are several open source CORDIC circuit references to be compared. The reference circuit is synthesized with eactly the same hardware, synthesis tools, and configuration. There are 5 CORDIC circuits and 2 reference CORDIC circuits for comparison. Those references are taken from 5] and 6]. The comparison is shown in Table II. III. THE TONE GENERATOR The tone generator is implemented using our pipeline CORDIC with 6 pipeline stages. The CORDIC circuit is TABLE II. CORDIC CIRCUIT HEAD-TO-HEAD COMPARISON Parameter CORDIC Circuit Type Iterative Iterative 6-Pipeline 7-Pipeline 8-Pipeline Iterative 5-Pipeline Fied Point Format Q3.3 Q3.3 Q3.3 Q3.3 Q3.3 Q2.4 Q2.4 Number of Iterations Region of Convergence - π π -π π -π π -π π -π π -π/2 π/2 -π/2 π/2 Rotation Mode Yes Yes Yes Yes Yes Yes Yes Vectoring Mode Yes Yes Yes Yes Yes No No Total Logic Elements Total Combinational Total Registers Maimum Frequency (MHz) Processing Cycle Maimum Throughput (MIOPS) Normalized Total Logic Elements Normalized Maimum Frequency CORDIC Iterative Structure with 6 iterations. 2. CORDIC Iterative Structure with 4 iterations. 3. CORDIC Pipeline Structure with 6 pipeline stages (assuming pipelines are full). 4. CORDIC Pipeline Structure with 7 pipeline stages (assuming pipelines are full). 5. CORDIC Pipeline Structure with 8 pipeline stages (assuming pipelines are full) (assuming pipelines are full, separate circuit available for Vectoring Mode). A. Angle Generator Block Angle Generator block provides input angle to CORDIC circuit to be calculated thus the circuit can generate full sine wave. Angle generator will increment angle repeatedly. There are 5456 values of angle in Q3.3 fied point format which represent angle from π π. Angle generator is implemented to increment the angle by the value of 32. Therefore, to achieve one period of sine wave,,608 clock cycles is needed. At 20 KHz sine wave, we need, , 000 = 32, 60, 000 Hz 32 MHz. B. Numerically Controlled Oscillator Block Numerically controlled oscillator (NCO) provides clock needed for the angle generator to generate sine wave in specific frequency. The numerically controlled oscillator divides the main clock at 50 MHz into smaller frequency based on given divider. To determine the value of divider for specific frequency of sine wave, the following equation is used. divider = (3) f sine 608 C. Volume Adjustment Block To adjust the volume, an access to Audio Codec WM873 via I2C protocol is needed. Therefore, an I2C controller to send configuration data to the Audio Codec WM873 is built. The configuration will be sent to set the register RHPVOL and LHPVOL as described in 7]. The adjustment can be done to control the volume from -73 db until +6 db as well as to mute the volume. IV. THE ULTRASONIC SENSOR A. Paralla PING))) Ultrasonic Distance Sensor In this work, Paralla PING))) ultrasonic distance sensor is used. This sensor is equipped with two elements, the transmitter and the receiver. Generally, the sensor works by transmitting an ultrasonic pulse to the target and receiving the feedback pulse that reflected from the target. The return pulse s time contains the information to measure the distance between the sensor and the target.

6 Fig. 9. Complete circuit of the Redefined Theremin B. Sensor Interface Circuit Based on the datasheet, circuit to interface the PING))) sensor is created. Tri-state buffer to interface the I/O Pin on PING))) sensor is needed as the pin can be used as both input and output. A counter-based finite state machine to match the timing requirement is implemented. The finite state machine state will be changed based on counter value. There are four state of the finite state machine: triggering, waiting, counting echo, and delay. The delay state is needed before performing net measurement. Besides, to count the time needed for wave to travel, a distance counter is required. V. THE REDEFINED THEREMIN All of the circuits is then integrated to make a complete circuit. Two PING))) sensors are employed: frequency control and volume control. The frequency mapping block maps given distance range to a value of divider to generate sine wave in desired frequency. Higher divider means lower frequency. The volume mapping block maps given distance range to a value of volume level. Higher level means higher volume. The complete circuit is shown in Figure 9. The redefined Theremin is successfully implemented as standalone solution which does not need eternal hardware outside the board. The functionality of antenna can be changed with ultrasonic sensor hence the contactless feature of Theremin can be preserved. VI. CONCLUSION AND FUTURE WORK We have successfully designed and implemented our CORDIC Circuit. We started from the iterative structure to see how it works and to eamine the precision. We modified the iterative structure into pipeline structure. The pipeline structure can achieve operating frequency of 50 MHz. We also presented several variant of our CORDIC circuit so that we can choose which one that fits our need. We have also made PING))) sensor interfacing and successfully acquired the distance data from ultrasonic transmission. We mapped this distance to desired frequency and volume to generate sine wave in specific frequency and volume. Then, we integrate all of the component to perform complete circuit. Our solution is standalone which means that we do not need eternal processing hardware outside DE2-70 board. We have successfully made a newly redefined Theremin which has ultrasonic sensor to replace the antenna. For future work, the CORDIC circuit can be etended to support more mathematical functions such as hyperbolic function. Moreover, the usage of CORDIC circuit as a tone generator can be taken to higher level such that it can produce multiple frequencies at the same time. It will be useful to create sound synthesizer using additive synthesis and speech synthesizer based on sine wave. The ultrasonic sensor interfacing circuit can also be useful for more advanced applications. Multiple ultrasonic sensors can be operated simultaneously using dedicated interfacing circuit to achieve higher performance, lower latency, and better tracking capability compared to single core sequential microprocessor solutions. Applications such as advanced distance measurement, object locator, and object tracking can be built using ultrasonic sensor and FPGA with proper interfacing circuit. REFERENCES ] Y. Wu, P. Kuvinichkul, P. Y. Cheung, and Y. Demiris, Towards anthropomorphic robot thereminist, in 200 IEEE International Conference on Robotics and Biomimetics (ROBIO). IEEE, 200, pp ] J. E. Volder, The CORDIC trigonometric computing technique, Electronic Computers, IRE Transactions on, no. 3, pp , ] P. K. Meher, J. Valls, T.-B. Juang, K. Sridharan, and K. Maharatna, 50 years of CORDIC: Algorithms, architectures, and applications, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 56, no. 9, pp , ] L. C. E. Committee, Cordic core overview, Okinawa, Japan, Jan 205. Online]. Available: 5] R. Herveille, Cordic core overview, Mar. 0, Online]. Available: 6] L. C. E. Committee, Cordic verilog code, Okinawa, Japan, Jan 205. Online]. Available: v.zip 7] Wm873 portable internet audio codec with headphone driver and programmable sample rates, Wolfson Microelectronics Ltd, Edinburgh, UK, Aug 200.