IN OUT VDD VSUBSTRATE VNWELL. p+ p+ n+ n+ n-well. p- SUBSTRATE

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1 Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks Pankaj Pant Georgia Institute of Technology Vivek De Intel Corp., Hillsboro, OR Abhijit Chatterjee Georgia Institute of Technology Abstract We demonstrate a new approach for minimizing the total of the static and the dynamic power dissipation components in a CMOS logic network required to operate at a specied clock frequency using joint optimization of both device and circuit designs for a specic logic schematic and activity prole. We present a new approach to designing ultra low-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths for a specied speed constraint. The static (leakage) and dynamic (switching) energy components are considered and an ecient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods. 1 Introduction Traditionally, approaches to minimizing the dynamic power dissipation or switching energy consumption of static CMOS logic networks have advocated straightforward reduction in the supply voltage. It has been shown that the resulting throughput loss on account ofincreased gate delay can be eectively compensated through increased data-path parallelism in special-purpose signal-processing applications and by careful transistor sizing [3]. Methodologies for minimizing the sum total of static or leakage and dynamic energy consumption in general-purpose CMOS processes without regard to a performance requirement have also been proposed [2]. Total power is minimized through selection of supply and threshold voltage values such that the leakage and switching components of the dissipation are equal. The accompanying performance loss can be compensated to some degree by minimizing the product of the switching energy and the propagation delay instead of power or energy alone. The relationship between transistor sizing and power has been examined in [10]. A study of supply and threshold voltage selection for low power has been performed in [7]. However, the focus of this study is dierent from the CMOS circuit networks discussed in our paper. In this paper, we propose a comprehensive approach to the minimization of the sum total of the static and dynamic energy dissipation components in a CMOS random logic network required to operate at a specied clock frequency. This This research was supported by NSF Grant No MIP at the Georgia Institute of Technology. \Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for prot or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specic permission and/or a fee." DAC 97, Anaheim, California c1997 ACM /97/06... $3.50 power minimization is accomplished through conjoint optimization of both device and circuit designs for a specic logic schematic, activity prole and critical path delay requirement. In particular, we determine the optimal supply voltage for the entire module, one or more distinct threshold voltage values for groups of MOSFETs and a channel width for each transistor that minimizes total power or the total energy consumption per cycle while satisfying the critical path delay constraint. The resulting designs operate at low supply voltages and have comparable leakage and switching power dissipation components. The leakage current becomes signicant due to the need to reduce threshold voltage with reduced supply voltage to maintain speed. The underlying optimization algorithms and the associated CAD tools allow an order of magnitude reduction in power consumption over designs optimized for only supply voltage and device widths (as opposed to supply voltage, device widths and threshold voltage). The algorithms discussed in this paper can be used to design a CMOS process for ultra low power designs (the algorithms inuence threshold voltage selection). In determining the threshold voltage for a process being developed for future applications, one may use the algorithms on existing benchmarks with predicted circuit timing parameters to nd the most desirable threshold voltage. Also, the methods discussed in this paper can be used to statically adjust the threshold voltage as follows. The threshold-adjust implant step [2] which produces low V ts natural nmos and pmos transistors is eliminated. A static reverse bias is applied to the p-substrate and the n-wells to obtain the desired nmos and pmos V ts values, respectively. An example of an inverter designed this way isshown in Figure 1. Akey advantage of this approach is that one can design ultra low-power VLSI with existing CMOS manufacturing technology. VDD VNWELL p+ p+ n+ n+ n+ p+ n-well IN OUT p- SUBSTRATE VSUBSTRATE Figure 1: Adjustment of threshold voltage in CMOS technology In summary, the new power minimization technique provides the following advantages over existing techniques: 1) power reduction is accomplished without any performance loss; 2) both static and dynamic power consumption com-

2 ponents are minimized; and 3) optimizations are performed conjointly across device and circuit design. Moreover, the energy savings yielded by this technique is in addition to what is achievable by activity minimization through assorted architectural and algorithmic techniques [3]. 2 The Power Minimization Problem The power minimization problem can be stated as follows: Given : 1)arandom logic network of N static CMOS gates, 2) a required operational clock frequency f c, 3) a device technology and 4) activity proles at each input node, Determine : 1) the supply voltage V dd, 2) the threshold voltage V TSi of each MOSFET and 3) the channel width W i of each device such that the sum total of the static and dynamic components of energy consumption in a clock cycle is minimized while allowing operation at the desired clock frequency f c. The number n v 1 of distinct threshold voltages that are allowed by the tolerable technology complexity is also specied. For simplicity of fabrication and design, it is desirable that all nmos threshold voltages and pmos threshold voltages are identical (n v = 1). Increasing the number of distinct threshold voltages incurs proportional escalation of processing or design complexity, requiring for example, 1) additional implant masking steps, or 2) generation and application of multiple tub biases [2] as shown in Figure 1, and 3) migration to a triple-tub process. The net length associated with each node, as dictated by the physical and architectural characteristics of a random logic network, is required for the determination of the interconnect capacitive load driven by each gate. We have employed a complete stochastic wire-length distribution model, derived from rst principles through recursive application of Rent's rule and the principle of conservation of I/O's [4], [5] for net length estimation. In Appendix A we present an accurate model for the calculation of the power consumption and propagation delay in CMOS networks. These models have been extensively validated with HSPICE. 3 Physics of the Device-Circuit Optimization for Minimum Dissipation To illustrate the dynamics of the power minimization process, let us consider a fully loaded static CMOS gate resident in a random logic network and required to operate at a specied clock rate frequency. The desired clock frequency constrains the delay of the gate not to exceed a certain value. The activity factor of the gate is assumed to be known. As the supply voltage is scaled down, the threshold voltage must simultaneously be reduced and the device width increased to maintain a constant speed. While lowering the supply voltage causes the dynamic component of the dissipation to reduce quadratically (as expected), the threshold voltage reduction causes the static or leakage dissipation to increase exponentially. In addition, concurrent increase in device width contributes to larger static dissipation and to some extent prevents the dynamic power component from reducing quadratically. Therefore, the sum total of the static and the dynamic components of dissipation is minimized by a unique choice of supply voltage, threshold voltage and device width values when the sum of the increased static dissipation due to lower threshold voltage and larger device width and the increased dynamic dissipation due to larger device width equals the reduction in the dynamic power due to power supply voltage scaling. These results have been extensively studied and presented in [1]. 4 Algorithm Our goal is to minimize the power consumption, over all gates, of a given CMOS random logic network. The power consumption of each gate is the sum of its static and dynamic power consumption as given by the respective equations in Appendix A.1. As discussed in Appendix A.1, the power consumption of each gate is a non-linear function of V TSi, w i and V dd. The expression for total power consumption of a logic network with N gates is a non-linear expression of N +2 variables, under the assumption that all the gates have the same supply voltage V dd and the same threshold voltage V TSi. This non-linear cost function has to be minimized under the constraint that the sum total of the delays of all the gates in the circuit's critical path(s) must be less than or equal to the desired delay ofthe logic circuit. Let P be the total number of paths considered and let n j be the number of gates in the j th path, j = 1;:::;P. Let E si and E di be the static and dynamic components of the power dissipation of the i th gate in the j th path. The nonlinear optimization P problem can now be stated as i=n Pfollows: Minimize i=1 (Esi + E di) under the constraints nj i=1 t di maxdelay; j =1;:::;P. In the above, note that both the cost function and constraints are highly nonlinear functions. Due to the computational complexity involved, we propose a fast heuristic to solve the optimization problem. This heuristic is based on the observation that the the larger the allowed delay of a single CMOS gate, the lower is the optimum power consumption of the gate for the given delay, over all V TSi, w i and V dd values. Hence, it is clear that any heuristic should attempt to make the total delays of all the circuit paths, including noncritical paths, as close to the critical path delay of the circuit as possible, in order to achieve minimum power consumption. There are four parameters associated with each logic gate, namely, V TSi, w i, V dd and the delay t di. Out of these, the only parameter that can be controlled independently for each gate is w i. In the limiting (and the most practical) case, one must assign the same threshold voltage V TSi and the same supply voltage V dd to all the logic gates. Our heuristic approach then, is to assign delay values to all the logic gates in such a way as to minimize overall power consumption. This eliminates one out of the four variables associated with each gate. We next solve for V TSi, w i and V dd associated with each gate using numerical methods, keeping within the maximum number of distinct threshold and power supply voltages permitted by the technology. (we retain the exibility to use more than one threshold or power supply voltage if desired). 4.1 Activity Estimation We assume that the signal probability and activity proles at the circuit inputs are supplied. In general, such information for a combination circuit can be obtained from activity proling of the architecture in which the circuit is embedded. To calculate the activities at the internal nodes we use the method of transition densities described in [8]. This method of computing the transition density of each circuit node does not take into account input signal correlations

3 and is a rst order approximation to more complex transition density computation algorithms [11]. In the energy and delay equations described in Appendix A.1, the activity factor, a i, is simply the transition density at the output of that operator. 4.2 Determination of Gate Delays In the following, we rst describe our heuristic procedure for assigning delay values to all the logic gates to minimize power consumption. We dene the criticality, N cj, of the j th path from an input to an output of the given CMOS random logic P as the sum i=n of the fanouts of the gates in the path, ie. N cj = j i=1 foij where n j is the number of gates in the j th path, f oij is the fanout of the i th gate in the j th path. The most critical path in the network is dened as the one in which the sum of the fanouts of the gates in that path is the maximum. The specied cycle time (critical path delay) must meet the following criterion, given as, T c t dc b i=n X cp i=1 f oi (1) where, t dc is the delay per fanout of a gate in the critical path, and b 1 is the clock skew factor. In eect, if each gate in this path has the desired t dc, then the delay of each gate is proportional to its fanout. Thus, the delay of the i th gate in the most critical path is, t MAXi = f oit dc = f oi! bt P c i=n cp i=1 f oi If there is more than one path with the same maximum criticality value N cj, then one of the paths is arbitrarily chosen as the most critical path and the above equation used to assign maximum delay values to all the gates in that path. The second most critical path is then determined. There are two possibilities: (a) all the gates in the second path have unassigned maximum delay values or (b) one or more gates in this path have already been assigned maximum delay values. The latter will happen when these gates also belong to other paths with higher criticality values than the path being currently considered. In case (a), Equation 2 is used as before, to assign maximum delay values to all the relevant logic gates. In case (b), the maximum allowable delay of the i th hitherto unconsidered gate in the j th path is determined as, t MAXij = f oij P m=n bt c, dj! m=1 t P MAXm i=n j,n dj i=1 f oij where, n dj (0 n dj n j) is the number of gates which are parts of paths more critical than the current j th path under consideration, i.e. the maximum allowable delay of these gates has already been determined. In eect, the difference between the available clock period and the sum of the maximum delays already assigned to gates of the path is distributed among the remaining gates in the path in proportion to their fanouts. This strategy ensures that the maximum allowable delay of each gate is dictated by the most critical path intersecting that gate. We continue this for the next most critical path, and so on, until all the gates in the (2) (3) network have been assigned a maximum delay value. Procedure 1 outlines the algorithm for the assignment of delays to the gates in the circuit. It can be shown that the assignment of delays using Procedure 1 ensures that there does not exist any circuit path with total delay larger than T c. Procedure 1 Assign Maximum Delays to Gates b clock skew factor for all gates g i do g i unassigned while 9g i unassigned do P j next most critical path n dj number of assigned gates in P j if n dj P1 then m=n T dj A m=1 t MAXm T A 0 for all unassigned gates g i 2 P j do bt t MAXij = f c,ta oij P i=n j,n dj f i=1 oij g i assigned end while Since, the number of paths in a logic network is exponential in the number of gates in the network it is unreasonable, in terms of both time and space, to sort the paths before assigning the delays to each gate. Ju and Saleh [6] have demonstrated ecient algorithms for enumerating the K-most critical paths in the circuit in decreasing order of criticality, where they dene the criticality of a path as the number of gates in the path. We use a modied version of the algorithm in [6], with changes made to incorporate our notion of criticality of paths, which takes O(Knlog(n)) time, where n is the number of gates in the circuit. In practice however, we make some adjustments to Procedure 1. From the equations of Appendix A.2 it is seen that the delay of a logic gate has one component that is dependent entirely upon the maximum of the delays of all the logic gates driving that gate. Consequently, if the assigned delay ofthe driving gate is much larger than the assigned delay of the driven gate, then it may not be possible to nd any combination of V dd, V ts and W i values that satisfy the assigned delay of the driven gate. In this event, some post processing of delay assignments (typically for a very small fraction of the total number of logic gates) is done in order for the heuristic algorithm to be able to nd a solution to the problem without violating the overall delay constraint. 4.3 Optimization for Minimum Power After the maximum delays have been assigned to each gate in the circuit, we optimize each gate individually for minimum power. The strategy is to nd iteratively, using binary search, the optimal combination of V dd, v tsi, and w i for each gate that meets the maximum delay condition while achieving minimum power dissipation. This strategy is based on the observation that power consumption and delay are monotonic functions of V dd, V ts and W i, individually, other parameters being xed. Since it is impractical to have more than one power supply in the circuit, we keep only one global value of V dd. However, we allow the use of multiple threshold values in the circuit if desired. The scheme

4 is outlined in Procedure 2. In the procedure, XRange denotes the range of values that the variable X can take. The subroutine MID(XRange) returns the central value of XRange, while LOWER(XRange) and HIGHER(XRange) return the lower and higher subranges of XRange, splitting it at MID(XRange). The algorithmic complexity of this procedure depends on the number of iteration steps that we allow for convergence to the optimal values. Assuming that each loop runs M times, it takes O(M 3 ) simulations of the entire circuit to obtain the nal optimal values. This is many orders of magnitude lower than the complexity ofany direct or random search algorithm that may be used to search for the optimal solution. The algorithm is outlined below in Procedure 2. Procedure 2 Optimize V dd Range [0:1; 3:3] (Volts) for M steps do V dd MID(V dd Range) v tsrange [0:1; 0:7] (Volts) for M steps do v ts MID(v tsrange) for all gates g i do W Range [1; 100] for M steps do if t d t MAXgi then W Range LOW ER(W Range) W Range HIGHER(WRange) if 8g i : t dgi t MAXgi & Total energy decreased then vtsrange HIGHER(v tsrange) vtsrange LOW ER(v tsrange) if 8g i : t dgi t MAXgi &Total energy decreased then V dd Range LOW ER(V dd Range) Vdd Range HIGHER(V dd Range) To summarize, from the knowledge of the cycle time, T c, delays are assigned to all the gates using Procedure 1. Next, using Procedure 2, we compute V dd, V ts and device width w i values for each gate in the circuit to minimize power consumption while preserving the cycle time constraint. For evaluation purposes, we have also implemented an optimization tool for the above problem using multiple-pass simulated annealing. Our approach performed signicantly better than annealing over all the circuits. The details are omitted for brevity. 5 Results We ran our optimization algorithms on several ISCAS benchmark circuits. In this section we present the results obtained for the algorithms. Table 1 shows the static and dynamic energy consumption of the circuits under minimum total power for two dierent input activities for a xed threshold voltage of 700mV. The energy consumption metrics were obtained by optimizing the device widths and supply voltage to minimize power while meeting a cycle time constraint of 300MHz. It is assumed that the activity levels are the same over all the inputs to the circuit. In practice, however, the input activity levels will be dierent. Table 1 was generated to serve asa basis for comparative evaluation of our power minimization algorithm. Table 2 shows the static and dynamic energy components yielded by our algorithm for all the benchmark logic networks of Table 1. It is seen that the total energy dissipation of the circuits reduces by factors larger than 10 compared to the situation where only the device-widths are varied to decrease the power consumption without any performance loss. It can also be seen that the static and the dynamic power components are approximately equal, thus conrming the previously discussed physics of the optimization process. We note that the savings increase with specied input activity levels. Computation time for these circuits range between 5s and 20s. For reasons of practical utility, the data in Table 2 was obtained assuming the use of a single supply and threshold voltage across all the gates. The values for the threshold voltage returned by the heuristic were in the range of mV while the supply voltages ranged between 600mV and 1.2V. In the case of the optimization with the threshold xed at 700mV, the optimization coincidentally returned V dd values close to 3.3V. We performed experiments to determine the impact of the threshold voltage variation due to process uctuations on the amount ofpower savings possible. We modied our optimization algorithm to use worst-case values of threshold voltage (ie. nominal plus-minus allowed percentage variation) during the delay and power computation. The delay of the optimized circuit is guaranteed to meet the cycle time constraint under the stated threshold variation. The worst case power under the stipulated V ts variation is used to compute the power savings over the benchmark of Table 1 for dierent V ts tolerance values. This data is shown in Figure 2(a) for the circuit s298. We also explored the role of the available cycle time on the power savings obtained for dierent circuits. Figure 2(b) shows the data obtained for s298. Power Savings Power Savings Percentage Variation in Threshold Voltage (a) Power Savings Considering Vth Fluctuations Cycle Time Slack (b) Power Savings Considering Clock Skew Figure 2: Process Variations and Clock Skew Considerations We ran a simulated annealing based algorithm on the benchmark circuits. Though we expect simulated annealing to return a near-optimal solution, in most cases, we nd that it does not perform as well as the proposed heuristic.

5 Input Static Dynamic Total Critical Circuit Gates Depth Activities Energy Energy Energy Delay(ns) s e e e e e e s e e e e e e s e e e e e e s e e e e e e s e e e e e e s e e e e e e s e e e e e e s e e e e e e Table 1: Performance of Benchmark Circuits Circuit Input Static Dynamic Total Critical Activities Energy Energy Energy Delay(ns) Savings s e e e e e e s e e e e e e s e e e e e e s e e e e e e s e e e e e e s e e e e e e s e e e e e e s e e e e e e Table 2: Optimization Results for Heuristic This is because the size of the optimization problem is too large for annealing to converge in a practical amount of time. Hence, the use of the proposed heuristic is well justied. 6 Conclusions and Future Work We have demonstrated a new comprehensive approach to minimizing the sum total of the static and dynamic dissipation components in a CMOS random logic network required to operate at a specied clock frequency. This power minimization is accomplished through the conjoint optimization of both device and circuit designs for a specic logic schematic and activity prole. In particular, we determine the optimal supply voltage for the entire logic module, one or more distinct threshold voltage values for a group of MOS- FET's and a channel width for each transistor that minimizes the total power or the total energy consumption per cycle. It is shown that the new algorithm yields reductions in power by typically a factor of 25 (compared to optimization by changing the device widths and the supply voltages) across a number of benchmark logic networks. Consequently the new power minimization technique provides the following advantages over previous approaches: 1) power reduction is achieved without performance loss, 2) both static and dynamic components are optimized, 3) the algorithm is fast. Moreover, the energy savings are in addition to what is achievable by activity minimization through assorted architectural and algorithmic techniques. Appendix A : Energy and Delay Models The device and circuit optimizations for minimum energy are performed under a required cycle time constraint. Consequently, accurate models of dynamic energy, static energy and signal propagation delay are essential for ecient computation of the optimization cost functions. A.1 Energy Model Equations The equations used to compute the dynamic and static energy dissipations of a gate are described next. Similar models have been presented and analyzed in a recent work by Bhavnagarwala et.al. [1]. It is assumed that the gates are simple multi-input gates with symmetric series or parallel pull-up

6 and pull-down MOSFET congurations. Contributions of subthreshold leakage through the MOSFET channel as well as the leakage across the device drain junctions to static dissipation are included. The short-circuit component ofthe dissipation is neglected since under typical input signal rise time and output load conditions it is an order-of-magnitude smaller than the switching energy [12]. However, these are being incorporated in the next version of the optimization tool. 1. Static Energy Dissipation of the i th Gate (i 2 N): E si = V ddw ii off f c (A1) V dd is the power supply voltage, f c is the clock frequency, I off is the o current per unit feature size device width, w i 1 is the device width in minimum feature size F (adjusting w i scales the widths of all the transistors in the gate). 2. Dynamic Energy Dissipation of the i th Gate (i 2 N): E di = 1 2 aiv dd 2 w i fc PDi +(f ii, 1)C mig X j=f oi + (w ijctij + C INTi j) j=1 (A2) a i 1 is the activity factor of the output node, f ii 1 is the number of inputs, f oi 1 is the number of fanouts, w ij i is the width of the device in minimum feature size at the j th fanout, C PDi is the sum of the overlap, junction and fringing capacitances at the output node per unit feature size device width, C mi is the intermediate node capacitance of series-connected MOSFETs in multi-fanin gates, C tij is the input capacitance per unit feature size width of the MOSFET being driven by the j th fanout, C INTij is the interconnect capacitance load at the j th fanout. A.2 Delay Model Equations We use a transregional model for estimating the worst-case signal propagation delay through a gate. The delay model has been derived using an extension of the alpha-power law saturation drain current model [9] to subthreshold region. The drain current model incorporates eects of high-eld and quasi-ballistic (velocity overshoot) carrier transport in the MOSFET channel. All components of the delay, namely, 1) the delay due to switching MOSFETs, 2) the distributed RC delay of the interconnection, 3) the time of ight delay, 4) the delay component due to the non-zero rise time of the input signal are considered. The unique feature is that the model is \transregional", ie. the model is accurate for both subthreshold (V dd V TSi ) and superthreshold (V dd >V TSi ) operation of the switching MOSFET. By allowing subthreshold switching, we unleash the opportunity for substantial reduction in the supply voltage (and thus, energy and power) in situations where the delay requirement is not very demanding. The superthreshold delay model equations are described below. Similar models are used for subthreshold of operation. Note that the computed delays are the worst case delays through multi-input AND, OR, NAND, NOR gates. Superthreshold Operation Delay ofthe i th Gate (V dd > V TSi ): t di =! 1 2, 1, V tsi V dd 1+ max j 2 (1;f ii) ft dijg + V dd 2[I Diw, f iii off ] + max j 2 (1;f oi) CmiV dd X "CPDi + 1wi j=f oi R INTij w ijc tij CINT ij X j=f ii,1 j=1 1 I Diw(j) (w ijc tij + C INTij ) j=1 + LINT ij v ij # (A3) V tsi is the threshold voltage of the i th gate, t dij is the delay of the gate at the j th fanin, I Diw(f ii) is the switching drain current per unit feature size device width, R INTij is the resistance of the interconnect at the j th fanout, v ij is the eective propagation velocity through the interconnect at the j th fanout, 1 is the pmos to nmos width ratio, 1 2 is the velocity saturation coecient. References [1] Bhavnagarwala, A., De, V., Austin, B., and Meindl, J. Circuit techniques for CMOS low power GSI. In International Symposium on Low Power Electronics and Design: Digest of Technical Papers (Aug 1996), pp. 193{196. [2] Burr, J., and Shott, J. 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