Two Switch Forward. Switching Topology. Figure 1. Switch Mode Topologies vs. Maximum Output Power

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1 APPLYING ISOS IN HIGH-VOLTAGE SWITCH-MODE POWER TOPOLOGIES 1. Introduction Switch-mode power converters often use high-voltage, high-side/low-side gate driver ICs ( HVIC ), which accept logic-level input signals and float (level shift) the high-side driver output to voltages as high as 1,200 VDC. The transistor-based level shift circuits of the HVIC are prone to catastrophic latch-up when output voltage dv/dt exceeds specified limits. This is problematic in several applications, including Class D audio and high-frequency power converters. Moreover, input voltages greater than 72 V require galvanic safety isolation, forcing the designer to add external isolation devices around the HVIC driver circuit. Silicon Labs isolated gate driver family ( ISOdrivers ) offers galvanic isolation and latch-up free, advanced level shifting in a single device. ISOdrivers are available with on-chip isolation rated up to 5 kvac RMS and have the added benefits of high performance and reliability, parametric stability over operating temperature, and integrated protection features. This application note describes the use of ISOdrivers in various switch mode topologies over the output range shown in Figure 1. Primary and secondary side control and associated design trade-offs are also discussed. 1,400+ 1,200 Output Power (W) 1, Single Switch and Active Clamp Forward Two Switch Forward Push Pull Half Bridge Full Bridge Switching Topology Figure 1. Switch Mode Topologies vs. Maximum Output Power Rev /11 Copyright 2011 by Silicon Laboratories

2 2. CMOS Isolation Technology ISOdrivers utilize Silicon Labs' proprietary CMOS isolation technology, which uses a capacitive isolation barrier and reliable on/off keying modulation for robust operation and highly reliable data transfer. Its 60 year+ isolation barrier lifetime offers more than 10 times higher device reliability than optocouplers, with substantial gains in performance and integration. For more information on Silicon Labs CMOS isolation technology, see the Silicon Labs White Paper, CMOS Digital Isolators_WP.pdf: CMOS Digital Isolators Supersede Optocouplers in Industrial Applications available for download at 3. ISOdriver Overview Silicon Labs CMOS isolation technology resides between the ISOdriver input and output as shown in the Highside/Low-side ISOdriver block diagrams of Figure 2. These ISOdrivers are multichip modules that contain three separate dies that isolate the driver outputs from the input and each driver output from the other resulting in very high latch-up immunity. Unlike HVIC drivers, ISOdrivers will not latch-up, even if the relative voltage polarities of two drivers reverse (e.g. low-side driver at a higher voltage than the high-side driver). PWM and two-wire input high-side/low-side ISOdrivers are shown in Figure 2A and 2B respectively and have the following features in common: Flexible 0.5 A or 4 A(pk) drive options Isolation ratings of either 2.5 kvac RMS or 5 kvac RMS User-adjustable linear dead time setting for precise efficiency optimization Overlap protection to ensure both driver output channels cannot be on at the same time Schmitt trigger inputs for high input noise rejection Output drivers isolated from each other for latch-up free operation DISABLE input for driver on/off control (driver outputs are held low when DISABLE is high) Input and output-side under voltage lockouts () for glitch-free system startup and shutdown. PWM DT DISABLE LOGIC, DT TIMER, OVERLAP PROTECTION INPUT DIE GATE DIE A GATE DIE B HS/LS PWM Input ISOdriver A B A B Figure 2. High-Side/Low-Side ISOdriver Block Diagrams GATE DIE A GATE DIE B HS/LS Two Input ISOdriver The PWM input ISOdriver (Figure 2A) internally splits the incoming PWM input signal into separate and control signals and adds delay time if so programmed, then transmits the resulting control signals through the isolation barrier to the output drivers. Operation of the two-input ISOdriver (Figure 2B) is the same, except the and control signals are transmitted through the isolation barrier to the output drivers with added delay time if so programmed. For more information on the Si823x ISOdriver family, see the Si823x data sheet available at DT DISABLE LOGIC, DT TIMER, OVERLAP PROTECTION INPUT DIE A B 2 Rev. 0.1

3 PWM GATE DIE A A GATE DIE A A LOGIC LOGIC DISABLE INPUT DIE A GATE DIE B PWM Input Dual ISOdriver B Figure 3. Dual ISOdriver Block Diagrams GATE DIE B Two Input Dual ISOdriver Dual ISOdrivers (Figure 3A and 3B) differ from the High-side/Low-side drivers of Figure 2 in that they have no overlap protection or dead time generator. This allows both driver outputs to be high or low at the same time for use as dual high-side or dual low-side drivers. Note: Dual ISOdrivers can also be used as high-side/low-side drivers, but the user's system design must ensure that and are never both on at the same time. The single-channel Si822x ISOdriver (see Figure 4) is a 2.5 A isolated, pin-compatible upgrade for optocouplerbased gate drivers (i.e. Optodrivers ) as well as new designs. Like the ISOdrivers of Figures 2 and 3, the Si822x offers the advantages of faster timing, lower input current, higher CMTI, and substantially higher reliability compared to optocoupler-based solutions. Referring to Figure 4, the Si822x input die is powered by a voltage regulator connected across the Anode and Cathode pins and monitored by a current threshold detector with hysteresis. The input-side opto emulator mimics the voltage and current characteristics of an optocoupler LED and causes the current detector to close S1 when minimum current flow is reached. This action turns on the transmitter, causing the receiver to switch the driver output high. Conversely, insufficient anode/cathode current causes the current monitor to disable the transmitter, causing the receiver to switch the driver output low. For more information on the Si822x ISOdriver family, see the Si822x data sheet available for download at DISABLE INPUT DIE B B NC Opto Emulator S1 VREG VDD VDD ANODE CURRENT DETECTOR XMITTR IN RECVR CATHODE INPUT DIE GATE DIE NC Si822x Opto Input Driver Figure 4. Si822x Single Channel Isolated Driver Rev

4 4. Using ISOdrivers The integrated nature of ISOdrivers makes them easy to apply in many switch mode applications. The key design considerations in selecting an ISOdriver are the isolation voltage rating, the required peak gate current drive, and the VDD supply bypassing Isolation Voltage Rating The ISOdriver isolation rating is selected based on its working voltage (i.e. the maximum continuous voltage difference across the ISOdriver while operating). Rated isolation and working voltages are specified in the Si823x and Si822x ISOdriver data sheets and are covered in detail in the application note, AN583: Safety Considerations and Layout Recommendations for Digital Isolators Required Peak Gate Current Drive Peak gate drive current is calculated based on the total gate charge (Q G ) that must be transferred into the total gate capacitance to fully enhance the MOSFET. Q G is the sum of three separate gate charge intervals during MOSFET turn-on shown in Equation 1. Q G = Q GS + Q GD + Q OD Where: Q G is the total gate charge Q GS is the gate-to-source charge Q GD is the gate-to-drain Miller charge Q OD is the overdrive charge after charging the Miller capacitance Equation 1. Total Gate Charge VGS Gate to Source Voltage (V) I D = 2A V DS = 400V V DS = 250V V DS = 100V VG = 12V QGS Total Gate Charge (nc) Figure 5. Gate Charge Characteristics for 400 V MOSFET 4 Rev. 0.1

5 The MOSFET data sheet curve of Figure 5 shows the turn-on characteristics for a 2.5 A, 400 V MOSFET. The required peak gate current is estimated based on the required gate charge at a given gate-to-source voltage (VGS) and the desired transition time (tr) as shown in Equation 2. Example: Q G I G = tr Where: Equation 2. Required Peak Gate Current Using Figure 5, calculate peak gate current for a MOSFET having a VGS of 12 V, and a rise time requirement of 40 nsec. Solution: Referring to the MOSFET manufacturer's data sheet curve shown in Figure 5: Q G =19nC at V GS =12V. From Equation 2: Peak gate current = I G = QG/t = 19 x 10 9 /40 x 10 9 = 0.48 A (0.5 A ISOdriver). For detailed information about calculating gate driver current, see Silicon Labs application notes AN486: High- Side Bootstrap Design Using Si823x ISOdrivers in Power Delivery Systems and AN490: Using ISODrivers in Isolated SMPS, UPS, AC Inverter and Other Power Systems VDD Supply Bypassing Q G is the total gate charge, as defined above V GS is the gate-to-source voltage I G is the peak gate current required to fully enhance the MOSFET tr is the desired gate voltage rise time The VDD inputs of the Si823x ISOdrivers require bypassing with a parallel combination of 1.0 µf and 0. capacitors located as close to the VDD pin as possible. (If used, high-side bootstrap circuits should be placed as close to the corresponding ISOdriver pins as possible.) Rev

6 5. Applications ISOdrivers can be used in a wide range of switching power topologies. Table 1 summarizes the topology examples covered in this application note, the functions ISOdrivers provide in each example, and the recommended ISOdriver part numbers. In all examples in this application note, Controller U1 is assumed to have non-isolated gate drive available at its DRV terminals and low-current logic-level signals available at the terminals. Table 1. Topology Examples Covered in this Application Note SMPS Topology Controller Location Input Voltage (VDC) Isolation Rating (kv RMS ) Primary-Side Driver Type Primary-Side Driver Base Part Number Secondary-Side Driver Type Secondary-Side Driver Base Part Number Single-Switch Forward Primary Side Dual 35 Single-Switch Forward Secondary Side LS Single Si8220/21 Two-Switch Forward Primary Side HS/LS 35 Dual 35 Active Clamp Forward Primary Side HS/LS Si8231/34 Dual 35 Half Bridge Primary Side HS/LS 35 Dual 35 Half Bridge Secondary Side Dual 35 Push/Pull Primary Side Dual 35 PWM Full Bridge Primary Side Dual 35 Dual 35 6 Rev. 0.1

7 5.1. Single-Switch Forward Converter (Primary-Side Control) The single-switch Forward converter (Figure 6) is useful in applications in the 100 W output range and is typically found in moderate power output applications, such as PoE systems, brick power modules, isolated telecom supplies, keep-alive supplies, and industrial systems. It is a simple, low-side drive topology with a maximum duty cycle of 50% to maintain T1 volt-second balance. Transformer T1 is reset by the reset winding, which has the same number of turns as the transformer primary-side winding. (The number of turns is a trade-off between the voltage stress across transistor Q1 and the maximum duty cycle.) Local controller U1 provides low-side drive to main switching transistor Q1 and logic level gate signals to the inputs of Dual ISOdriver U2. Note that Q2 and Q3 are both referenced to secondary-side ground and are driven by dual ISOdriver U2, which provides two functions: primary/secondary safety isolation (mandated by the 400 V input) and low-side gate drive for synchronous FETs Q2 and Q3. The 400 VDC input is within the working voltage specification of the 2.5 kv ISOdriver with adequate margin. The example in Figure 6 can use either the Si8232AB (0.5 A) or AB (4.0 A) 2.5 kv ISOdrivers, depending on the required peak gate drive current. For more information on calculating peak gate drive current, see "4. Using ISOdrivers" on page 4. RESET Winding N1 T1 L1 VIN (400 VDC) VDD1 U1 Controller D1 N1 N2 Q3 C1 VDD DRV Q1 U2 A Q I B 0. Figure 6. Single-Switch Forward Converter (Primary-Side Control) Rev

8 5.2. Single-Switch Forward Converter (Secondary-Side Control) Secondary-side control is often preferred over primary-side control because the feedback signal resides on the same ground as the controller, eliminating the need for an optocoupler and resulting in faster control loop response. Figure 7 shows the forward converter of Figure 6 using secondary-side control. As shown, the secondary-side controller provides low-side gate drive to synchronous FETs Q2 and Q3 while the ISOdriver, U2, provides gate drive to the primary-side switching transistor as commanded by controller U1. In this example, U2 provides safety isolation and primary-side gate drive in a single 8-pin package. L1 VIN (400 V) D1 Q1 T1 U2 Si8220/ Si8221 VDD2 Controller VDD U1 Q2 Q3 C1 (12 V) LOAD VDD Vo Vo ANODE R1 DRV DRV VSS CATHODE Figure 7. Single-Switch Forward Converter (Secondary-Side Control) The Si8220/1 is an ideal single-channel gate driver for use in new designs or as a functional upgrade for optocoupler-based gate drivers, such as the HCPL-0302, HCPL-3120, TLP350, and similar devices. This device offers 60 ns propagation delay max independent of input drive current, 14x tighter part-to-part matching versus opto-drivers, and common-mode transient immunity (CMTI) of 30 kv/µs. The example of Figure 7 requires that the ISOdriver be rated at 2.5 kv. This design can use either the 0.5 A (Si8221x) or 2.5 A (Si8220x) ISOdriver, depending on the required peak gate drive current. For more information on calculating peak gate drive current, see the second paragraph in "4. Using ISOdrivers" on page 4. 8 Rev. 0.1

9 5.3. Two-Switch Forward Converter Weaknesses of the single-switch forward converter of Figure 6 include a 50% maximum duty cycle limitation and high-voltage stress on power switch Q1 when off. Adding a second switch on the high side causes the stress on each MOSFET to be clamped to the input voltage, effectively recycling energy back to the input for increased efficiency. Also, the addition of the second switch enables the two-switch version to produce up to four times the output power of the single-switch version. The two-switch forward high-side bootstrap can be problematic at low duty cycles since both Q1 and Q2 are off and there is no return path from the bootstrap to ground. This issue is eliminated using high-voltage transistor Q5 to ground the low-side of CB1 when Q1 and Q2 are not conducting. The voltage rating of Q5 must be high enough to withstand VIN with sufficient voltage margin to spare. The two-switch forward converter of Figure 8 uses two high-side/low-side ISOdrivers; U2 drives the primary-side transistors, Q1 and Q2, and U3 drives the secondary-side synchronous FETs, Q3 and Q4. The 800 V input requires both ISOdrivers to have an isolation rating of 5 kvrms. This design uses the Si8232BD (0.5 A) or BD (4.0 A) ISOdrivers for U2 and U3, depending on the required peak gate drive current. For more information on calculating peak gate drive current, see "4. Using ISOdrivers" on page 4. VIN (800 V) U1 U2 Controller VDD DRV CHRG 0. I A CB1 CHRG D3 Q5 B D1 D2 Q1 Q2 Q3 Q4 L1 C1 (50 V) U3 Si8232 A 0. I B Figure 8. Two-Switch Forward Converter Rev

10 5.4. Active Clamp Forward Converter Forward topologies do not inherently reset the transformer each switching cycle like symmetrical topologies, such as push-pull, half-bridge and full-bridge. While a number of different reset mechanisms have been employed in forward converters, the active-clamp reset offers the best combination of benefits: The active clamp supports cycle-by-cycle transformer reset without an additional reset winding or dissipative clamp. The active clamp provides increased maximum duty-cycle, allowing a higher input voltage range or higher transformer turns ratio for a wider VIN range. Energy stored in parasitic elements is transferred back to a resonant clamp circuit and recycled, resulting in higher efficiency and lower noise. Switching voltage is clamped to a controlled level reducing switching device voltage stress. Controller U1 provides low-side drive timing to dual ISOdriver U2, which, in turn, provides gate drive for the main switching transistor, Q2, and the active clamp transistor, Q1. ISOdriver U2 provides the necessary level shift for high-side bootstrap circuit D1,CB1 to drive Q1. ISOdriver U3 provides primary/secondary safety isolation of 2.5 kv RMS (due to the 200 V input) and provides low-side gate drive to synchronous transistors Q3 and Q4. The user can select the Si8231AB (0.5 A) or Si8234AB (4.0 A) ISOdrivers for U2 and the Si8232AB (0.5 A) or (4.0 A) for U3, depending on the required peak gate drive current. For more information on calculating peak gate drive current, see "4. Using ISOdrivers" on page 4. U1 Controller VDD VIN (200 V) RDT 0. PWM DT I U2 Si8231/ Si8234 CB1 A D1 VDD2 Q1 B C1 Q2 T1 Q3 Q4 L1 C (24 V) RDT 0. I U3 VDD2 DT A VDD2 B Figure 9. Active Clamp Forward Converter 10 Rev. 0.1

11 5.5. Half Bridge Converter (Primary-Side Control) Half-Bridge topology (Figure 10) is commonly used in applications requiring 200 to 1200 W of output power. Typical applications include isolated telecom and networking power systems, server power supplies, plasma display systems, and motor drives. The primary-side controlled, half-bridge converter of Figure 10 uses largevalue, input bulk capacitors C1 and C2 to maintain a voltage of approximately 0.5 VIN at transformer T1. The transformer primary voltage is therefore +0.5 VIN when transistor Q1 is on, and 0.5 VIN when transistor Q2 is on. Note that Q1 and Q2 see only half of VIN, allowing the use of lower voltage (lower cost) transistors. C1 Q1 L1 VIN (800 V) C2 0.5 x VIN U1 Controller VDD 0. U2 A I B CB1 Q2 T1 U3 Q3 Q4 L2 C (5 V) 0. A I B 15V 15V Figure 10. Primary-Side Controlled Half Bridge Converter with Output Current Doubler Like the forward converters described earlier, ISOdriver U2 (Figure 10) operates as a non-isolated, high-side/lowside gate driver for Q1 and Q2, respectively. The secondary-side circuit of Figure 10 is a current doubler consisting of transistors Q3 and Q4 and output inductors L1 and L2 and provides two major benefits: 1) output current is doubled since the entire secondary-side transformer winding is applied to each switching period, and 2) Q3 and Q4 can be low-side driven, eliminating the need for a bootstrap or floating supply. The two-input ISOdrivers were chosen for both U2 and U3 to allow the controller to actively control the dead time of both primary-side switching transistors Q1 and Q2 and synchronous FETs Q3 and Q4 for optimum efficiency. The 800 V input mandates an ISOdriver rating of 5 kv RMS. ISOdrivers U2 and U3 can use either the Si8232BD (0.5 A) or BD (4.0 A) ISOdrivers, depending on the required peak gate drive current. For more information on calculating peak gate drive current, see the second paragraph in "4. Using ISOdrivers" on page 4. Rev

12 5.6. Half Bridge Converter (Secondary-Side Control) Secondary-side control is often preferred over primary-side control because the feedback signal resides on the same ground as the controller, eliminating the need for an optocoupler and resulting in faster control loop response. The secondary-side control half-bridge of Figure 11 demonstrates a reduction in component count as well. C1 Q1 VIN (800 V) C2 0.5 x VIN T1 Q3 Q4 L1 C RA (5 V) Q2 CB2 A U2 PWM U1 Controller DRV VDD DRV FB RB DT RDT 0. B I Figure 11. Secondary-Side Controlled Half Bridge Converter As shown, the secondary-side system controller provides low-side drive to synchronous FETs Q3 and Q4 and the PWM signal to the ISOdriver U2 input. In this example, U2 provides high-side/low-side drive for primary-side switches Q1 and Q2, 5 kv RMS safety isolation, and user-optimized dead time delay in a single device. This design can also use the Si8232BD (0.5 A) or BD (4.0 A) ISOdrivers, depending on the required peak gate drive current. For more information on calculating peak gate drive current, see the second paragraph in "4. Using ISOdrivers" on page Rev. 0.1

13 5.7. Push-Pull Converter Push-pull converters are useful over a wide range of output power up to 1,000 W. Typical applications include telecommunications systems, server power supplies, high-density power modules, and industrial system power supplies. The push-pull converter of Figure 12 is a simple design that scales well with increased power output levels. These converters typically exhibit low primary-side conduction losses since only one transistor is connected to VIN at any time. The controller applies alternating low-side drive to transistors Q1 and Q2, each for an identical length of time, such that the volt-second balance is maintained across the transformer, preventing saturation. In this example, the controller directly drives the primary-side transistors, Q1 and Q2, and provides gate drive timing to dual ISOdriver U2, which functions as an isolated dual low-side driver for Q3 and Q4. With VDD2 at 24 V, the ISOdriver output swing is more than adequate to fully enhance Q3 and Q4, given the converter's 5 V output. This design can use the 2.5 kvrms rated Si8232BD (0.5 A) or BD (4.0 A) ISOdrivers, depending on the required peak gate drive current. For more information, see "4. Using ISOdrivers" on page 4. T1 Q3 L1 C1 (5 V) U1 Controller VDD DRV Q1 VIN (400 V) DRV U2 A B Q2 Q4 I Figure 12. Push-Pull Converter Rev

14 5.8. Full-Bridge Converter Full-Bridge topology is most often used in very-high-power systems from 400 W to kilowatts. Typical applications include telecom rectifier supplies, data center backup supplies, industrial UPS systems, etc. Full-bridges readily accept different control and modulation schemes (e.g. PWM, ZVS phase-shift modulation) and while the example in Figure 13 assumes no specific modulation scheme, ISOdrivers can be used in virtually all modulation scenarios. For example, a PWM modulated full bridge might use high-side/low-side drivers on the primary to take advantage of the overlap protection and programmable dead time, whereas a ZVS phase-shift-modulated full-bridge would most likely use dual ISOdrivers since the gate drive phases naturally overlap. The block diagram in Figure 13 shows one possible full-bridge control and gate drive implementation (other implementations are possible and may use fewer components, depending on the end application). Controller U1 supplies logic level gate timing signals to the high-side/low-side ISOdrivers, U2 and U3, which function as primaryside level shift drivers. ISOdriver U4 is used as a safety-isolated, dual low-side driver for the synchronous transistors in the secondary-side current doubler circuit. The 400 V input allows for the use of an isolation rating of 2.5 kv RMS for safety; so, the user can select either the Si8232AB (0.5 A) or AB (4.0 A) ISOdrivers (the 4.0 A driver is usually selected in full bridge topologies due to the increased gate capacitance of larger MOSFETs or IGBTs). For more information on calculating peak gate drive current, see "4. Using ISOdrivers" on page 4. VIN 400 VDC U1 Controller VDD 0. U2 CB1 A I B 0. U3 Q1 Q2 Q3 T1 Q5 Q6 L1 CO (3.3 V) 0. CB2 A I B Q4 U4 A I B L2 Figure 13. Full-Bridge Converter 14 Rev. 0.1

15 6. Summary Silicon Labs ISOdrivers use proprietary isolation technology that provides substantial gains in timing performance, reliability, operating stability over temperature, physical size, and installed cost. ISOdrivers are highly versatile and available in high-side/low-side, dual, and single-channel configurations. ISOdrivers have none of the duty cycle limitations imposed by gate drive transformers and substantially better overall performance and reliability compared to optodrivers. These attributes enable ISOdrivers to be used in virtually all isolated switch-mode power systems. 7. Related Documents AN490: Using ISOdrivers in Isolated SMPS, UPS, AC Inverters and Other Power Systems AN486: High-Side Bootstrap Design Using Si823x ISOdrivers in Power Delivery Systems AN441: Using the 5/6 Dual ISOdrivers in Power Delivery Systems AN486: High-Side Bootstrap Design Using Si823x ISOdrivers in Power Delivery Systems AN490: Using ISODrivers in Isolated SMPS, UPS, AC Inverter and Other Power Systems AN497: Adding Over current Protection to ISOdrivers AN583: Safety Considerations and Layout Requirements for Digital Isolators Silicon Labs White Paper: CMOS Digital Isolators_WP.pdf; Title: CMOS Digital Isolators Supersede Optocouplers in Industrial Applications Rev

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