Application Range Analysis and Implementation of the Logic-Processed CPS-PWM Scheme Based MMC Capacitor Voltage Balancing Strategy

Transcription

1 CPSS TRANSACTIONS ON POWER EECTRONICS AND APPICATIONS, VO. 4, NO., MARCH 29 Application Range Analysis and Implementation of the ogic-processed CPS-PWM Scheme Based MMC Capacitor Voltage Balancing Strategy Kun Wang, eyuan Zhou, Yan Deng, Yi u, Chaoliang Wang, and Feng Xu Abstract Fundamental frequency sorting algorithm (FFSA) is outstanding for the MMC capacitor oltage balance due to the reduced computational burden and elimination of arm current detection. Howeer, with the traditional carrier-phase-shifted pulse width modulation (CPS-PWM) scheme, FFSA will be ineffectie when the carrier frequency is higher than 25 Hz, where the line frequency is 5 Hz. Thus, preious works proposed a logicprocessed CPS-PWM scheme to oercome this disadantage. This paper furtherly introduces the application ranges and implementation of this logic-processed CPS-PWM scheme based capacitor oltage balancing method in detail. With a detailed mathematical analysis, the factors that influence the balancing strategy s conergence speed are obtained, i.e., modulation index and power factor angle. It is found that in the applications where the modulation index is usually higher than.75, the influence of the modulation index is negligible. Howeer, when the power factor angle is closed to ±/2, the conergence speed is almost zero. Therefore, by comparing with the traditional CPS-PWM scheme based FFSA balancing method, the application ranges of power factor angle are reealed to guarantee a high conergence speed. Meanwhile, the balancing strategy s application scope is specified. Moreoer, a three-tier control architecture is demonstrated, where the logic process of driing signals and capacitor oltage sorting process are both executed in the middle-tier FPGA controller. This centralized scheme guarantees the synchronization of switching actions. And the logic process is easy and cost-effectie in FPGA. Simulation and experimental results are presented to alidate the theoretical analysis. Index Terms Balancing strategy, conergence speed, FFSA, logic-processed CPS-PWM, modular multileel conerter. I. Introduction MODUAR multileel conerter (MMC) has attracted great attention due to its modularity, high efficiency and scalability []-[3]. With these adantages, MMC is promising Manuscript receied January 22, 29. This work is supported by National Key R&D Program of China (27YFB93), Science and Technology Projects of State Grid Corporation of China (524743). This paper was presented in part at the 28 IEEE International Power Electronics and Application Conference and Exposition (PEAC), Shenzhen, China, Noember 28. K. Wang,. Zhou, and Y. Deng are with the College of Electrical Engineering, Zhejiang Uniersity, Hangzhou 327, China ( wkun@ zju.edu.cn; zlyuan@zju.edu.cn; dengyan@zju.edu.cn). Y. u, C. Wang, and F. Xu are with the State Grid Zhejiang Electric Power Research Institute, Hangzhou 34, China ( lu_yi5@zj.sgcc.com.cn; chaoliangwang@26.com; xuf_988@63.com). Digital Object Identifier.24295/CPSSTPEA.29. in medium- and high-oltage applications. Researches on modulation schemes, oltage balancing strategies and circulating current suppression strategies hae been widely carried out [4]- [7]. Capacitor oltage balancing of sub-modules (SMs) is ital for the stable operation and performance of MMC. Different kinds of oltage balancing methods hae been presented in the literature. Among them, the open-loop balancing method requires no measurement of the capacitor oltages, which simplifies the design of the control system and reduces the cost [8]. Howeer, its dynamic performance is poor. Sorting and selecting method is one of the most commonly used methods, which sorts the capacitor oltages at first and then inserts proper SMs according to the sorting result and the arm current direction [9]. Although this method is easy to implement, the high frequency sorting process leads to heay computational burden and excessie switching actions. A reduced switchingfrequency oltage balancing strategy was proposed in [] to reduce the switching actions of SMs. But the sorting frequency of this method is still high. Fundamental frequency sorting algorithm (FFSA) based balancing strategy is proposed in [], which aoids the excessie switching actions and effectiely reduces the sorting frequency to fundamental frequency. So, a large amount of computing resources is saed. Further studies on FFSA hae been carried out in [2]-[4] under different modulation schemes, such as carrier-phase-shifted pulse width modulation (CPS-PWM), nearest leel (N) modulation and phase disposition PWM (PD-PWM). And it is found in [4] that, with CPS-PWM scheme, FFSA based balancing strategy will no longer feasible when the carrier frequency is higher than 25 Hz, where the line frequency is 5 Hz. This is caused by the little difference in the charging ability among different driing signals. Therefore, an improed balancing strategy is proposed in [4]-[5] based on the logic-processed CPS-PWM scheme. In the improed balancing strategy, driing signals with proper phase angle difference are processed by logic AND/OR process to synthesize new driing signals with obiously charging ability difference. Subsequently, the FFSA can balance the capacitor oltage under high-frequency CPS-PWM. Howeer, the conergence speed and application ranges of the proposed balancing strategy is not analyzed in detail. In this paper, the conergence speed of logic-processed CPS-PWM scheme based MMC capacitor oltage balancing strategy is analyzed in detail. It is found that the conergence

2 2 CPSS TRANSACTIONS ON POWER EECTRONICS AND APPICATIONS, VO. 4, NO., MARCH 29 +V dc/2 I dc Upper Arm V cseq D seq N seq cseq SM SM SM ua V ch D h N k ck V ci D i N l cl O i ua A i la i ub B i lb i uc C i lc s i sa isb i sc s s sa sb sc N V cj acending D j N m cm descending -V dc/2 la SM SM SM S D S 2 C ower Arm D 2 Fig.. Structure of a typical three-phase grid-connected MMC. Vc Fig. 2. Principle of fundamental frequency sorting algorithm. can be synthesized by properly inserting a certain number of SMs in upper and lower arms. speed is influenced by the modulation index and power factor angle. While, as reealed in this paper, in the applications where the modulation index is usually higher than.75, the influence of modulation index is negligible. Howeer, when the power factor angle is closed to ±/2, the balancing strategy becomes infeasible because the conergence speed is too slow to balance the capacitor oltage. By comparing with the traditional CPS- PWM scheme based FFSA balancing method, the application ranges of power factor angle are reealed. Consequently, the proposed balancing method s application scope is specified. It is especially suitable for the high oltage direct current (HVDC) transmission, but not suitable for applications such as static synchronous compensator (STATCOM), which mainly generate or absorb reactie power. Moreoer, a three-tier control architecture is also presented, where the logic-processed CPS-PWM is centralized in the middle-tier FPGA controllers for each phase. Thus, the synchronization of switching actions is guaranteed, and the logic process can be accomplished easily and cost-efficiently. This paper is organized as follows. The principles of logicprocessed CPS-PWM scheme based capacitor oltage balancing strategy are presented in Section II. In Section III, the conergence speed is analyzed in detail, and the application ranges of power factor angle are reealed subsequently. The three-tier control architecture is demonstrated in Section IV. Simulation and experimental results erify the theoretical analysis in Section V. Finally, Section VI draws the conclusion. II. ogic-processed CPS-PWM Scheme Based Voltage Balancing Strategy With FFSA A. Structure of MMC A typical structure of three-phase grid-connected MMC is illustrated in Fig., where each phase leg is comprised of two arms. In each arm, N SMs and one inductor are connected in series. The SM consists of two IGBT switches and one capacitor. When S is on, the SM is inserted. And it is bypassed when S 2 is on. Thus, the output oltage of SM aries between V c and zero, where V c is the capacitor oltage. The output oltage B. Traditional CPS-PWM Scheme Based Balancing Strategy With FFSA The basic principle of FFSA is firstly introduced in []. In this algorithm, the capacitor oltage ariations of SMs in the preious fundamental period are calculated and sorted in ascending order at the fundamental frequency. In Fig. 2, ΔV ch, ΔV ci, ΔV cj represent the oltage ariations of SM h, SM i and SM j, and ΔV cseq stores the sorting result. The oltage ariations sorting result reflects the charging ability of each SM s driing signal assigned to them in the preious fundamental period. Subsequently, the driing signals sequence, namely D seq, is obtained in ascending order regarding to their charging ability. Meanwhile, the capacitor oltages are sorted in descending order, obtaining the oltage sequence labeled as cseq. Symbols ck, cl, and cm represent the capacitor oltage of SM k, SM l and SM m, respectiely. And N seq stores the corresponding number of the SMs. So far, the relationship between driing signals and SMs can be rebuilt with the balancing strategy going like this: in the following fundamental period, driing signal which has the lowest charging ability will be assigned to SM with the highest capacitor oltage, e.g., D h is assigned to SM-N k, while driing signal which has the highest charging ability will be assigned to SM with the lowest capacitor oltage, e.g., D j is assigned to SM- N m. Thus, the capacitor oltage can be well balanced. Howeer, in this scenario, the charging ability of driing signals is related to the CPS-PWM carrier frequency. As illustrated in Fig. 3, N carriers are compared with the modulation signal aref to generate driing signals for the lower arm of phase A. Taking S x as an example, which is generated by the x th carrier, the Fourier expression of S x can be deried as: where m is the modulation index, is the angular frequency of modulation signal, c is the angular frequency of carrier, θ is the phase angle of the modulation signal, θ cx is the initial phase angle of x th carrier and A mn is the amplitude of harmonic ()

3 K. WANG et al.: APPICATION RANGE ANAYSIS AND IMPEMENTATION OF THE OGIC-PROCESSED CPS-PWM SCHEME 3 θ cx S x S y S or x th y th aref = m cos(t + θ ) t t t t S() S(N d ) S(N d +) S(N-N d ) S(N-N d +) S(N) P () P (N d ) P U (N d ) P U () N seq () N seq (N d ) N seq (N d +) N seq (N-N d ) N seq (N-N d +) N seq (N) ΔV Nd+ ΔV Nd ΔV S and t Fig. 4. ogic process and assignment of the driing signals. Fig. 3. Illustration of CPS-PWM and logic processing of driing signals. component, in which m is the carrier harmonic index and n is the carrier sideband harmonic index (m =, 2, 3, and n =, ±, ±2, ). So the oltage ariation caused by the x th carrier during one fundamental period can be calculated as: where i la is the lower arm current of phase A and V, V 2 and V 3 represent the oltage ariations caused by carrier harmonics and their sidebands that oerlap the DC component, the fundamental component and the secondary harmonic, respectiely. As presented in [4], if the line frequency is 5 Hz, when the carrier frequency is higher than 25 Hz, the charging abilities of each driing signal are all near to zero, which leads to the failure of balancing strategy based on traditional CPS- PWM scheme with FFSA. C. ogic-processed CPS-PWM Scheme Based Balancing Strategy With FFSA In order to synthesize driing signals with obiously different charging ability when the carrier frequency is higher than 25 Hz, the logic-processed CPS-PWM scheme is proposed. As depicted in Fig. 3, carrier x and carrier y are selected in pairs as an example. Driing signal S or is the logic OR process result of S x and S y, and S and is the result of logic AND process of S x and S y. As proed in the next section, the logic-processed driing signals, S or and S and possess obiously different charging ability with each other. So the logic-processed CPS-PWM scheme based balancing strategy with FFSA can be executed as follows. Firstly, the sorting process of capacitor oltages is operated at fundamental frequency with the corresponding SM s number sequence stored in N seq, as illustrated in Fig. 4. The oltage differences of each SM-pair can be obtained simultaneously, where the SMs are combined in pairs by the following rules: SM with the highest capacitor oltage is combined with the SM with lowest capacitor oltage, and the second highest SM is combined with the second lowest SM, and so on. In this paper, 2% of the rated capacitor oltage is set as the threshold to determine whether the SMs are in balance state or not. If the oltage difference oerreaches this threshold, it means that the corresponding SM-pair is in unbalance state. As shown in (2) Fig. 4, assume there are N d pairs of SMs in unbalance state, i.e., oltage differences of the highest N d SMs and the lowest N d SMs (ΔV ~ ΔV Nd ) exceed the threshold. Accordingly, N d pairs of driing signals with proper phase angle difference are selected in S(i) and S(N-i+), where i =, 2,, N d. And the rest driing signals are stored in S(N d + ) to S(N-N d +), which are directly assigned to the SMs in balance state. P (i) and P U (i) represent the logic process of driing signal pairs as defined in (3) and (4), where min{} means selection of the driing signal with lower charging ability, and max{} means selection of the driing signal with higher charging ability. And then, P (i) is assigned to SM-N seq (i), while P U (i) is assigned to SM-N seq (N-i + ). Consequently, the capacitor oltages can conerge back to the balance state. III. Conergence Speed and Application Range Analysis It is clear that the charging ability difference between driing signals is the key to balance the capacitor oltages. The oltage balancing strategy may be deactiated when the charging ability difference is not so obious. Thus, the conergence speed is analyzed in this section and the application range is reealed. A. Conergence Speed Analysis Similar to the traditional CPS-PWM scheme, the Fourier expression of S or and S and can be obtained and the oltage ariations caused by them in one fundamental period can be deried as follows: (3) (4) (5)

4 4 CPSS TRANSACTIONS ON POWER EECTRONICS AND APPICATIONS, VO. 4, NO., MARCH 29 where I sm is the amplitude of output phase current, θ is the power factor angle, θ xy is the phase angle difference of carrier x and y, and φ xy is calculated as follows: It should be noticed that the oltage ariations caused by the carrier sideband harmonic are neglected in (6) since they are ery small when the carrier frequency is high. Moreoer, because the driing signals are logic processed in pairs and assigned to the SM-pairs simultaneously, the conergence speed of capacitor oltage can be ealuated by the difference of ariations caused by S or and S and as shown in (8). Furtherly, since the second part of (5) and (6) is also small enough to be neglected, only the first part of the oltage ariations is considered for simplification. Thus, V can be simplified as follows: It can be obsered that the conergence speed is determined by actie current component I sm cos θ, modulation index m and carrier phase angle difference θ xy. By the partial differential operation of θ xy and φ xy, the following equation can be obtained as: (6) (7) (8) (9) () Assuming () to be zero, it can be deried that V achiees its maximum alue when θ xy = and φ xy = /2. Consequently, the maximum conergence speed V max can be calculated as: max cos θ cos θ cos θ () ΔVmax* ΔVmax* m Normalized by I sm /C, the relationship of V max *, m and θ is illustrated in Fig. 5. It can be obsered that the balancing strategy has the highest conergence speed when θ equals to or ±. While it reaches the lowest speed when θ equals to ±/2. And it can be seen from Fig. 5(b) that when m is higher than.75, m has little influence on the conergence speed. Thus, only the application range of power factor angle θ needs to be analyzed in the next subsection. B. Application Range Analysis.7.6 -/2.5 - θ (a) m =.95 m =.8 m =.9 m =.7 (b) m =.6 m =.5 It is presented in [4] that the balancing strategy s conergence speed will be degraded when there is reactie power transferred. Howeer, the acceptable application range of power factor angle is not clearly specified. It is reasonable to take the conergence speed of traditional CPS-PWM based balancing strategy as the reference to analyze the application ranges of the proposed strategy. As demonstrated aboe, the traditional CPS-PWM based balancing strategy s conergence speed slows down with the increase of carrier frequency and eentually becomes infeasible when the carrier frequency is higher than 25 Hz. But it can still offer considerable speed when the carrier frequency is 5 Hz [4]. Therefore, the conergence speed of traditional CPS-PWM based balancing strategy with 5Hz carrier frequency is taken as the lowest acceptance of conergence speed for the proposed balancing strategy. Based on the expansion of (2), the maximum and minimum /2 - - /2 /2 θ Fig. 5. Influence of power factor angle θ and modulation index m on the normalized conergence speed V max *.

5 K. WANG et al.: APPICATION RANGE ANAYSIS AND IMPEMENTATION OF THE OGIC-PROCESSED CPS-PWM SCHEME 5 m =.95 m =.75 m =.85 m =.65 m =.55 approximation.7 m =.95 m =.8 m =.9 m =.7 m =.6 m = ΔVcl5Hzmax*.3.2 ΔVmax* Application range Application range Application range - -2/3 - /3 /3 2/3 θ - -2/3 - /3 /3 2/3 θ Fig. 6. Conergence speed V cl5hzmax * ersus the power factor angle θ and the modulation index m. Fig. 7. Application ranges of power factor angle for logic-processed CPS-PWM scheme based balancing strategy. capacitor oltage ariations generated by the driing signals with 5 Hz carrier frequency are calculated as (2). Hzmax Hzmin (2) P * Q * Main Controller Dual-loop control Aref Bref Cref Phase Controller ogic- Processed CPS-PWM &Voltage Balancing Strategy +V dc /2 c D SM SM SM Controller N where θ cx is the phase angle of carrier x, x = mod (round ( + N (θ c - 3θ + θ )/2), N), θ cx2 is the phase angle of carrier x 2, x 2 = mod (round ( + N(θ c - 3θ + θ - )/2), N). And A (-2) is the harmonic amplitude, which can be calculated as: sa sb sc i sa i sb i sc -V dc /2 (3) Thus, the maximum conergence speed with 5 Hz carrier frequency can be represented by V cl5 Hz max as follows: (4) Normalized by I sm /C, the relationship of V cl5hzmax *, m and θ is illustrated in Fig. 6, where θ c =, θ =, and N = 2. Fig. 6 shows that, for the traditional CPS-PWM based balancing strategy, the conergence speed is mainly determined by m. Compared to the logic-based CPS-PWM based strategy, when the modulation index m is higher than.75, its normalized conergence speed is always aboe.3. Therefore, V max * =.3 is taken as the lowest acceptable conergence speed of the proposed balancing strategy. It can be calculated from () or read from Fig. 5(b) that the logicprocessed CPS-PWM scheme based oltage balancing strategy reaches a normalized conergence speed of.3 when θ ±/3 and ±2/3. Hence the conclusion can be drawn that the application range of power factor angle is θ [-/3, /3] [-, -2/3] [2/3, ]. Fig. 7 illustrates the application ranges. Thus, it can be inferred that the proposed strategy is especially suitable for the HVDC Fig. 8. The three-tier control architecture for logic-processed CPS-PWM based balancing strategy. transmission, which mainly deals with actie power and has a modulation index higher than.75. IV. Implementation of the ogic-processed CPS-PWM Based Balancing Strategy In the logic-processed CPS-PWM scheme, the manipulation of driing signals should be achieed without affecting the synchronization of switching actions among SMs. Otherwise, distorted oltage leels and defected arm currents will be induced [6]. As demonstrated in Fig. 8, a three-tier control system architecture is proposed. The control system is diided into three parts: the main controller, phase controllers and submodule controllers. The main controller is one DSP controller, which is responsible for the high-leel controls, such as actie and reactie power control. The phase controller utilizes FPGA as the control unit, which carries out the logic-processed CPS-PWM scheme based capacitor oltage balancing strategy. Since the generation and manipulation of driing signals are centralized in the middle-tier controller, the synchronization of switching actions is naturally guaranteed. Moreoer, the logic process of driing signals is easy and cost-effectie in FPGAs. The SM controllers only receie control signals from the phase controllers and report the capacitor oltage to the phase controllers.

6 6 CPSS TRANSACTIONS ON POWER EECTRONICS AND APPICATIONS, VO. 4, NO., MARCH 29 TABE I Parameters of Simulation and Prototype ia(a/di) a(5v/di) Prototype Enable Simulation flag Parameters t=.s VclA~2(V/di) 8.3 V=29.V.35 a(5v/di) Vripple=34.2V 5 (a).5 t(s).55 ia(a/di) In order to erify the theoretical analysis, a 2-leel threephase grid-connected inerter is built in MATAB Simulink and a 9-leel three-phase grid connected prototype is established. The parameters of simulation and prototype are shown in Table I. And the carrier frequency (switching frequency) is set as 45 Hz for both simulation and experiment. Enable V. Simulation and Experimental Verification flag VclA~2(V/di) 8 A. Simulation Results.3 V=29.8V.35 a(5v/di) Vripple=36.6V 5.5 (b).55 t(s) ia(a/di) Enable flag t=.2s VclA~2(V/di) 8.3 V=22.8V.35 a(5v/di) Vripple=43.V 5 (c).5 t(s).55 ia(a/di) Enable flag Dual-loop control is adopted in the simulation, where the outer loop controls the actie and reactie power and the inner loop controls the actie and reactie current. The carrier phase angle difference for the logic processed driing signals is selected according to [4], so new driing signals with proper charging ability can be synthesized. Simulation results with different power factor angles are presented in Fig. 9(a)-(c). The output oltage, output current, enable flag and execution flag of balancing strategy, and the lower arm capacitor oltages of phase A are presented successiely. In order to erify the effectieness of the balancing strategy, the capacitor oltages should be dierse at the initial state. Therefore, the balancing strategy is disabled at first, and the logic processed driing signals are intentionally assigned to specific SMs to charge and discharge the capacitors. This process is not illustrated in Fig. 9. After a preset timespan, the SMs are in unbalance state and they are re-assigned with their original driing signals. At the meantime, the balancing strategy is still disabled. As obsered in Fig. 9(a)-(c), with the original high frequency driing signals, the capacitor oltages keep unchanged. This is because there is little difference in the charging ability of original driing signals, which erifies the theoretical analysis. The balancing strategy is enabled at.3 s. And it can be seen from Fig. 9(a)-(c) that the capacitor oltages conergence speeds are different with different power factor angles. Fig. 9(d) is the simulation result of the traditional CPS-PWM scheme based balancing strategy with 5 Hz carrier frequency, and its power factor angle is /3. t=.2s t=s VclA~2(V/di) 8 V=223.5V.3.35 Vripple=42.2V t(s) (d) Fig. 9. Simulation results. (a) power factor angle θ = with 45 Hz logic processed CPS-PWM, (b) θ = /6 with 45 Hz logic processed CPS-PWM, (c) θ = /3 with 45 Hz logic processed CPS-PWM, (d) θ = /3 with 5 Hz traditional CPS-PWM.

7 K. WANG et al.: APPICATION RANGE ANAYSIS AND IMPEMENTATION OF THE OGIC-PROCESSED CPS-PWM SCHEME 7 TABE II Comparison of Simulation Results i A, 2A/di Balancing Strategy ogic Processed CPS-PWM Traditional CPS-PWM A, 5V /di cla, 2V/di cla5, 2V/di 5ms /di V ripple =8.7V V c_ag =97.5V V=33V cla8, 2V/di flag flag3 t=.s Enable flag (a) 5ms/di Key performance characters of the simulation results are concluded in Table II. When the power factor angle θ changes from to /6, i.e., actie power is still the major power component, the conergence speed difference is small. Howeer, when reactie power becomes the major power component (power factor angle θ changes to /3), the conergence time is two times longer than that with θ =. It indicates that the conergence speed drops quickly with the increase of reactie power. Compared with the traditional CPS- PWM scheme based balancing strategy (seen fundamental periods), the conergence speed of logic processed CPS-PWM scheme based balancing strategy is much slower when power factor angle reaches /3 (ten fundamental periods). This result erifies the proposed application ranges of power factor angle in Section III. i A, 2A/di A, 5V/di cla, 2V/di cla5, 2V/di V c_ag =97.2V V=35V t=s Enable flag i A, 2A/di (b) 5ms/di V ripple =9.4V cla8, 2V/di flag flag3 5ms/di B. Experimental Results Similarly, the logic-processed oltage balancing strategy is disabled at first, and the driing signal synthesized by logic OR process of the st and the 5th carriers is assigned to SM, and the driing signal synthesized by logic AND process is assigned to SM 8. Besides, the rest SMs driing signals remain unchanged. Consequently, the capacitor oltages of SM and SM 8 dierge from their rated alue. Three cases are studied in this section, i.e., the power factor angle equals to, /6 and /3. The experimental results are presented in Fig. (a), (b), (c). The output oltage, output current, capacitor oltages of SM, SM 5 and SM 8 in the lower arm of phase A, execution flag and enable flag of the balancing strategy are depicted in sequence in each figure. It should be noticed that, in order to keep a high conergence speed and aoid the possible oltage oscillations, the selection of carrier phase angle difference for logic processing is diided into three regions according to the oltage diergence degree as introduced in [4]. Therefore, the conergence time is indicated by the execution flag of the outermost region flag and the innermost region flag 3. The key experimental results are concluded in Table III. It is consistent with the analysis and simulation that the conergence time increases with the increase of reactie power component. And when the power factor angle θ reaches /3, the conergence speed drops a lot compared to the condition when θ = (from fie fundamental periods to fifteen fundamental periods). cla, 2V/di cla5, 2V/di V c_ag =96.7V A, 5V/di V=34V t=.3s Enable flag (c) 5ms/di V ripple =9.7V cla8, 2V/di flag flag3 5ms/di Fig.. Experimental results for 45 Hz logic-processed CPS-PWM based balancing strategy, (a) power factor angle θ =, (b) θ = /6, (c) θ = /3. Balancing Strategy TABE III Comparison of Experimental Results ogic Processed Scheme With FFSA

8 8 CPSS TRANSACTIONS ON POWER EECTRONICS AND APPICATIONS, VO. 4, NO., MARCH 29 VI. Conclusion The conergence speed and application ranges of the logicprocessed CPS-PWM scheme based balancing strategy is analyzed in this paper. It is reealed through mathematical analysis that the conergence speed is mainly determined by the power factor of MMC. And by comparing with the normal CPS-PWM scheme based balancing strategy, the application ranges of power factor angle for the proposed balancing strategy is deried, i.e., [-/3, /3] [-, -2/3] [2/3, ]. It indicates that this strategy is especially suitable for MMC- HVDC transmissions, which mainly deals with actie power. Besides, with the proposed three-tier control system, CPS- PWM and logic process are centralized in the phase-controllers (FPGA). Therefore, the synchronization of switching actions is guaranteed naturally. The theoretical analysis is alidated by both simulation and experimental results. References [] M. A. Perez, S. Bernet, J. Rodriguez, S. Kouro and R. izana, "Circuit topologies, modeling, control schemes, and applications of modular multileel conerters," IEEE Trans. Power Electron., ol. 3, no., pp. 4-7, Jan. 25. [2] A. Nami, J. iang, F. Dijkhuizen and G. D. Demetriades, "Modular multileel conerters for HVDC applications: Reiew on conerter cells and functionalities," IEEE Trans. Power Electron., ol. 3, no., pp. 8-36, Jan. 25. [3] H. Alyami and Y. Mohamed, "Reiew and deelopment of MMC employed in VSC-HVDC systems," in Proc. IEEE CCECE, DOI:.9/CCECE , pp. -6, 27. [4] M. Hagiwara, R. Maeda and H. Akagi, Control and analysis of the modular multileel cascade conerter based on double-star choppercells (MMCC-DSCC), IEEE Trans. Power Electron., ol. 26, no. 6, pp , Jun. 2. [5] R. izana, M. A. Perez, D. Arancibia, J. R. Espinoza and J. Rodriguez, Decoupled current model and control of modular multileel conerters, IEEE Trans. Ind. Electron., ol. 62, no. 9, pp , Sept. 25. [6] R. Zeng,. Xu,. Yao and S. J. Finney, Analysis and control of modular multileel conerters under asymmetric arm impedance conditions, IEEE Trans. Ind. Electron., ol.63, no., pp.7-8, Jan. 26. [7] M. Hagiwara and H. Akagi, Control and experiment of pulsewidthmodulated modular multileel conerters, IEEE Trans. Power Electron., ol. 24, no. 7, pp , Jul. 29. [8] S. Fan, K. Zhang, J. Xiong and Y. Xue, "An improed control system for modular multileel conerters with new modulation strategy and oltage balancing control," IEEE Trans. Power Electron., ol. 3, no., pp , Jan. 25. [9] A. esnicar and R. Marquardt, An innoatie modular multileel conerter topology suitable for a wide power range, in Proc. IEEE Power Tech. Conf., ol. 3, pp. 6, Jun. 23, doi:.9/ptc [] Q. Tu, Z. Xu and. Xu, "Reduced switching-frequency modulation and circulating current suppression for modular multileel conerters," IEEE Trans. Power Del., ol. 26, no. 3, pp , July 2. [] H. Peng, Y. Wang, Z., Y. Deng, X. He and R. Zhao, "Capacitor oltage balancing based on fundamental frequency sorting algorithm for modular multileel conerter," in Proc. IEEE Energy Coners. Congr. Expo., Sept. 24, pp , doi:.9/ecce [2] H. Peng, R. Xie, K. Wang, Y. Deng, X. He and R. Zhao, "A capacitor oltage balancing method with fundamental sorting frequency for modular multileel conerters under staircase modulation," IEEE Trans. Power Electron. ol. 3, no., pp , No. 26. [3] G. Chen, H. Peng, R. Zeng, Y. Hu and K. Ni, "A fundamental frequency sorting algorithm for capacitor oltage balance of modular multileel conerter with low frequency carrier-phase-shift modulation," IEEE J. Emerging Sel. Topics Power Electron., ol. 6, no. 3, pp , Sept. 28. [4] K. Wang, Y. Deng, H. Peng, G. Chen, G. i, and X. He, "An improed CPS-PWM scheme based oltage balancing strategy for MMC with fundamental frequency sorting algorithm," IEEE Trans. Ind. Electron., ol. 66, no. 3, pp , Mar. 29. [5]. Zhou, K. Wang, Y. Deng, Y. u, C. Wang and F. Xu, Conergence speed analysis of capacitor oltage balancing strategy for MMC with logic processed CPS-PWM scheme, in Proc. 28 IEEE Int. Power Electron. Appl. Conf. Expo. (PEAC), No. 28, pp. 6, doi:.9/ PEAC [6] S. Huang, R. Teodorescu and. Mathe, "Analysis of communication based distributed control of MMC for HVDC," in 23 5th Eur. Conf. Power Electron. Appl. (EPE), ille, 23, pp. -.doi:.9/ EPE Kun Wang receied the B.E.E. degree from the Uniersity of Electronic Science and Technology of China, Chengdu, China, in 23. He is currently working toward the Ph.D. degree from the College of Electrical Engineering, Zhejiang Uniersity, Hangzhou, China. His current research interests include modular multileel conerters, dc-dc conerters and grid-connected photooltaic systems. eyuan Zhou receied B.Eng from Nanjing Uniersity of Science and Technology, China, in 25. He is currently working towards his M.S. degree in Power Electronics and Motor Dries. His current research interests include modular multileel conerters (MMC) and the inter-connection of multi-end in the distribution network. Yan Deng receied the B.E.E. degree from the Department of Electrical Engineering, Zhejiang Uniersity, Hangzhou, China, in 994, and the Ph.D. degree in power electronics and electric dries from the College of Electrical Engineering, Zhejiang Uniersity, in 2. Since 2, he has been a faculty member at Zhejiang Uniersity, teaching and conducting research on power electronics. He is currently a professor with Zhejiang Uniersity. His research interests are topologies and control for switch-mode power conersion. Yi u receied his B.S. degree in Electrical Engineering from North China Electric Power Uniersity, Baoding, China, in 2. He receied his M.S. and Ph.D. degrees in Intelligence Engineering and Electrical Engineering from the Uniersity of ierpool, ierpool, U.K., in 22 and 27, respectiely. In 28, he joined the State Grid Zhejiang Electric Power Research Institute, Hangzhou, China. He is a senior engineer, and his research interests include HVDC and FACTS.

9 K. WANG et al.: APPICATION RANGE ANAYSIS AND IMPEMENTATION OF THE OGIC-PROCESSED CPS-PWM SCHEME 9 Chaoliang Wang receied his B.S. and M.S. degrees in Electrical Engineering from North China Electric Power Uniersity, Beijing, China, in 2 and 24, respectiely. Since 24, he has been an engineer at State Grid Zhejiang Electric Power Research Institute, Hang Zhou, China. His current research interests include HVDC and FACTS. Feng Xu was born in Zhejiang, China, in February 988. He receied the B.S. and Ph.D. degrees in Electrical Engineering from Zhejiang Uniersity, Hangzhou, China, in 2 and 25 respectiely. Currently, he works in State Grid Zhejiang Electric Power Research Institute. His research focus is on high power electronics technology, CC-HVDC transmission system, VSC-HVDC transmission system, and DC grid.