A SIMPLE APPROACH TO DESIGN TELE-COMMAND DECODER A FPGA IMPLEMENTATION OF ZCD BASED FSK DEMODULATOR

Transcription

1 International Journal of Electrical and Electronics Engineering Research (IJEEER) ISSN X Vol. 3, Issue 2, Jun 2013, TJPRC Pvt. Ltd. A SIMPLE APPROACH TO DESIGN TELE-COMMAND DECODER A FPGA IMPLEMENTATION OF ZCD BASED FSK DEMODULATOR UTPAL MANDAL 1 & AMIYA RANJAN PANDA 2 1 Scientist, Integrated Test Range, Drdo, Chandipur, Odisha, India 2 Senior Research Fellow, Integrated Test Range, Drdo, Chandipur, Odisha, India ABSTRACT The paper describes a simple technique used to implement a Tele-Command decoder system in Field Programmable Gate Array (FPGA). Tele-Command decoders are critical part for a Flight Vehicle such as Unmanned Air Vehicle (UAV) under test in terms of a safety tool. Decoders are employed in a UAV system after receiver and frequency demodulator block to demodulate the baseband signal to decode the transmitted command. A receiver-decoder system is used with the ground transmitting system for instant validation of digital code and system configuration. In general, decoder outputs TTL signals for corresponding commands, which are used by Personal Computer, based software to record the data for future analysis. The design is based on a VLSI development board consisting of a high performance high density Vertex-4 FPGA with required interfaces to handle both analog and digital domain signals. KEYWORDS: Tele-Command, VLSI, TTL, FSK, VHD INTRODUCTION Ground transmitting system (GTS) consists of Digital Encoder, FM Modulator and Power Amplifier system as the fundamental units. Digital Encoder is the baseband unit which is responsible for generating command word of particular length. A Frame is formed adding sync bits and parity bit to the command words. Manchester encoding is performed on the command frame with few invalid Manchester bits on the frame. This is done to identify the sync bits at decoder side. The Manchester data bits are transferred at particular rate and passed to a Binary Frequency Shift Keying (BFSK) modulator. Sub-carrier frequencies for BFSK signal are chosen in the specified band of 10 KHz to 50 KHz. BFSK signal of low level is fed to FM modulator for wide band FM modulation at Ultra High Frequency (UHF) band. A particular frequency in UHF band is used for FM modulation. This signal is then power amplified and transmitted through Omni-directional or directional antenna depending upon requirement. GTS system generates four types of commands and transmits these commands on demand through UHF link. SA1 command is transmitted normally which ensures link between GTS system and UAV on board receiver. When termination of the test vehicle is required, then a sequence of commands like SA2, SA3 and SA4 are transmitted. These commands are received, decoded by the on-board receiver decoder and passed to destruction system. SA2 command allows activation of SA3. SA3 command is used to cut-off the thrust of liquid propellant and SA4 command enables destruction system for termination. Power amplified signal transmitted in air needs to be received by a receiver and demodulated to base-band signal, which is the signal of interest. The receiver and FM demodulator are not included in the scope of this paper and hence shall not be described at any part of this paper. The baseband signal characteristics, demodulation technique used shall be considered in subsequent sections. DESIGN SPECIFICATION To realize a digital decoder system for UAV system the following basic functionality from design point of view is

2 50 Utpal Mandal & Amiya Ranjan Panda realized for Digital Encoder system: Demodulate baseband FSK signal to recover Manchester data bits. Detection of sync bits Manchester decoding to extract command data word. Compare decoded command word to the known transmitting command word. Declare the decoded command by displaying in LCD interface. Output corresponding command in TTL level on I/O pins for display or recording purpose. The next few sections are dedicated to describe implementation of these design steps in details with results obtained at different step of design. The following section depicts the characteristics of FSK signal, different methods to demodulate the signal and details of the used technique for the design. FSK SYSTEM Frequency Shift Keying (FSK) system is a type of wireless systems that is very popular in today s life and has widespread applications. A FSK system carries its information in the instantaneous frequency of the received signal. E.g. a binary FSK system which transmits the symbols 0 and 1 have one frequency corresponding to the symbol 0 and another frequency to the symbol 1. FSK systems are broadly classified into Coherent and Non-coherent systems. A coherent system requires carrier or phase synchronization at the receiver end in order to detect the signals whereas non coherent detection does not require any sort of phase synchronization. Consequently the design of non coherent systems is much simpler when compared to coherent systems making them more popular when power is an important concern. But non-coherent systems have a BER performance of 3db less than the traditional coherent receiver at a BER of 10E-5. The general analytic expression for FSK modulation is Si (t) = (2E/T) cos (ωi t + φ) 0 t T i = 1,., M Where Si (t) is the modulated carrier, E is the energy content of Si (t) over each information symbol of duration T, ωi is the frequency term with M discrete values, and the phase term, φ is an arbitrary constant. In case of binary FSK, the value of M is 2, representing binary information symbols and a carrier with two possible frequencies. FSK is much less susceptible to corruption by unwanted amplitude modulation ( i.e. due to noise or transients). Detection of FSK signal may not incorporate the phase information of the incoming signal. Thus, BFSK modulation technique preceded other digital modulation technique like ASK and PSK in many applications. Figure 1 below demonstrates modulating information bits and its corresponding FSK waveform. It is very much visible that on change in the information data from logic 0 to logic 1 the frequency changes abruptly in the FSK wave [1-2]. DETECTION OF FSK FSK detection is the process of extracting the information symbols from a modulated carrier wave.

3 A Simple Approach to Design Tele-Command Decoder A 51 FPGA Implementation of ZCD Based FSK Demodulator Figure 1: BFSK Waveform The detection process is mainly categorized into two types; i.e. coherent detection and non coherent detection. In the case of coherent detection, the receiver exploits the knowledge of the carrier s phase in order to detect the symbols whereas in the case of non coherent detection, the receiver does not utilize any phase reference information from the carrier. Coherent based receivers are usually complex to design but have the best BER performance. The, coherent designs also consume more power. Non coherent receivers have simple design, consume less power but have degraded BER performance [3]. In the context of the present Decoder design for FTS, the receiver performance is considered to be optimum as it is kept very nearer to the transmitter. COHERENT BINARY FSK DETECTOR Figure-2 below, shows a commonly used coherent type binary FSK receiver. As mentioned in the previous section a coherent receiver needs to be in phase synchronization with the transmitter. It consists of two correlators with a common input and which are supplied with two locally generated reference signals φ1 (t) and φ2 (t). Figure 2: Coherent BFSK Receiver The correlators outputs are then subtracted one from another and the resulting difference d is compared with a threshold of zero volts. If d > 0, the receiver decides in favor of 1 else in favor of 0. The transmitted signal consists of both the frequencies f1 and f2. The reference signals φ1(t) and φ2(t) are extracted by applying the received signal to a pair of

4 52 Utpal Mandal & Amiya Ranjan Panda narrow band filters, one tuned to f1 and the other tuned to f2. Hence the reference signals are in phase coherence with the transmitted signals. NON COHERENT BINARY FSK DETECTOR There are again various techniques for non coherent detection of BFSK signal. A zero-crossing detector based demodulator is described here which is implemented in the design. Figure below shows a block diagram for the demodulator. Figure 3: Block Diagram for the BFSK Demodulator Each tone of a Binary FSK signal can be characterized by the number of clock cycles it takes between two zero crossings for a given sampling frequency. For example a 100 khz signal sampled at 4 MHz will have 20 samples between two zero crossings and a 200 khz signal would have about 10 samples. So a counter that can resets for every zero crossing would have two discreet values at the output. A threshold somewhere in between 20 and 10 would hard limit the output to digital levels, thus, demodulating the FSK signal. To increase the tolerance to noise, the sampling can be increased so that the values from the counter are separated further apart and decreasing the probability of an error [1-3]. MANCHESTER CODE Non-return to Zero (NRZ) and Manchester codes are used in digital systems to represent the binary values "1" and "0". Figure-4, defines how NRZ and Manchester code represent binary values. NRZ is the code which is used most often. In NRZ, logic "1" is represented as a high level throughout a data cell, and logic "0" is represented by a low level. Manchester code represents binary values by a transition rather than a level. The transition occurs at mid-bit, with a low-to-high transition used to represent logic "0", and a high-to-low to represent logic "1". Depending on the data pattern, there may be a transition at the cell boundary (beginning/end) [4-5]. A pattern of consecutive "1s" or "0s" results in a transition on the cell boundary. When the data pattern alternates between "1" and "0", there is no transition on the cell boundary. In figure 4 it can be seen that two different types of convention are used for Manchester encoding. In IEEE convention logic 0 is represented by a high to low transition and logic 1 is by low to high. The reverse is used in G. E. Thomas convention. Here G. E. Thomas convention is used in the application.

5 A Simple Approach to Design Tele-Command Decoder A 53 FPGA Implementation of ZCD Based FSK Demodulator Figure 4: NRZ and Manchester Code Manchester code has no DC component, but it can be transformer coupled. The mid-bit transition in Manchester code provides a self-clocking feature of code. This can be used to improve synchronization over non-self clocking codes as NRZ. The transition allows additional error detection with relatively little circuitry. Manchester decoding is performed on FSK demodulated data which is described in details in next section. IMPLEMENTATION FSK Detection Figure 3, shows the technique which is less complex than any other technique as it does not employ any filter or any complex algorithm. For the simplicity, the technique is chosen and implemented. Design of the digital logic has been done by VHDL coding. Implementation is targeted for a FPGA Development Board housing a Virtex-4, Xilinx make device [6-7]. Analog to Digital (ADC) controller interface is implemented which takes the FSK signal and convert it to a 12-bit digital data in 2 s complement format. The most significant bit (MSB) of the ADC data represents the sine convention of the incoming wave. ADC data is sampled at much higher rate. As the MSB is sign bit for the wave so it remains high for the positive cycle of the wave and low for negative cycle. Hence it results in a square wave with variable width as tone is abruptly changing. Figure 5, shows a screen image, of FSK tone and its corresponding 1-bit analog to digital data bit waveform, captured in a scope. ADC data is sampled at much higher rate at MHz than the FSK tone sub-frequencies, which are at 18 KHz and 22 KHz at the present design concern. The 1-bit A/D data is further processed for demodulating purpose. It can be seen that this waveform is a square wave replica of the FSK tone with varying width. Figure 5, shows the width 1 represents sub-frequency of 22 KHz and width 2 represents 18 KHz. An edge detector is implemented by comparing the two sample values of the 1-bit A/D data. Figure 5: 1-Bit A/D Data Captured in Scope

6 54 Utpal Mandal & Amiya Ranjan Panda Figure 6: Edge Detector Output Figure 6, shows the edge detector output pulses. These edge pulses corresponds to the zero cross detection of the FSK tones. A counter is implemented which lathes the value of the count to a register at the rising edge of the edge detector pulse and resets to zero. The latched value of the counter is compared to a threshold which is calculated on the basis of the counter operation frequency. By comparing these values, the logic is derived which is the expected demodulated output. A 9 bit counter is implemented to provide sufficient separation between the counter values for two different widths. Figure 7, depicts the demodulated output. Figure 7: Demodulated Output Manchester Decoding The decoded data represent the Manchester encoded data which needs further decoding process. A separate Manchester decoder module has been designed for receives the demodulated output as the Manchester encoded (Manch in) data along with clock (CLK) and reset (RST) inputs. The module is shown schematically in figure 8. The CLK clock input is the main clock here which is further divided by to give a 20 MHz clock at which the module operating. The module outputs decoded data bits (Ser_Data) serially along with recovered clock signals denoted as Sync in the diagram. The module also performs extraction of command word from the command frame (encapsulated by sync and parity bits) represented by Ser_Data.

7 A Simple Approach to Design Tele-Command Decoder A 55 FPGA Implementation of ZCD Based FSK Demodulator Figure 8: Schematic of Manchester Decoder The technique for decoding is described here in brief. Except the sync bits of the incoming Manchester data, which do not carry proper Manchester encoding, the data bits with Manchester can be seen elaborately in the top waveform of figure 9. Figure 9, shows the ideal waveform fed to and output from the decoder unit. Here as to decode the data bits the clock signal has been recovered first. As in the figure 9 it is seen that the cycle for Manchester is fixed and transition occurs at the middle of the cycle which is very significant as it represents some data bits at that instant. Other edges occur at the boundary of the cycle while boundary edges are not present when there are different consecutive bits (0 then 1or vice versa). So it is found that time between two consecutive edges of Manchester signal is either one half cycle or two half cycle and three half cycle or four half cycle for invalid Manchester (sync bits). Two counter is implemented which resets on positive and negative edges of the Manchester signal respectively. Hence with this fact it is concluded that one counter represents the duration of two consecutive edges when other is reset. For the design considered here as the data rate is known, hence the half cycle duration is also known. So, a sync signal is derived which is inverted when any of the counters resets or the counter value crosses over the half cycle duration. Now with the derived clock, Manchester signal can be decoded easily. It can be observed that rising edge of the derived clock arrives just after the significant edges of the Manchester signal. Hence, on clock (derived sync clock) event and when it is high inverted value of the Manchester signal gives the desired decoded waveform of course leaving the invalid Manchester Bits (sync bits). After this, extraction of the command is performed by implementing counter by resetting it on sync interval and storing the bit values on register on counter increment. The extracted word is passed to the main module for comparison and declaration of particular command. Figure 9: Waveforms Applied to and Generated by Manchester Decoder Unit

8 56 Utpal Mandal & Amiya Ranjan Panda Figure 10 shows a snapshot of the design files hierarchy from the ISE editor tool. The top module named as decoder. ADC interface and command comparison is implemented here. Other modules like clock dividers, Manchester decoder and LCD modules are instantiated by this top module [8-9]. Figure 10: Design Hierarchy and Lab Setup The lab set up is arranged to test the decoder in such a way that one of the board of similar configuration is loaded with program to operate as encoder unit [10-11]. Figure 11 shows the Encoder set up, which is used as the source. From the board analog interface the BFSK signal output containing particular sub frequencies is fed to the ADC interface of the second development board where the decoder application has to run. Additionally the decoder unit has been tested with the proven Encoder system which is being used for various tests. FUTURE WORK There are many methodologies and techniques for BFSK demodulation including coherent as well non-coherent. The other technique shall be realized to compare between them to visualize which techniques performs better and the technique suitable for particular application. Future work may also include testing the system in very low signal strength condition and to do dynamic testing also. The system shall be made robust to cater for noise in the received signal. CONCLUSIONS In the paper, a zero crossing detector based FSK demodulation technique implementation is described and further as the demodulated data represent Manchester encoded data, hence decoding of the same is also performed to extract the transmitted data word from the encapsulated (by sync and parity bits) data frame. The extracted command word is stored and compared to the known transmitted command word, to declare about the particular command. The decoder has been tested with proven encoder system and keeping the receiver very near to transmitter, which yields a good Signal to Noise Ratio (SNR). The decoder performance in terms of command decoding is found to be very good. REFERENCES 1. Vikram B Arkesh, FPGA Implementation of a Low Power Doppler Invariant BFSK Receiver, thesis report, North Carolina State University, Raleigh, Virk, K. M., Design of an Integrated GFSK Demodulator for a Bluetooth receiver, Project report, Informatics &

9 A Simple Approach to Design Tele-Command Decoder A 57 FPGA Implementation of ZCD Based FSK Demodulator Mathematical Modeling, Technical University of Denmark, Lyngby, Denmark Mukthavaram, S., Design and FPGA Implementation of an Adaptive Demodulator, Thesis report, B.S. E.E., Osmania University, Hyderabad, India, Lech, Olmedo, Using the XGATE for Manchester Decoding Application Note, Rev. 0, Freescale Semiconductor, Guadalajara, Mexico Manuel Alves Austin, USA, Anton, A., Manchester Decoder and Clock Recovery Module for FPGA Prototype of Active RFID Tag, Technical Report, Berkeley Wireless Research Center, University of California, Berkeley, Xilinx Inc, ISE 11.1, 7. Mechatronics Test Equipment, FPGA DaVinci Development Board, User manual, MTE India, Arora, M., Clock Dividers Made Easy, application note, ST Microelectronics Ltd, Noida, India, Pong, P. C., fpga prototyping by vhdl examples, a john wiley & sons, inc., Hoboken, New Jersey, U.S., 2008, pp , chap Tektronix, MSO 4104 Mixed Signal Oscilloscope, user manual, Mandal, U., Realization of UART Controlled Digital Encoder System in Field Programmable Gate Array, DRDO Science Spectrum, 2012, pp

10