MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs

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1 JOURNAL OF ELECTRONIC TESTING: Theory and Applications 23, , 2007 * 2007 Springer Science + Business Media, LLC Manufactured in The United States. DOI: /s MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs SUNGHOON CHUN, YONGJOON KIM AND SUNGHO KANG Department of Electrical and Electronic Engineering, Yonsei University, 134, Shinchon-Dong Seodaemoon-Gu, Seoul, South Korea shchun@yonsei.ac.kr yongjoonkim@yonsei.ac.kr shkang@yonsei.ac.kr Received October 31, 2005; Revised August 21, 2006 Editor: K. K. Saluja Abstract. Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches. Keywords: signal integrity, interconnect test, RLC interconnect model, fault modeling 1. Introduction Signal integrity issues arise from long on-chip interconnects where the effect of parasitic elements may jeopardize the functionality and reliability of high performance SoCs. Long on-chip interconnects fall primarily into three categories: data-buses, control, or clock. Data lines generally have halfa-chip-edge in length, and have a small load at the receiver. Such lines synchronously operate and are designed for minimum path delay over fairly long path length. Therefore, these data-buses are vulnerable to signal integrity problems due to their synchronous and possibly in-phase data patterns. Therefore, in this paper, we focus on testing signal integrity faults on long interconnects like data-buses. To enable testing for signal integrity defects, several fault models and test generation methods have been proposed to capture the signal integrity effects in gatelevel circuits [2, 7, 9]. In addition, many approaches for analysis, modeling and testing signal integrity effects on long interconnect lines have been proposed [4, 8, 10, 11]. Maximum Aggressor (MA) fault model was presented in [4], which abstractly models crosstalk effects on interconnects with a linear number of faults. However, since the MA fault model was based on RC interconnect model, test patterns for it could not achieve high fault coverage for long interconnects [3]. In [8], the authors presented a BIST for signal integrity using pseudo-random patterns. Signal integrity fault model was presented in [1]. This was based on accurate RLC interconnect models; however, this method requires too much large computation power for solving numerical equations. The other signal integrity fault model based on RLC interconnect model, the MT fault model, was proposed in [11]. However, since it actually considered the effects of coupling capacitances, it could not guarantee the high fault coverage. In addition, the MT fault model requires too many test patterns. Therefore, in our approach, we use the accurately distributed RLC interconnect models and present a new accurate and simpler fault model for signal integrity in a system-on-chip. 2. Signal Integrity Effects The short local wirings with the highest density are shown to be affected by the large capacitance and capacitive coupling to adjacent neighbors that generate excessive data-patterndependent delay and delay violation. The medium and long

2 358 Chun et al. lines are mostly limited by the capacitive and inductive coupling, causing excessive crosstalk, especially when these lines are driven by larger low-impedance devices. Signal integrity noise is broadly classified into two types. Functional noise occurs when a victim line is intended to be at a stable state and results in an unwanted noise pulse on the net. Delay noise occurs when noise is injected on a net when it transitions, and results in a change in the delay of the net. As mentioned above, the RC interconnect models underestimate the noise error of the victim line. We analyzed this underestimation problem of previous works by comparing each type of noise error. The following two cases were considered: (1) all inductances are ignored (RC interconnect modeling) and (2) all inductance and capacitances are considered (RLC interconnect modeling). First, we analyzed the functional noise of the victim line. The simulation results for the functional noise are shown in Fig. 1a. Note that, in Fig. 1, the interconnection parameters are as follows: the resistance of 0.1 W/mm, the self-inductance of 0.6 ph/mm and the mutual inductance of 0.4 ph/mm are considered. In addition, the capacitance is ff/mm and the coupling capacitance is ff/mm. Interconnection length of 1,000 mm is considered. The waveforms in Fig. 1 highlight the initial fast LC-like transition of the signals even for fairly resistive lines. Note that the tool FASTHENRY was used for extracting inductance values [6] and all the simulation results for a given RLC network were obtained using HSPICE simulation [5]. In case (2), this magnitude is more than twice as large as the pulse for case (1). This demonstrates that signal integrity noise induced by a combination of mutual inductance and capacitance can be more severe than that due to capacitive coupling alone. In the second experiment, signal integrity slowdown was analyzed. The output is shown in Fig. 1b. As shown in Fig. 1b, not only was the absolute magnitude of the delay higher than the alternatives,_ but also the inductanceinduced slowdown caused the latest occurring transition among the two cases. Thus, the magnitude of signal integrity slowdown may increase when parasitic inductances are considered. Similarly, there were differences of speedup between case (1) and (2); the latter_s rate was much larger. 3. Signal Integrity Fault Model and Test 3.1. Maximal Dominant Signal Integrity Fault Model The effective characteristic impedance and propagation delay of a interconnect line will change with different switching patterns in SoCs where significant coupling between traces exists. Electric and magnetic fields interact in specific ways that depend on the data patterns on the coupled lines. An odd-mode propagation mode is defined as the case when two coupled interconnection lines are driven with equal magnitude and 180- out of phase with one another. The effective coupling capacitance of the interconnect line will increase by the coupling capacitance and the equivalent inductance will decrease by the mutual inductance. In this case, the increased capacitance value and the decreased inductance value become 1õ2 times depending on the relative strength of the aggressor driver and the victim driver. Even-mode occurs when two coupled interconnection lines are driven with equal magnitude and are in phase with one another. The effective capacitance and the equivalent inductance will increase by the mutual inductance. To resolve the limitations of the MA fault model, we propose a new signal integrity fault model called the MDSI (Maximal Dominant Signal Integrity) fault model. Our proposed fault model consists of a single victim line, oddmode propagations for limited number of near aggressor lines and even-mode transitions of the other lines for functional glitch faults and slowdown faults. In addition, all the aggressors are even transitions for speedup faults. The basis of the MDSI fault model is the combined effect of capacitances and inductances. In the RLC interconnect model, we have observed an interesting fact. The mutual inductance is always added or subtracted in the opposite manner as the coupling capacitance for odd- and even-mode propagation. For example, in odd-mode propagation, the effect of the coupling capacitance must be added because the conductors are at different potentials. Additionally, since the currents in the two conductors are always flowing in opposite directions, the currents induced on each line due Fig. 1. Signal integrity noise of the victim line.

3 MDSI 359 Fig. 2. Required transitions for the MDSI fault model. to the coupling of the magnetic fields always oppose each other and cancel out any effect due to the mutual inductance. Subsequently, the mutual inductance must be subtracted and the coupling capacitance must be added to calculate the odd-mode characteristics. However, since the effect scope of the coupling capacitance is much narrower than that of the mutual inductance, the effects of adding the coupling capacitance in odd-mode propagation are restricted within narrow boundaries. Therefore, the number of lines (aggressors) nearby the victim line can be limited. We define á as a limited factor that is determined empirically showing how far the effects of capacitances at aggressor lines remain significant. The appropriate value of the limited factor depends on technology and application. However, once a user based on application and accurate simulation provides it, effective test patterns are determinable. We found the following properties of signal integrity. Property 1 For two tests t 1 and t 2 for signal integrity faults, if t 1 has one or more contributive transitions beside all the contributive transitions that t 2 has, the error produced by t 1 is more significant than that produced by t 2. In this case, we refer that t 2 is dominated by t 1 and t 1 is more dominant test than t 2 for the noise error of the victim line v. Therefore, to obtain the most dominant test vectors, it is important to determine the adequate limited factor a. The limited factor a is determined empirically or by using the HSPICE simulation [5] partially. Assuming that the limited factor has been determined, there is only one modeled fault in the MDSI model for each error on a victim line L i, and only one set of transitions that can excite that fault unless the bus topologies in a chip are considered. Fig. 2 shows the transitions on the victim and aggressor wires required to excite the six different possible faults for a victim wire L i under the maximal signal integrity fault model without considering the topology of interconnects. Therefore, when the topology of interconnects is not considered, we can say that for an N-line wide set of interconnects, the fault model has 6 N faults, and requires 6 N two-pattern tests. Discussions of the effect of the topology in our proposed fault model are presented in the next section Consideration of Interconnection Topology An interconnection shown in Fig. 3 is used to discuss the impact of the interconnection topology. The length of the portion of an aggressor line that is adjacent to the victim Fig. 3. An example of an interconnect.

4 360 Chun et al. Fig. 4. Signal integrity effect vs. length of an aggressor. line is increased in order to determine the effect of the length of the portion of an aggressor line. As shown in the results of HSPICE simulations [5] in Fig. 4, the effects of the signal integrity at the victim line deteriorates in proportion to the length of portion of the aggressor line. Since we used the distributed RLC interconnection model, the parasitic values according to the length of the aggressor are easily obtained. After accounting for the interconnect topology, the signal integrity error depends on the length of the aggressor and the distance of the aggressor from the victim line. For example, we assumed that the L3 line in Fig. 3a is the victim line. In this case, the effect of the L2 line and the effect of the L4 line is the same if we do not consider the interconnect topology. However, the effect of the L4 is actually more severe than that of the L2 because the effective lengths as the aggressor are different. Considering the interconnect topology, the signal integrity error depends on the length of the aggressor and the distance of the aggressor from the victim line. The interconnection is depicted by a graph where vertices represent interconnects and edges represent distances from the victim line. In addition, each vertex contains the value of the actually effective length as the aggressor. The topological representation of the above example in Fig. 3a is shown in the graph in Fig. 3b. The number of graphs for the MDSI fault model equals the number of vertices in the graph, since each vertex represents a possible victim and the value of each vertex differs corresponding to the victim line. The above topological representation graph is based on the assumption that any pair of adjacent lines have the same significant coupling effect. In fact, adjacent lines do not have sufficient coupling capacitances if the length of the portion of these lines that are adjacent to the coupling capacitance between the lines is small. Therefore, the effects of the coupling capacitances and the mutual inductances differ according to the effective length of the aggressor and the distance of the aggressor from the victim line. We defined b as an impact factor that shows how severely the effect of capacitance at an aggressor line affects the victim line in the topology representation graph. The impact factor b of the aggressor i is calculated as the following equation. b ¼ el i d i ð1þ where d i is the distance of the aggressor i from the victim line. The relation between a and b is defined by the following equation. b C Ci el a a C Ca ð2þ where C Ci is the coupling capacitance between line i and the victim line and el a is the effective length of the aggressor line which have a distance from the victim line when the interconnection topology is not considered. Note that a, el a and C Ca are obtained assuming that all the interconnections are the same length and the length is the longest in the interconnection topology. Using this relation between a and b, more dominant test patterns for the MDSI fault model are generated. Table 1. Comparison of various interconnect systems. BUS MA (%) [4] MT (%) [11] MDSI w/o ITG (%) 8 bit (1) bit (2) bit (3) bit (1) bit (2) bit (3) bit (1) bit (2) bit (3) MDSI w/ ITG (%)

5 MDSI Test Generation For a given interconnect system, a RLC network is generated by using parasitic extraction tools with process technology libraries. Next, the limited factor á is determined empirically or by using the HSPICE simulation [5] partially. After the determination of the limited factor, a victim line is selected from the list of possible victims and then the interconnection topology graph for the selected victim line is generated. For the generated interconnect topology graph, the desired test vector pair for the proposed MDSI fault model is produced by using the relation equation 2. Until the list of possible victims is empty, the above test pattern generation procedures are continued. 4. Experimental Results Using 8, 16 and 32 interconnection systems with randomly generated interconnection topologies, running for 3 mm in parallel on metal layer 4, and in a 0.18 mm process, we demonstrated the efficiency of the MDSI fault model with the interconnection topology graph. For the given RLC network, we injected 100 random signal integrity defects and simulate in order to obtain the defect coverage for test vectors for the MDSI fault model and the MA fault model. Table 1 shows the defect coverage percentages for the MA fault model, the MDSI fault model without the interconnection topology and the MDSI fault model with the interconnection topology. Note that the defect coverage of the applied test set T is calculated using the following equation. number of detected defects DCðTÞ ¼ number of the injected defects 100 ð3þ As shown in Table 1, among the three test vector sets, the MDSI fault model with the interconnection topology is the most efficient for all the interconnect systems. To find the appropriate a value, we monitored variations when we increased aggressor lines. Though HSPICE simulation, we found that the noise voltage difference between a=3 and a=4 is 0.06 V which for many systems can be assumed negligible in our interconnect models. Therefore, we used a=3 as the limited factor for our experiments. Note that non-aggressor lines keep 0 V. 5. Conclusions In this paper, we proposed a new signal integrity fault model for a given RLC interconnection. The proposed MDSI (Maximal Dominant Signal Integrity) fault model is based on the analysis of the impact of aggressor lines on signal integrity effect at a victim line. Test vector pair for each type of signal integrity fault was also described. We then presented a methodology to deal with arbitrary interconnect topology. Using the interconnection topology graph, our methodology generates test vector pairs to maximize the impact of aggressor lines. Experimental results showed that the proposed MDSI fault model is more exact than the MA fault model and the MT fault model and the defect coverage is much higher since the MA fault model and the MT fault model lead to underestimation of signal integrity effects caused by considering only the coupling capacitor_s effects. Acknowledgment This work was supported by the Korea Science and Engineering Foundation Grant funded by the Korea government (MOST) No. R References 1. A. Attarha and M. Nourani, BTest Pattern Generation for Signal Integrity Faults on Long Interconnects,^ Proc. IEEE VLSI Test Symp., pp , W. Chen, S.K. Gupta, and M.A. Breuer, BAnalytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Input,^ Proc. Int. Test Conf., pp , C. Cheng, J. Lillis, S. Lin, and N. Chang, Interconnect Analysis and Synthesis, New York: Wiley, M. Cuviello, S. Dey, X. Bai, and Y. Zhao, BFault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects,^ Proc. Int. Conf. Computer-aided Design, pp , HSPICE, v SP1, Synopsys Corporation. 6. M. Kamon, T.J. Tsuk, and J.K. White, BFASTHENRY: A Multipole Accelerated 3-D Inductance Extraction Program,^ IEEE Trans. Microwave Theor. Tech., vol. 42, pp , K.T. Lee, C. Nordquist, and J.A. Abraham, BTest Generation for Crosstalk Effects in VLSI Circuits,^ Proc. IEEE VLSI Test Symp., pp , M. Nourani and A. Attarha, BBuilt-In Self Test for Signal Integrity,^ Proc. Des. Autom. Conf., pp , A. Rubio, N. Itazaki, X. Xu, and K. Kinoshita, BAn Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits,^ IEEE Trans. Comput.-aided Des. Integr. Circuits Syst., vol. 13, pp , W. Sirisaengtaksin and S.K. Gupta, BEnhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology,^ Proc. Asian Test Symp., pp , M.H. Tehranipour, N. Ahmed, and M. Nourani, BTesting SoC Interconnects for Signal Integrity using Extended JTAG Architecture,^ IEEE Trans. Comput.-aided Des. Integr. Circuits Syst., vol. 23, pp , Sunghoon Chun received his B.S. degree in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea in He was a Reseach Engineer with ASIC Research Center in Yonsei University. He researched for test methodologies for SoC. He received his M.S. degrees in Electrical and Electronic Engineering from Yonsei Uiversity in He is currently working toward Ph.D. degree in Electrical and Electronic Engineering at Yonsei University. His area of interests include SoC testing, delay

6 362 Chun et al. testing, fault diagnosis, functional testing for processor based system and test methodologies for signal integrity faults. Yongioon Kim was born in Seoul, Korea on June 10, He received his B.S. and M.S. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea in 2002 and 2004, respectively. He is currently working towards the Ph.D. degree in Electrical and Electronic Engineering at Yonsei University. His area of interest includes SOC testing and computer-aided design (CAD) tools for SoC. Sungho Kang received his B.S. degree from Seoul National University, Seoul, Korea and M.S. and Ph.D. degrees in Electrical and Computer Engineering from The University of Texas at Austin. He was a Post-Doctorial Fellow with the University of Texas at Austin, a Research Scientist with the Schlumberger Laboratory for Computer Science, Schlumberger Inc., and a Senior Staff Engineer with the Semiconductor Systems Design Technology, Motorola Inc. Since 1994, he has been an Associate Professor with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea. His current research interests include VLSI design, VLSI CAD, and VLSI testing and design for testability.