symbols s 1 and s 0 are transmitted simultanously from the transmitters at time instant t. At time instant t + T,the

Transcription

1 2 Fifth IEEE Intrnational Symposium on Elctronic sign, Tst & Applications FPGA Implmntation of a Ral Tim Maximum Liklihood Spac-Tim codr on a MIMO Softwar Radio Tst Platform Ptr J. Grn and smond P. Taylor partmnt of Elctrical and omputr Enginring Univrsity of antrbury hristchurch, Nw Zaland drgrnptr@gmail.com taylor@lc.cantrbury.ac.nz Abstract This papr dscribs th concpt, architctur, dvlopmnt and dmonstration of a ral tim, maximum liklihood Alamouti dcodr for a wirlss 4-transmit 4-rcivr multipl input and multipl output (MIMO) Smart Softwar Radio Tst Systm (SASRATS) platform. It is implmntd on a Xilinx Virtx 2 Pro Fild Programmabl Gat Array (FPGA). Hardwar, firmwar, us of th Xilinx or Gnrator Intllctual Proprty moduls and xprimntal vrification of th dcodr ar discussd. Kywords-ral-tim implmntation; Alamouti; FPGA; maximum liklihood dcodr; MIMO; softwar radio tst platform RX 3 RX 2 RX RX 4 Analog own onvrtr 7 MHz IF Analog- igital onvrtr irct igital Synthsizr 65 MHz lock S Sync igital own onvrtr NO Sync SP5632 Sync Synchronizr I ata Output Xilinx Virtx 2 Pro FPGA I. INTROUTION Th proposd systm implmntation is dvlopd on an xisting MIMO Smart Softwar RAdio Tst Systm (SASRATS) platform [], [2] dsignd to tst and vrify various spac tim architcturs and algorithms. Th 4 rcivrs complmnt a 4-transmittr spac tim (ST) ncoding platform [3] dsignd and dvlopd for ral-tim tsting of ST coding schms dvlopd by Alamouti [4] and othrs mntiond in [5]. Th primary objctiv is to incras systm capacity and prformanc through th us of multipl antnnas, mploying spatial multiplxing and ST coding and dcoding. Spatial multiplxing and divrsity tchniqus ar currntly adoptd in th IEEE 82.n draft spcification to fully xploit th bnfit of MIMO channls. Th focus of this papr is on th digital basband portion of th systm, particularly th ral-tim implmntation of th Alamouti dcodr on a Xilinx Virtx 2 Pro FPGA. Othr MIMO tstbds [6], [7] typically prform post procssing oprations such as channl stimation and Alamouti dcoding in Matlab aftr capturing larg batchs of data. Ral-tim implmntation of a 2 Alamouti dcodr was brifly dscribd by [8]. Our work dscribs in dtail, th ral-tim implmntation of a maximum liklihood 2 2 Alamouti dcoding implmntation xtnding to a 2 4 systm on th SASRATS platform. II. OVERVIEW OF THE SASRATS ARHITETURE Th basic architctur of th SASRATS rcivrs is shown in Figur. Th analogu portion amplifis, translats and Figur. SASRAT 4 rcivr systm architctur with th Xilinx FPGA channl stimator filtrs a rcivd radio frquncy signal at 95 MHz or 2.4 GHz to an intrmdiat frquncy of 7 MHz whr digitization and bandpass sampling occurs. Th output of th analog to digital convrtr is thn fd into a digital down convrtr which digitally downconvrts, dcimats and filtrs th input data to produc basband in-phas (I) and quadratur phas () signals for furthr procssing. Th SASRATS rcivrs work asynchronously with th transmittrs and w hav dvlopd and implmntd ral-tim algorithms for carrir and symbol timing synchronization [9] and also channl stimation oprations [] in SP and FPGA. W adopt a fdforward approach through th us of known training symbols (data-aidd) or prambls at th transmittr to rsolv magnitud and phas ambiquitis in Rayligh flat fading channls. W assum that th channls chang only slowly during th priod btwn training prambls. A portion of th FPGA prforms ral-tim channl stimation as dscribd in []. In a 4-transmitr and 4- rcivr (4 4) MIMO systm, ach rcivr must stimat 4 distinct channls with a total of 6 channl stimats for 4 rcivrs. III. OVERVIEW OF ALAMOUTI SHEME Th Alamouti schm is th only orthogonal spac-tim block cod using complx signals for two transmit antnnas which provids full divrsity of 2 and full rat of. For mor / $26. 2 IEEE OI.9/EA

2 than two transmit antnnas, th goal is to dsign transmission cods that achiv full divrsity at th highst possibl rat with low dcoding complxity. In our 2 2 MIMO implmntation, w us two distinct training cods ovr 2 tim multiplxd prambl slots at th transmittr. Whn on transmittr is snding training data in on tim slot, th othr is off. Ths 26-bit prambls ar GSM training squnc cods (TS) and []. Th two transmittrs thn transmit 28 spac-tim ncodd data symbols simultanously bfor th cycl rpats. At th transmittr, th SASRATS transmittrs ar programmd to run a 2 transmit Alamouti ncoding schm, whr two symbols, s and s, ar transmittd simultanously from two transmittrs at tim instant t. At tim instant t + T,th symbols s and s ar transmittd simultanously from th transmittrs whr * rprsnts th complx conjugat. Th transmission matrix is rprsntd by [ ] s s S = s s () Th transmittd symbols travl throug indpndnt channls h and h to a rcivr whr noiss n and n ar addd to th rcivd signals. h and h ar complx multiplicativ distortions assumd constant across two conscutiv symbols. This is dpictd in Figur 2. TX s - s h = TX s * s h 3 = h = RX = n n n n 2 3 RX SASRATS hannl Estimator SASRATS hannl Estimator r r r r 2 3 h h h 3 ombinr s Maximum Liklihood tctor h h VIRTEX FPGA to ombinr h 3 s s to Maximum Liklihood tctor Figur 2. Block diagram of Alamouti dcoding implmntation on SASRATS platform It is shown in [4] that at th input of th combinr, th rciv signals ar givn by r = r(t) =h s + h s + n r = r(t + T )= h s + h s + n (2) s In our implmntation[], a ral-tim FPGA basd channl stimator producs th stimats ĥ and ĥ and this information is fd to th combinr to yild two combind output signals s = ĥ r + ĥr s = ĥ r ĥr (3) Th signals s and s ar snt to th maximum liklihood (ML) dtctor so that ML stimats ˆs and ˆs can b mad of s and s. As w us PSK modulation of th symbols at th transmittr (qual nrgy constllations), th ML dtctor dos not nd channl stimats and th dcision rul in th ML dtctor is simplifid to choos s i iff d 2 ( s,s i ) d 2 ( s,s k ), i = k for ˆs and choos s i iff d 2 ( s,s i ) d 2 ( s,s k ), i = k for ˆs whr d 2 (x, y) is th squard Euclidan distanc btwn signals x and y. Th complxity of th combinr and ML dtctor dpnds on typ of modulation. Binary phas shift kyd (BPSK) symbols ar th simplst to dtct. tction of non qual nrgy modulation schms rquir channl stimats in th ML dtctor and has highr complxity. Th prsnt work considrs BPSK and PSK implmntations only. Implmntation of a MIMO 2 transmittr and 2 rcivr Alamouti systm, rquirs th stimation of 4 channls (ĥ, ĥ, ĥ2 and ĥ3), 2 at ach rcivr as shown in Figur 2. In this situation, th output of combinr yilds 2 outputs s = ĥ r + ĥr + ĥ 2 r 2 + ĥ3r 3 s = ĥ r ĥr + ĥ 3 r 2 ĥ2r 3 (4) whr ĥ2 and ĥ3 ar channl stimats from th scond rcivr. In th cas of a 2 2 Alamouti implmntation using PSK signals, th ML dcodr rmains unchangd xcpt for th combinr. As sn from (4), th combinr output s is actually th sum of s from rcivr and s from rcivr. Likwis, s is actually th sum of s from rcivr and s from rcivr. Thus a 2 M Alamouti implmntation can b asily implmntd by summing togthr th appropriat combinr outputs from M rcivrs bfor fding on ML dtctor. In an xtndd vrsion of Alamouti for 4 transmittrs [2], full rat is achivd but th systm is half rank (quasi-orthogonal) with som loss in divrsity as transmittd symbols cannot b fully dcoupld. Tarokh s STB schm [3] for 4 transmittrs on th othr hand, achivs complt orthogonality at half th full rat. Tarokhs schm suffrs no loss in divrsity and rcivr dcoding is simplr as th transmittd symbols can b fully dcoupld. Th dcoding of th Alamouti ncodd signals is a linar procss and our SASRATS rcivr systm dsign implmnts th combinr and maximum liklihood dtction on th Xilinx Virtx 2 Pro FPGA board using th Xilinx Intgratd Systm Enviromnt (ISE) Foundation dsign tool. 4

3 At th SASRATS rcivrs, th I and outputs ar fd into a Xilinx Univrsity Program Virtx 2 Pro vlopmnt Systm board basd on th Virtx 2 Pro X2VP3 with 3,86 logic clls. This low cost dvlopmnt board from igilnt Inc. has four 2-bit wid ports which ar idal for our 4 rcivr systm. Th complt dsign is implmntd using a top down hirarchical schmatic ntry approach on th Xilinx Intgratd Systm Enviromnt (ISE) Foundation dsign tool. VHL cod can also b intgratd as a block with othr schmatic componnts if dsird. W hav also mad xtnsiv us of various Xilinx or Gnrator intllctual proprty(ip) moduls incorporatd within th ISE Foundation toolst to shortn dsign cycl tim. h* r h r* h* r h r* h_x(6:) h_y2(6:) r_x(6:) r_y(6:) h_x(6:) h_y(6:) r_x(6:) r_y2(6:) h_x(6:) h_y2(6:) r_x(6:) r_y(6:) h_x(6:) h_y(6:) r_x(6:) r_y2(6:) OMPLEX MUIPLIERS ar(6:) ai(6:) br(6:) bi(6:) c ar(6:) ai(6:) br(6:) bi(6:) c ar(6:) ai(6:) br(6:) bi(6:) c ar(6:) ai(6:) br(6:) bi(6:) c pr(6:) pi(6:) pr(6:) pi(6:) pr(6:) pi(6:) pr(6:) pi(6:) ER A(6:) S(6:) B(6:) A(6:) S(6:) B(6:) A(6:) S(6:) B(6:) A(6:) S(6:) B(6:) SUBTRATOR RE_S(6:) IMJ_S(6:) RE_S(6:) IMG_S(6:) R(s) Img(s) OUTPUTS R(s) Img(s) IV. IMPLEMENTATION OF THE ALAMOUTI AN ML EOER W bgin by first dscribing th ovrall architctur of th Alamouti 2 dcoding schm for PSK modulatd rcivd symbols as shown in Figur 3. r, r h h X_IN(6:) Y_IN(6:) ENABLE h_x(6:) h_y(6:) h_x(6:) h_y(6:) GLOBAL_ PRE- X_IN(6:) Y_IN(6:) h_y(6:) h_y(6:) r_x(6:) r_y(6:) r_x(6:) r_y2(6:) h_y2(6:) h_y2(6:) GLOBAL_ s_ s_ s_ ML_LATH_ s_ ATA_OUTPUT OUTPUT ATA FORMATTER r_x(6:) r_y(6:) RE_S(6:) r_x(6:) r_y2(6:) IMJ_S(6:) h_y2(6:) h_y2(6:) h_x(6:) h_y(6:) h_x(6:) RE_S(6:) h_y(6:) IMG_S(6:) S S MAXIMUM LIKELIHOO ETETOR SYMBOL_A(6:) RE_Si(6:) SYMBOL_B(6:) SYMBOL_(6:) IMG_Si(6:) SYMBOL_(6:) SYMBOL_A(6:) RE_Si(6:) SYMBOL_B(6:) SYMBOL_(6:) IMG_Si(6:) SYMBOL_(6:) A(5:) B(5:) (5:) (5:) A(5:) B(5:) (5:) (5:) BIT_ BIT_ BIT_ BIT_ OUTPUT OUTPUT_BITS Figur 3. Block diagram of th Alamouti combinr and maximum liklihood dtctor implmntation on th SASRATS rcivr platform Th architctur consists of svral blocks; th prcombinr, combinr, ML dtctor and output data formattr. Th inputs into th pr-combinr block consist of 6-bit I and data and channl stimats ĥ and ĥ which rmain static for th duration of 28 data symbols. On rcipt of th ata Valid (V) puls from th channl stimator, th pr-combinr circuitry latchs to captur r and r ovr two symbol priods and calculats th complx conjugats of ĥ, ĥ and r ndd in th combinr. This is achivd by prforming a two s complmnt opration on th imaginary parts of ĥ, ĥ and r using th Xilinx Two s omplmnt IP modul. Th combinr block as shown in Figur 4 calculats s and s. Th product trms ĥ r, ĥr, ĥ r and ĥrar first calculatd in 4 sparat Xilinx omplx Multiplir v2. IP blocks. Th product trms ĥ r and ĥr ar thn summd to comput s. Th signal s is thn formd by taking diffrnc btwn ĥ r and ĥr by two proprly configurd Xilinx Addr/Subtractr v7. IP cors rspctivly. S S Figur 4. Block diagram of th combinr Th outputs s and s, ar thn fd into th maximum liklihood (ML) dtctor procssing block. Th ML block consist of 2 paralll and indpndnt sts of Euclidan distanc calculators and minimum distanc comparators as shown in Figur 3 whr th dcision statistics, s and s ar procssd indpndntly. R(s) RE_Si(6:) Imag(s) IMG_Si(6:) SYMBOL IFFEREN A(6:) A(6:) A(6:) A(6:) A(6:) A(6:) A(6:) A(6:) S(6:) S(6:) S(6:) S(6:) S(6:) S(6:) S(6:) S(6:) SUARER a(6:) b(6:) a(6:) b(6:) a(6:) b(6:) a(6:) b(6:) a(6:) b(6:) a(6:) b(6:) a(6:) b(6:) a(6:) b(6:) o(6:) o(6:) o(6:) o(6:) o(6:) o(6:) o(6:) o(6:) A(6:) B(6:) A(6:) B(6:) A(6:) B(6:) A(6:) B(6:) ER PARALLEL SUARE EULIEAN ISTAN ALULATOR S(6:) S(6:) S(6:) S(6:) OUTPUTS SYMBOL_A(6:) SYMBOL_A () SYMBOL_B(6:) SYMBOL_B () SYMBOL_(6:) SYMBOL_ () SYMBOL_(6:) SYMBOL_ () Figur 5. Block diagram of th squard uclidan distanc block in th ML dtctor Th Euclidan distanc calculator block shown in Figur 5 first calculats in paralll, th diffrnc btwn th symbol dcision statistic and 4 prstord PSK symbols (±.77 ± j.77). Th ral and imaginary parts of ach symbol ar thn squard and addd togthr. Th 4 squard Euclidan distanc outputs (A,B, and ) ar fd into th minimum Euclidan distanc comparator block shown in Figur 6. Th minimum Euclidan distanc comparator is implmntd using 6 two-input magnitud comparators. Thr ar two outputs (x > y,x < y) from ach comparator. Th outputs from th various comparators ar AN d togthr 4

4 A[5:] B[5:] A[5:] B[5:] A[5:] B[5:] A[5:] B[5:] A[5:] B[5:] A[5:] B[5:] LR LR LR LR OR4 OR2 OR2 SYMBOL_A(6:) RE_Si(6:) SYMBOL_B(6:) SYMBOL_(6:) IMG_Si(6:) SYMBOL_(6:) SYMBOL_A(6:) RE_Si(6:) SYMBOL_B(6:) SYMBOL_(6:) IMG_Si(6:) SYMBOL_(6:) X_IN(6:) r_x(6:) Y_IN(6:) r_y(6:) h_y(6:) h_y(6:) r_x(6:) r_y2(6:) h_y2(6:) h_y2(6:) X_IN(6:) r_x(6:) Y_IN(6:) r_y(6:) h_y(6:) h_y(6:) r_x(6:) r_y2(6:) h_y2(6:) h_y2(6:) A(5:) B(5:) (5:) (5:) A(5:) B(5:) (5:) (5:) BIT_ BIT_ BIT_ BIT_ r_x(6:) r_y(6:) RE_S(6:) r_x(6:) r_y2(6:) IMJ_S(6:) h_y2(6:) h_y2(6:) h_x(6:) h_y(6:) h_x(6:) RE_S(6:) h_y(6:) IMG_S(6:) r_x(6:) r_y(6:) r_x(6:) r_y2(6:) h_y2(6:) h_y2(6:) h_x(6:) h_y(6:) h_x(6:) h_y(6:) RE_S(6:) IMJ_S(6:) RE_S(6:) IMG_S(6:) GLOBAL_ s_ s_ s_ ML_LATH_ s_ ATA_OUTPUT S_X_RX(6:) S_Y_RX(6:) S_X_RX(6:) S_Y_RX(6:) S_X_RX(6:) S_Y_RX(6:) S_X(6:) S_X_RX(6:) S_Y(6:) S_Y_RX(6:) S_X_RX2(6:) S_X(6:) S_Y_RX2(6:) S_Y(6:) S_X_RX2(6:) S_Y_RX2(6:) S_X_RX3(6:) S_Y_RX3(6:) S_X_RX3(6:) S_Y_RX3(6:) A B A(5:) B(5:) (5:) (5:) MAGNITUE OMPARATORS OMPM6 A,B OMPM6 A, OMPM6 A, OMPM6 B, OMPM6 B, OUTPUT LATHES 'A' IS MIN F_ 'B' IS MIN F_ '' IS MIN F_ '' IS MIN F_ OMPM6 HOOSE_A, HOOSE_B HOOSE_ HOOSE_ BIT_ PSK EOE BITS Figur 6. Block diagram of th minimum distanc comparator block in th ML dtctor BIT_ r, r RX_ h h h2 h3 r2, r3 S S X_IN(6:) Y_IN(6:) h_x(6:) h_y(6:) h_x(6:) h_y(6:) X_IN_RX(6:) Y_IN_RX(6:) RX RX _RX h_x_rx(6:) h_y_rx(6:) h_x_rx(6:) h_y_rx(6:) PRE- _RX _RX _RX MAXIMUM LIKELIHOO ETETOR S S GLOBAL_ OUTPUT ATA FORMATTER MUI SUMMER OUTPUT OUTPUT_BITS S S OVERFLOW Figur 7. Block diagram of t X 2 Alamouti implmntation and latchd basd on th following minimum magnitud slction critrion which chooss A iff (A <B)&(A<) &(A<), B iff (A >B)&(B<)&(B<), iff (A >)&(B>)&(<), iff (A >)& (B >)&(>4). Only on of th four outputs gos high whn th critrion is mt. Thn th latchd outputs ar fd into two OR gats to dcod th stimatd PSK symbol into bits. Thus ach magnitud comparator for ˆs or ˆs has on 2-bit output which rprsnts ithr,, or. Th output data formattr placs th bit stimats of ˆs and ˆs in th corrct tim position rsulting in a continuous srial bit output which can b stord and chckd agaisnt th original srial bit stram snt at th transmittr for bit rror rat masurmnts. Th systm outputs 4 bits for vry pair of PSK symbols rcivd. Th Alamouti 2 2 dcoding schm on our tstbd is implmntd by duplicating th pr-combinr and combinr blocks for th scond rcivr whr th combinr outputs of both rcivrs ar summd togthr in a multi-rcivr summr block as dfind by (4), as shown in Figur 7, to form th nw combind output s and s prior to ML dtction. Th sam procss is rpatd for th Alamouti 2 3 and 2 4 schms. In all cass, only on ML dtctor block is ndd. Th sam modular approach can b usd to implmnt Tarokh s 4 orthogonal STB [3] with som xtnsions to th rcivr pr-combinr, combinr and ML dtctor dsign. Applying Tarokh s thory of complx gnralisd orthogonal dsigns [3] to a 4 4 schm for xampl, rquirs th pr-combinr to stor sts of 8 rcivd symbols and 4 channl stimats pr rcivr prior to combining, ML dtction and stimation of 4 symbols. Implmntation is byond th scop of this papr, but is straightforward. V. EXPERIMENTAL VERIFIATION OF THE ML ETETOR Th first xprimnt to tst th opration of th ML dtctor is prformd on a 2 stup of th SASRATS platform as shown in Figur 8. TX and TX ach transmit tim IGITAL TRANSMITTER TX IGITAL TRANSMITTER TX Figur 8. vrification HP 759B RAIO FREUENY HANNEL SIMULATOR OMPUTER NIA Input IGITAL RX XILINX VIRTEX 2 PRO EVELOPMENT BOAR SASRATS stup with HP759B for channl stimation multiplxd GSM prambls TS cods and rspctivly btwn data frams at 95 MHz. Th two transmittrs ar programmd to transmit Alamouti spac-tim ncodd data during th data fram. Th modulation is BPSK and symbol rat is 5 kbaud. In this xprimnt, a Hwltt Packard 759B radio frquncy channl simulator is programmd to gnrat two indpndnt uncorrlatd Rayligh flat fading channls. 48 kbit stimats from th output of th ML dtctor ar capturd by th NIA card and compard with th actual transmittd bits in Matlab. Alamouti [4] assums that thy ar constant across two conscutiv symbols but in a practical implmntation, this rquirmnt is difficult to mt. In our xprimnt, it is assumd constant across th ntir data fram of 28 symbols. W hav vrifid in Matlab that at an avrag SNR valu of 25 db, thr ar virtually no rrors proving th corrct opration of th ntir 42

5 systm on FPGA. Th xprimnt was rpatd with PSK modulation of data symbols with similar rsults. To tst opration with mor than on rcivr, th SAS- RATS platform is rconfigurd into a 2 2 MIMO systm with th HP759B rmovd as th channl simulator cannot gnrat mor than 2 Rayligh fading channls. In th lab, 4 antnnas spacd sufficintly apart ar connctd to th transmittr outputs and rcivr inputs. It was found that undr ths conditions, th channls at 95MHz ar highly corrlatd and xprinc almost no fading. W ar abl to procss th information from th FPGA to confirm opration of th ML spac-tim dcodr. At a high SNR valu of 3 db, thr ar no rrors dspit highly corrlatd channls using both BPSK and PSK modulatd symbols. W hav also tstd th SASRATS platform configurd as a 2 4 Alamouti MIMO systm with xcllnt prformanc. VI. ONLUSIONS W hav dscribd th implmntation of a ral tim maximum liklihood Alamouti dcodr for us on our MIMO platform implmntd on an FPGA using th Xilinx ISE tool and or Gnrator IP moduls. W hav also xprimntally vrifid th opration of th dcodr in a closd Alamouti 2 divrsity schm using an RF channl simulator and also in an opn 2 2 and 2 4 antnna basd systm undr corrlatd channl conditions. REFERENS [7] S. aban t al., Vinna MIMO tstbd, EURASIP Journal on Applid Signal Procssing, vol , pp. 3, 26. [8] P. F. P. Murphy and. ick, An fpga implmntation of alamoutis transmit divrsity tchniqu, Univrsity of Txas WNG Wirlss Ntworking Symposium, Oct. 23. [9] P. Grn and. Taylor, Implmntation of four ral-tim softwar dfind rcivrs and a spac-tim dcodr using xilinx virtx 2 pro fild programmabl gat array, Procdings of th Third IEEE Intrnational Workshop on Elctronic sign, Tst and Applications., pp , Jan. 26. [], Implmntation of a ral-tim multipl input multipl output channl stimator on th smart antnna softwar radio tst systm platform using th xilinx virtx 2 pro fild programmabl gat array, Procdings of t6 IEEE Intrnational onfrnc on Fild Programmabl Tchnology., pp , c. 26. [] ETSI/GSM, Multiplxing and multipl accss on th radio path, GSM Rcommndations ocumnt 5.2 Vrsion 3.8, c [2] M. Rupp and. Mcklnbraukr, On xtndd alamouti schms for spac-tim coding, Wirlss Prsonal Multimdia ommunications, 22. Th 5th Intrnational Symposium on, vol., pp. 5 9, Oct. 22. [3] V. Tarokh, H. Jafarkhani, and A. aldrbank, Spac-tim block cods from orthogonal dsigns, IEEE Transactions on Information Thory, vol. 45, no. 5, pp , 999. [] P. Grn and. Taylor, Smart antnna softwar radio tst systm, Procdings of th First IEEE Intrnational Workshop on Elctronic sign, Tst and Applications., vol.,pp , Jan. 22. [2], Exprimntal vrification of spac-tim algorithms using th smart antnna softwar radio tst systm (sasrats) platform, Prsonal, Indoor and Mobil Radio ommunications, 24. PIMR 24. 5th IEEE Intrnational Symposium on, vol. 4, pp , 24. [3], Implmntation of a high spd four transmittr spac-tim ncodr using fild programmabl gat array and paralll digital signal procssors, Procdings of th Third IEEE Intrnational Workshop on Elctronic sign, Tst and Applications., pp , Jan. 26. [4] S. Alamouti, Spac block coding: A simpl transmittr divrsity tchniqu for wirlss communications, IEEE J. Slct. Aras. ommunication, vol. 6, pp , Oct [5]. Gsbrt t al., From thory to practic: An ovrviw of mimo spac-tim codd wirlss systms, IEEE Journal on Slctd Aras in ommunications, vol. 2, pp , Apr. 23. [6] R. M. Rao t al., Multi-antnna tstbds for rsarch and ducation in wirlss communications, IEEE ommunications Magazin, vol. 42, no. 2, pp. 72 8,