Asian Power Electronics Journal

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1 Asian Powr Elctronics Journal, Vol.5 No.1 Aug 211 Asian Powr Elctronics Journal PERC, HK PolyU i

2 Asian Powr Elctronics Journal, Vol.5 No.1 Aug 211 Copyright Th Hong Kong Polytchnic Univrsity 211 All right rsrvd. No part of this publication may b rproducd or transmittd in any form or by any mans, lctronic or mchanical, including photocopying rcording or any information storag or rtrival systm, without prmission in writing form th publishr. First dition August 211 Printd in Hong Kong by Rprographic Unit Th Hong Kong Polytchnic Univrsity Publishd by Powr Elctronics Rsarch Cntr Th Hong Kong Polytchnic Univrsity Hung Hom, Kowloon, Hong Kong ISSN Disclaimr Any opinions, findings, conclusions or rcommndations xprssd in this matrial/vnt do not rflct th viws of Th Hong Kong Polytchnic Univrsity ii

3 Asian Powr Elctronics Journal, Vol.5 No.1 Aug 211 Editorial board Honorary Editor Prof. Frd C. L Elctrical and Computr Enginring, Virginia Polytchnic Institut and Stat Univrsity Editor Prof. Yim-Shu L Victor Elctronics Ltd. Associat Editors and Advisors Prof. Philip T. Krin Dpartmnt of Elctrical and Computr Enginring, Univrsity of Illinois Prof. Kyu Smdly Dpartmnt of Elctrcial and Computr Enginring, Univrsity of California Prof. Muhammad H. Rashid Dpartmnt of Elctrical and Computr Enginring, Univrsity of Wst Florida Prof. Dhong Xu Collg of Elctrical Enginring, Zhjiang Univrsity Prof. Hirofumi Akagi Dpartmnt of Elctrical Enginring, Tokyo Institut of Tchnology Prof. Xiao-zhong Liao Dpartmnt of Automatic Control, Bijing Institut of Tchnology Prof. Wu Ji Elctric Powr Collg, South China Univrsity of Tchnology Prof. Hao Chn Dpt. of Automation, China Univrsity of Mining and Tchnology Prof. Danny Sutanto Intgral Enrgy Powr Quality and Rliability Cntr, Univrsity of Wollongong Prof. Siu L.Ho Dpartmnt of Elctrical Enginring, Th Hong Kong Polytchnic Univrsity Prof. Eric Chng Dpartmnt of Elctrical Enginring, Th Hong Kong Polytchnic Univrsity Dr. Norbrt Chung Dpartmnt of Elctrical Enginring, Th Hong Kong Polytchnic Univrsity Dr. Kvin Chan Dpartmnt of Elctrical Enginring, Th Hong Kong Polytchnic Univrsity Dr. Tz F. Chan Dpartmnt of Elctrical Enginring, Th Hong Kong Polytchnic Univrsity Dr. Edward Lo Dpartmnt of Elctrical Enginring, Th Hong Kong Polytchnic Univrsity Dr. David Chng Dpartmnt of Industrial and Systm Enginring, Th Hong Kong Polytchnic Univrsity Dr. Martin Chow Dpartmnt of Elctronic and Information Enginring, Th Hong Kong Polytchnic Univrsity Dr. Frank Lung Dpartmnt of Elctronic and Information Enginring, Th Hong Kong Polytchnic Univrsity iii

4 Asian Powr Elctronics Journal, Vol.5 No.1 Aug 211 Publishing Dirctor: Prof. Eric Chng Dpartmnt of Elctrical Enginring, Th Hong Kong Polytchnic Univrsity Communications and Dvlopmnt Dirctor: Ms. Anna Chang Dpartmnt of Elctrical Enginring, Th Hong Kong Polytchnic Univrsity Editorial Committ: Prof. Bhim Singh Prof. B.P.Divakar Prof. Dhong Xu Prof. K.Krthivasan Prof. Wang xiaoyuan Prof. Xiaozhong Liao Prof. Xi Yu Prof. Zh Chn Dr. Bnny Y.P.Yung Dr. B. Gthalakshmi Dr. B.Vinod Dr. C. Christobr Asir Rajan Dr. Chi Kwan L Dr. Dong Ping Dr. Dong Li Dr. Durairaj Dr. E. Chandra Skaran Dr. Frank H. Lung Dr. Gao Yanxia Dr. Jams Ho Dr. Kai Ding Dr. Lu Yan Dr. Martin Chow Dr. Mohan V Awar Dr. Patrick C. K.Luk Dr. P.Ajay-D-Vimal Raj Dr. Prasad Dr. R. Zaimddin Dr. S. Chandramohan Dr. Sudhir Kumar Srivastava Dr. Syd Sad Fazl Dr. Shu Ji Dr. S. P. Natarajan Dr. S. X.Wang Dr. Tz F. Chan Dr. Wai Chwn Gan Dr. W. N. Fu Dr. Xu Xiang Dang Dr. Y. B. Ch Dr. Yang Jinming Dr. Zng Jun. Dr. Z. Y. Dong iv

5 Asian Powr Elctronics Journal, Vol.5 No.1 Aug 211 Production Coordinator: Mr. Dickson Chau & Mr. Ng Tsz Wang Powr Elctronics Rsarch Cntr, Th Hong Kong Polytchnic Univrsity Scrtary: Ms. Canary Tong Dpartmnt of Elctrical Enginring, Th Hong Kong Polytchnic Univrsity v

6 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 Tabl of Contnt Fiv-lvl NPC-VSI Capacitor Voltag Balancing Using a Novl Clamping Bridg R. Chibani E.M. Brkouk and M.S. Bouchrit 1 Implmntation of Thr phas Shunt Hybrid Filtr Using ICOSφAlgorithm Sindhu.S Sindhu M.R Manjula G.Nair and Ginns.K.John 7 PI with Fuzzy Logic Controllr basd Activ Powr Lin Conditionrs Karuppanan P. and Kamala Kanta Mahapatra 13 Dynamic Prformanc Analysis of Slf-commutating PWM CSI-fd Induction Motor Driv undr MATLAB Environmnt S.M. Tripathi and A.K. Pandy 19 Voltag Sag Rstorr with Diod-Clampd Multilvl Bridg K. Ding, K. W. E. Chng, S. L. Ho, K. P. Wong & S. X. Wang 25 Author Indx 32 vi

7 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 Fiv-lvl NPC-VSI Capacitor Voltag Balancing Using a Novl Clamping Bridg R. CHIBANI 1 E.M. BERKOUK 2 M.S. BOUCHERIT 3 Abstract- A srious constraint in multilvl invrtrs is th capacitor voltag-balancing problm. Th unbalanc of th diffrnt DC voltag sourcs of th fiv-lvl Nutral Point Clamping Voltag Sourc Invrtr (NPC-VSI) constitutd th major limitation for th us of this powr convrtr. To rmdy to this problm, a nw control solution to compnsat th unbalancd DC voltags for th fiv-lvl NPC VSI is prsntd. It provids a fast and flxibl control of th invrtr capacitor voltags, lads to a simplr implmntation, and prsnt high qualization fficincy. Simulation rsults show th ffctivnss of our mthods. Kywords- Clamping bridg, fiv-lvl, NPC VSI, Lyapunov function, Sliding mod control. I. INTRODUCTION In 198, arly intrst in multilvl powr convrsion tchnology was triggrd by th work of Naba, who introducd th nutral-point-clampd (NPC) invrtr topology [1]. It was immdiatly ralizd that this nw convrtr had many advantags ovr th mor convntional two-lvl invrtr. Subsquntly, th concpt of th thr-lvl convrtr was xtndd furthr and som nw multilvl topologis wr proposd. An altrnativ to th diod-clampd convrtr, th flying capacitor topology dos not hav issus with clamping diods. First proposd in 1992 [2], this approach has th advantag of a largr numbr of rdundant switching stats, which allows mor frdom in balancing th clamping capacitors voltags. Th main disadvantag is th potntial for parasitic rsonanc btwn th dcoupling capacitors; this is mad vn wors by th high numbr of capacitors, which complicats packaging for small inductanc. In addition, thr ar issus with voltag rdistribution in th cas of voltag surgs. Nvrthlss, th flying capacitor topology sms vry promising. Th multilvl configuration with cascadd H-bridg invrtrs prsnts anothr altrnativ in th dsign of multilvl convrtrs [3]. A primary advantag of this topology is that it provids th flxibility to incras th numbr of lvls without introducing complxity into th powr stag. Also, this topology rquirs th sam numbr of primary switchs as th diod-clampd topology, but dos not rquir th clamping diod. Howvr, this configuration uss multipl ddicatd DCbusss and oftn a complicatd and xpnsiv lin transformr, which maks this a rathr xpnsiv solution. In addition, bi dirctional opration is somwhat difficult (although not impossibl) to achiv. Th papr first rcivd 3 Aug 29 and in rvisd form 24 Jul 211 Digital Rf: A ,2,3 Procss Control Laboratory of th National Polytchnic School of Algirs, 1, Ru Hassn BADI. ELHarrach BP182 Algirs ALGERIA 1 (corrsponding author -mail: rdha29@yahoo.fr). Prhaps th most important improvmnt in cascadd convrtr topologis is th hybrid multilvl topology [4]. Th main strngth of this approach is its combination of th high voltag capacity of th rlativly slow GTO dvics with th high switching frquncy of th lowr voltag capacity IGBT dvics. At th sam tim, th diffrnt voltag lvls of th IGBT and GTO bridgs crat an additional voltag lvl without any additional complxity. On important problm associatd with th NPC invrtr is its Nutral Point (NP) variation [1]. Th DC link NP potntial can significantly fluctuat or continuously drift to unaccptabl lvls du to non uniform switching dvic or DC link capacitor charactristics or fluctuation bcaus of th irrgular and unprdictabl charging and discharging in ach capacitor [5-7]. Som solutions hav bn proposd, which ar basd on rdundant switching configurations [1] [8-15] or on th addition of zro-squnc voltag componnts to th output voltag [9]. Unfortunatly, ths mthods modify th output voltag wavform. As th numbr of invrtr-lvls incrass, th problm of capacitor balancing bcoms mor complx and th solution vry drastic. Th unbalanc DC voltag problm can also b solvd by sparat DC sourcs [6] or by adding lctronic circuitry. In [16-18], clamping bridgs basd on transistors and rsistors ar proposd as a solution to this problm. This papr dals introducs a nw clamping bridg for th DC capacitor voltag qualisation has bn proposd to DC-link capacitors voltags fluctuations in an NPC VSI that prmits to achiv a corrct capacitors voltags sharing, whn convntional balancing mthods compnsat fail. Th organization of this papr is as follows. Sction 2 dvlops th mathmatical modlling of th DC-AC convrtr fiv-lvl NPC-VSI and its Puls Width Modulation control stratgy (PWM) using four bipolar carrirs. Th control of th two-lvl PWM currnt rctifir by Lyapunov function using fdback loops to rgulat th avrag valu of DC voltags and th ntwork currnts ar discussd in sction 3. Thrfor, a clamping bridg control is introducd to improv th prformanc of voltag balanc stratgy in sction 4. Finally, in th sction 5, simulations will b implmntd to prsnt a study of th phnomnon, to dmonstrat th proposd mthod and to rport th ffctivnss of this solution. II. FIVE-LEVEL CASCADE W firstly propos a knowldg modl of th thrphas fiv-lvl NPC-VSI invrtr and dvlop a PWM stratgy to control it (four bipolar carrirs). Th global schm of th cascad is givn on th Fig mail: mbrkouk@yahoo.fr 3 -mail: ms_bouchrit@yahoo.fr 1

8 Chibani R. t.al : Fiv-Lvl NPC-VSI Capacitor... This stratgy uss four bipolar carrirs ( U, p1 U, p 2 U, p3 U ). It is charactrisd by two paramtrs m th p 4 indx modulation and r th modulation rat. Th algorithm of this stratgy can b summarisd as follows: 2 Fig.1: Structur of th cascad proposd A. Fiv-lvl NPC-VSI modlling Th gnral structur of th thr-phas fiv-lvl NPC voltag sourc invrtr is shown on th figur 2. It is composd by 24 pairs transistor-diod. Evry lg of this invrtr includs ight pairs, four on th uppr half lg and four on th lowr on. Th optimal control law is givn blow: B = B k 1 k 5 B = B k 2 k 4 B = B (1) k 3 k 6 B k 7 = B k 1. B k 2. B k 3 B k 8 = B k 4. B k 5. B k 6 Bks is th control signal of TD ks. TD ks rprsnt vry pair transistor-diod by on bi-dirctional switch. Th voltag of th thr-phas A, B, C rlativly to th middl point M and using th half lg connction b functions F km ar givn by V XM with x = point A, B or C and k=1,2,3. b V XM = [ F k 1.( U c1 + U c 2 ) + F k 7.( U c1 )] (2) b [ F k.( U c 3 + U c 4 ) + F k 8.( U c 3 )] Th input currnts of th thr-phas fiv-lvl invrtr using th load currnts ar givn by th following rlations: b b b i d 1 = F 11. i1 + F 21. i 2 + F 31. i 3 b b b i d 2 = F 11. i1 + F 21. i 2 + F 31. i 3 b b b i = F. i + F. i + F i d b b b d 4 F 1. i1 + F 2. i 2 + F 3. i 3 i i = (3) = i + i + i i i i i d d1 d 2 d 3 d 4 B. Control stratgy of th invrtr For a fiv-lvl invrtr, four carrir wavs and thr modulation signals ar usd. th modulation wavs ar compard with th triangular carrir wavs and at th intrsction points th switching dcisions ar mad for th associatd switchs. Puls Width Modulation (PWM) of multilvl convrtrs is typically an xtnsion of two-lvl mthods. Th most common typs of multilvl voltag-sourc PWM ar sin-triangl modulation and spac-vctor modulation (SVM). Multilvl sin-triangl modulation rlis on dfining a numbr of triangl wavforms and switching ruls for th intrsction of ths wavforms with a commandd voltag wavform [13 14]. This mthod is fairly straightforward and insightful for dscription of multilvl systms. Stp 1: Dtrmination of th intrmdiat voltags If V rfk > U thn p 1 V XM 1 = + U c If V If If If If If V < U thn rfk p 1 XM 1 = V rfk > U thn p 2 V XM 2 = + 2U c V rfk < U thn p 2 V XM 2 = + U c V > U thn V (4) rfk rfk p 3 V < U thn V rfk p 3 p 4 XM 3 = = XM 3 U c V > U thn V XM 4 = U c If V rfk < U thn V p 4 XM 4 = 2U c Stp 2: Dtrmination of th output voltag (X=A, B,C) V = V + V + V + V (5) XM XM 1 XM 2 XM 3 XM 4 III.TWO-LEVEL PWM CURRENT RECTIFIER Th control of th two-lvl PWM currnt rctifir by Lyapunov Function using fdback loops to rgulat th output DC voltag and th ntwork currnts ar givn. Th gnral structur of th two-lvl PWM currnt rctifir is givn on th Fig 3. Fig.2: Gnral structur of th thr-phas fiv-lvl NPC VSI. Fig.3: Structur of th two-lvl PWM currnt rctifir A. Voltag fdback control

9 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 For ach phas k (k=1, 2 or 3) of th thr-phas ntwork fding, th rctifir considrd can b rprsntd by a R,L circuit. V rsk is th voltag of on phas k of th thrphas ntwork and V k is th voltag of th lg k of th rctifir [17]. Th voltag loop imposs th ffctiv valu of th rfrnc currnt of th ntwork corrsponding to th powr xchangd btwn th ntwork and th continu load (Fig 4). Fig.4: Control algorithm of th avrag output DC voltag of th two-lvl PWM currnt rctifir. To guarant th global asymptotic stability in th voltag loop, w obtain I as th output valu of th voltag rgulator: 4. U C I =.[ I ch K U. C.( U C U Crf )] (6) 3. V B. Currnt fdback control W control th ntwork currnt of th phas 1 and 2 by a sliding mod rgulator. Th algorithm of this currnt loop is givn on th Fig 5. In this schm, th transfr function H (s) is xprssd as follows: I rsk 1 H( s) = = (7) V R + L. s scond catgory using carrir-basd puls width modulation (PWM) schm, a zro squnc voltag signal is addd to th modulation signals. In som schms using zro squnc voltag to balanc DC capacitor voltags, knowldg of load powr factor (or dirction of instantanous powr flow) is rquird which is difficult to implmnt undr transint conditions, and in othrs, masurmnts of both capacitor voltags and load currnts (magnituds or polaritis) ar rquird. Unfortunatly, ths mthods modify th output voltag wavform. Also, as th numbr of invrtr-lvls incrass, th problm of capacitor balancing bcoms mor complx and th solution vry drastic. By using a sparat supply for ach DC-link lvl, th balancing issus ar solvd [6]. Howvr, this solution is xpnsiv spcially for mor thn thr-lvl. Anothr solution consists of adding lctronic circuitry. In [16-18], clamping bridgs basd on transistors and rsistors (dissipativ mthod) ar proposd as a solution to this problm. Advantags ar low cost and low complxity. Disadvantags ar high nrgy losss, high currnt switchs and costly dsign thrmal managmnt rquirmnts for larg valus. This mthod is bst suitd for systms that ar chargd oftn with small currnts. In ordr to rmdy to th unbalanc problm, w suggst a solution which consists in stablish a bridg balancing btwn th rctifir and th intrmdiat filtr (Fig 6). Th aim of this us is to limit and stabilis variations of th input DC voltags of th invrtr. Fig.5: Control algorithm of th ntwork currnt i rsk of th thrlvl PWM rctifir. To guarant th global asymptotic stability in th currnt loop, w obtain N gk as th output of th currnt rgulator: 1 2. π Ngk = V rsk RI. rsk Iω L 2cos( ωt ( k 1) + KL i ( irsk irfk) 4. U C 3 (8) IV. CLAMPING BRIDGE In this sction, a clamping bridg control is introducd to balanc th four DC input voltags, avoid NP potntial drift and improv th prformancs of th spd control of th prmannt magnt synchronous machin. Svral publications hav discussd ways to solv this balancing problm in thr-lvl NPC-VSI [8-17]. Th multitud of proposals (slction of appropriat voltag vctors) implmntd to nsur DC voltag balancing can b broadly dividd into two catgoris. In th first catgory basd on spac vctor ralization, rdundant switching stats of th convrtr ar usd whil in th Fig. 6: Structur of th clamping bridg Th capacitor voltag qualization clamping bridg schm has many advantags such as highr qualization fficincy and a modular dsign approach. As shown in Figur 6, switchs T 1, T 2, T 3 and T 4 ar MOSFET; diods D 1, D 2, D 3 and D 4 ar continud flow diods; L 1 and L 2 is th nrgy storag inductors; C 1, C 2, C 3 and C 4 ar four adjacnt sris clls, rspctivly. Th basic oprational principl is as follows: * Whn U c1 >U c2, a driv signal is givn to th switchs, and switch T 2 is turnd off and T 1 is turnd on. Whil T 1 is on, capacitor C 1, switch T 1 and inductor L 1 forms a loop circuit, whos currnt is I c1. Th part of nrgy of capacitor C 1 transfrs to inductor L 1. Whil T 1 is off, capacitor C 2, inductor L 1 and th diod D 2 forms a loop circuit, whos currnt is I c2. Th nrgy of inductor L 1 transfrs to capacitor C 2. * Whn U c1 <U c2, switch T 1 is turnd off and T 2 is turnd on. Th nrgy transfrs from C 2 to C 1 until th voltags of th two capacitors ar th sam. 3

10 Chibani R. t.al : Fiv-Lvl NPC-VSI Capacitor... * Whn U c3 >U c4, a driv signal is givn to th switchs, and switch T 4 is turnd off and T 3 is turnd on. Whil T 3 is on, capacitor C 3, switch T 3 and inductor L 2 forms a loop circuit, whos currnt is I c3. Th part of nrgy of capacitor C 3 transfrs to inductor L 2. Whil T 3 is off, capacitor C 4, inductor L 2 and th diod D 3 forms a loop circuit, whos currnt is I c2. Th nrgy of inductor L 2 transfrs to capacitor C 3. * Whn U c3 <U c4, switch T 3 is turnd off and T 4 is turnd on. Th nrgy transfrs from C 3 to C 4 until th voltags of th two capacitors ar sam. Capacitor voltag qualization control should b implmntd to rstrict th charg-discharg currnt to th allowabl cll limitations in th capacitor string. Th balancing algorithm sarch to fficintly rmov nrgy from a strong capacitor and transfr that nrgy into a wak on until th capacitor voltag is qualizd across all capacitors. Th capacitor voltag qualization clamping bridg schm has many advantags such as highr qualization fficincy and a modular dsign approach. Th balancing algorithms sarch to fficintly rmov nrgy from a strong capacitor and transfr that nrgy into a wak on until th capacitor voltag is qualizd across all capacitors. Fig.8. Output voltag V A for m=6, r=.8 and f=5hz Fig.9. Harmonic spctrum of th voltag V A (m=9 r=.8. A. Switch control stratgy of th clamping bridg Stp 1: Dduction of th sign of th diffrncs. W us th following quations: d ( U c1 U c 2 ) C 1. = ( i L1 i c 2 + id 2 + ic1) dt d ( U c 3 U c 4 ) C 3. = ( i L 2 i c 3 + i c 4 + i d 3) dt Stp 2: Dduction of th command of th transistors U c 2 > U c 1 T 2 = 1; T 1 = U c 1 > U c 2 T 2 = ; T 1 = 1 U > U T = ; T U c 3 c = c 4 > U c 3 T 3 = ; T 4 = 1 (9) (1) (11) Fig.1. Harmonic spctrum of th voltag V A for m=12 and r=.8 Fig.11. Harmonic spctrum of th voltag V A for m=15 and r=.8 V. SIMULATION RESULTS In ordr to validat th solution proposd prviously, w prsnt simulation rsults for th two-lvl PWM currnt rctifir fiv-lvl NPC-VSI PMSM cascad. In th first cas, th clamping bridg will not b usd in ordr to show th instability problm of th four input DC voltags. In th scond on, th solution proposd is introducd to improv th prformancs of DC voltags and PMSM. Fig.12. Charactristics of th voltag V A for m=6 Fig.7. Rfrnc voltags and bipolar carrirs Fig.13: Voltag U c and its rfrnc and th ntwork voltag V rs1, th ntwork currnt i rs1 and its rfrnc i rf1 4

11 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 VI. RESULTS AND DISCUSSIONS Fig.14: Voltag U c1 and Uc3 Fig.15: Voltag U c2 and Uc4 Fig.16: Spd and its rfrnc Fig.17: Elctromagntic torqu Fig.18: d axis currnt (i d ) Fig.19: q axis currnt (i q ) Fig.2: Voltags U c1 and U c2 Fig.21: Voltags U c3 and U c4 Fig.22: Spd and its rfrnc Fig.23: Elctromagntic torqu Fig.24: d axis currnt (i d ) Fig.25: q axis currnt (i q ) Th figur 7 shows th rfrnc voltags and th four bipolar carrirs usd for this stratgy. Th figurs 8 to 11 giv th output voltag V A. and its harmonic spctrum for a modulation indx m=6 (Fig.8), m=9 (Fig.9), m=12 (Fig.1) and m=15 (Fig.11) and a modulation rat r=.8. Th frquncy is 5 Hz. W notic that in th four cass, th harmonics gathr by familis cntrd around frquncis multipl of 4.m.f. Bcaus of th symmtry to th quartr of th priod prsntd by th voltag V A, w obtain only odd harmonics. Th most important harmonics gathr around th first family. Th modulation rat r lts linar adjusting of fundamntal magnitud from r= to r=1 and th harmonics rat dcrass whn r incrass (Fig.12). For valuating th prformancs of th Clamping bridg proposd, two simulations ar prsntd. Th first on propos to study a on two-lvl PWM currnt rctifir Fiv-lvl NPC VSI Prmannt Magnt Synchronous Machin. This study shows particularly th problm of th instability of th input DC voltags of th fiv-lvl NPC VSI and its consqunc on th prformancs of th PMSM spd control for U DC =8V, m=72, r=.8 In ordr to tst th Lyapunov function control of th avrag valu of th output voltag of th two-lvl PWM rctifir, a voltag rfrnc of 2V is applid and at t=1s w incras this rfrnc from 2 to 25V. Th figur 13 shows th voltag U c and its rfrnc obtaind. This voltag follows prfctly its rfrnc (2V). Th ntwork currnt i rs1 of th rctifir is in phas with th ntwork voltag V rs1. Th paramtrs of th nt ar: R=.25Ω ; L=1mH. On th figur 14 and 15, w show prfctly th problm of th unbalanc of th four DC voltags of th intrmdiat capacitors bridg. Th voltags U c2 and U c4 ar dcrasing and th voltags U c1 and U c3 ar incrasing. Th paramtrs of th capacitors ar: C 1 =C 2 =C3=C4= 2µF Th figurs 16 to 19 show th consquncs of th DC voltags drift on th charactristics of th Prmannt Magnt Synchronous Machin. Th spd follows its rfrnc (4 rd/s) but th undulations on th lctromagntic torqu and diffrnt currnts (i d, i q ) ar vry important du to th unbalanc problm of th four input DC voltags. Th paramtrs of th PM synchronous machin ar: L d =L q =3.2mH; R s =1Ω; p=3; Φ f =.13N.m/A; J=6.1-4 kg.m²; F c =9,5.1-5 N.m.s/rad. Thos rsults show th importanc of th stability of th input DC voltags of th invrtr in ordr to hav good prformancs for th spd control of th PM synchronous machin. On th scond simulation, w introduc th clamping bridg proposd in th prcdnt cascad on th Figur 1 in ordr to show th diffrnt input DC capacitor voltag qualization prformancs. W can s on th figurs 2 and 21 that th four voltags (U c1, U c2, U c3 and U c4 ) stabilis around th rfrnc voltag valu (2V) and th DC link capacitor voltags ar qualizd. By using this tchniqu of stabilisation, w can rmark on th figur 22, 23, 24 and 25 that th undulations on th prformancs (Torqu and currnts i d and i q ) of th PMSM disappar and thos prformancs ar improvd by using th inductiv Clamping bridg. Th paramtrs of th Clamping bridg ar: L 1 = 1mH L 2 =1mH. 5

12 Chibani R. t.al : Fiv-Lvl NPC-VSI Capacitor... Th afor-prsntd rsults confirm that th clamping bridg is abl to qualiz DC link capacitor voltags and stabiliz th diffrnt DC voltags around th dsird valu. Th prformancs of spd control of th PMSM ar thn amliorating. VII. CONCLUSION Th prsnt contribution intnds to dmonstrat that prmannt magnt synchronous machin control basd on sliding mod control whn applid with a two-lvl PWM currnt rctifir Fiv-lvl PWM NPC-VSI may contribut both for functional prformancs improvmnt and attnuation of som tchnological limitations. Th input DC voltags ar gnratd by a two-lvl PWM currnt rctifir controlld by Lyapunov function. By this study, w hav particularly shown th problm of th stability and its ffcts on th spd control of PMSM and th input DC voltags sourcs of th invrtr. In th last part of this papr, w propos a simpl solution to stabilis th four DC voltags and this by using a clamping bridg composd by four switchs (pair transistor-diod) and two inductancs. This nondissipativ qualization dsign has many advantags such as high qualization fficincy du to th nondissipativ currnt divrtr, bidirctional nrgy transfrring capability, and a modular dsign. Anothr advantag of this systm is that no closd-loop control is ndd and th procss is slf-limiting: whn voltag qualization is complt, th switching of th capacitors consums minimal nrgy. L d, winding, APPENDIX L q : slf inductanc of th d and q armaturs quivalnt R s : rsistanc of an armatur winding,ω : angular spd. s : Laplac oprator, J : inrtia of th st machin-load, C r : Load torqu, d : Error variabl, S d : Surfac variabl V rsk : Ntwork voltag of on phas k, V k : Voltag of th lg k of th rctifir, R : grid rsistanc L : grid inductanc U : Avrag valu of th four input DC voltags C 1 C2, C3, C, C 4 : input capacitors of th fiv-lvl NPC-VSI V ; : Voltag and currnt of th grid rs i rs V : Effctiv valu of th grid voltag REFERENCES [1] A.Naba, I.Takahashi and H.Agaki, A nw nutral point clampd PWM invrtr, IEEE Transactions on Industrial Application, 1981, Vol IA-17, issu 5, pp [2] T.Mynard and H.Foch. Multi-lvl chopprs for high voltag applications, EPE Journal, Vol 2 No. 1, pp45 5, [3] P. Hammond, A nw approach to nhanc powr quality for mdium voltag ac drivs, IEEE Transactions on. Industrial. Applications., Vol. 33, pp.22 28, Jan./Fb [4] M. D. Manjrkar, P. K. Stimr, and T. A. Lipo, Hybrid multilvl powr convrsion systm: a comptitiv solution for high-powr applications, IEEE Transactions on. Industrial. Applications., vol. 36, pp , May/Jun 2. [5] H.L.Liu, N.S.Choi, G.H.Cho, DSP basd spac vctor PWM for thr-lvl invrtr with DC-link voltag balancing, Procding of IEEE-IECON, Kob, Japan, Octobr 1991, pp [6] H.Mnzis, P.Stimr, J.K Stink, Fiv-lvl GTO invrtrs for larg induction motor drivs, Confrnc rcord IEEE-IAS Annual Mting, Toronto, Canada, 1993, pp [7] D.H.L, S.R.L, Frd.C.L, An analysis of midpoint balanc for th nutral-point-clampd thr-lvl VSI, Procdings of IEEE-PESC 98, Fukuoka, Japan, 1998, pp [8] M. Koyama, T. Fujii, R. Uchida, T. Kawabata, Spac voltag vctor basd nw PWM mthod for larg capacity thr-lvl GTO invrtr, Procding of IEEE IECON, San Digo, CA, USA, Novmbr 1992, pp [9] N. Clanovic, D. Borojvic, A comprhnsiv study of nutral point voltag balancing problm in thr-lvl nutral-point-clampd voltag sourc PWM invrtrs, IEEE Transactions on Powr Elctronics, vol. 15, March 2, pp [1] M. Fracchia, T. Ghiara, M. Marchsoni, M. Mazzucchlli, Optimizd modulation tchniqus for th gnralizd n- lvl convrtr, PESC 1992 Confrnc Rcord, Toldo, Spain, Jun/July 1992, pp [11] P.Purkiat, R.S.Sriamakavacham A nw gnralizd spac vctor modulation algorithm for Nutral-point-clampd Multilvl convrtrs, Progrss in Elctromagntics Rsarch Symposium 26, Cambridg, USA, March.26-29, pp [12] A.Bndr, S.Krstic, J.Vandr Mr, G Vnkataramanan, Comparativ valuation of modulation algorithms for Nutral-Point-Clampd convrtrs, IEEE Transactions on Industry Applications, Vol.41, No. 2, March/April 25, pp [13] Z.Pan, F.Z.Png, K.A.Corzin, V.R.Stfanovic, J.M.Luthn, S.Gataric, Voltag balancing control of Diod Clampd Multilvl Rctifir/Invrtr systms, IEEE Transactions on industry applications, Vol 41, No. 6, Novmbr/Dcmbr 25, pp [14] A.Bndr, G Vnkataramanan, D.Rosn, V.Srinivasan, Modlling and dsign of Nutral-Point voltag rgulator for a thr-lvl Diod Clampd invrtr using multiplcarrir modulation, IEEE Transactions on Industrial Elctronics, Vol 53, No. 3, Jun 26, pp [15] S. Vnkatshmarhu, B.P.Muni, A.D Rajkumar, J.Pravn, Dirct Powr Control stratgis for multilvl invrtr basd custom powr dvics, Procding of th World Acadmy of Scinc, Enginring and Tchnology, Vol 29, May 28, pp [16] R. Chibani, E.M. Brkouk, Fiv-lvl PWM currnt rctifir Fiv-lvl NPC VSI Prmannt magnt synchronous machin cascad, Europan Physical Journal- Applid Physics, No. 3, May 25, pp [17] R.Chibani, E.M. Brkouk, M.S.Bouchrit, Lyapunov control of thr-lvl PWM rctifirs to quilibrat input DC voltags of fiv-lvl NPC-VSI, Intrnational Rviw of Elctrical Enginring, Vol 2, No. 1, January- Fbruary 27, pp [18] Chibani, R. Brkouk, E.M. Bouchrit. M.S. "Fiv-lvl NPC-VSI: Diffrnt ways to balanc input DC link voltags" ELEKTRIKA Journal of Elctrical Enginring, Vol 11, No. 1, July 29, pp

13 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 Implmntation of Thr phas Shunt Hybrid Filtr Using ICOSφAlgorithm Sindhu.S 1 Sindhu M.R 2 Manjula G.Nair 3 Ginns.K.John 4 Abstract This papr prsnts a hybrid filtr configuration to supprss harmonic currnt distortion in th sourc currnt. It is a combination of shunt activ powr filtr and shunt passiv filtr. Major amount of harmonic currnts gnratd by th nonlinar load ar bypassd through th passiv filtr and th activ powr filtr supplis th rmaining harmonics and ractiv powr. Thus th powr rating of th shunt activ powr filtr can b rducd in th hybrid configuration compard with pur activ filtr configuration. Th ffctivnss of th adoptd topology and control schm has bn vrifid by simulation and xprimntal rsults undr various sourc/load conditions. Kywords Hybrid filtr, Powr quality, Harmonic compnsation. I. INTRODUCTION A larg numbr of solid stat powr convrtrs such as diod bridg rctifirs and thyristor convrtrs ar usd in industrial applications and transmission/distribution ntworks. All ths brds of powr convrtrs ar nonlinar in natur and caus srious problms of currnt harmonics, poor powr factor, non sinusoidal supply voltag, ractiv powr burdn and low systm fficincy. Hnc, du to ths srious issus thr has bn an incrasing intrst in th subjct of powr quality improvmnt tchniqus which can supprss supply harmonics, improv powr factor and balanc th input supply [1]. Many circuit configurations of filtrs hav bn suggstd to limit harmonic currnt distortion. Passiv filtrs which act as last impdanc path to th tund harmonic frquncis wr usd initially to rduc harmonics. This tchniqu is simpl and lss xpnsiv. But it has many drawbacks such as rsonanc, fixd compnsation charactristics, bulky siz, high no load losss tc. As a bttr option of complt compnsation of distortions, activ powr filtrs [2, 3] hav bn rsarchd and dvlopd. Activ filtrs ovrcom drawbacks of passiv filtr by using th switchd mod powr convrtr to prform complt harmonic currnt limination. Shunt activ powr filtrs ar dvlopd to supprss th harmonic currnts and ractiv powr compnsation simultanously by suitabl control tchniqus to gnrat a compnsating currnt in qual and opposit dirction so that sourc currnt bcoms harmonic fr[2,4]. Th papr first rcivd 2 Dc 29 and in rvisd form 23 Dc 21. Digital Rf: A Dpartmnt of ECE, Nhru Collg of Enginring and Rsarch cntr, Thrissur, Krala, India, -mail:sindhu_2478@yahoo.com 2,3 Dpartmnt of EEE, School of Enginring, Amrita Vishwa Vidyaptham Univrsity, India, -mail:mr_sindhu@cb.amrita.du, gn_manjula@blr.amrita.du. 4 Dpartmnt of EEE, Adi Shankara Institut of Enginring and Tchnology, Kochi, Krala, India, -mail: ginnskjohn@gmail.com Howvr, th powr rating and construction cost of activ powr filtrs in a practical industry is too high. To avoid this limitation, hybrid filtr topologis hav bn dvlopd. Using low cost passiv filtrs with th activ filtr, th powr rating of activ convrtr is rducd compard with that of pur activ filtrs. This hybrid filtr rtains th advantags of activ filtrs and passiv filtrs. Also hybrid filtrs ar cost ffctiv and bcom mor practical in industry applications [5-9]. In this papr, th hybrid filtr structur consistd of an activ filtr and a passiv filtr, connctd in shunt is usd for powr quality improvmnt. Th ffctivnss of th hybrid filtr configuration was vrifid with simulation and xprimntal rsults. Th rsults prov that th proposd mthod can ffctivly liminat harmonic currnts, balanc sourc currnts, compnsat ractiv powr i.. in othr words; powr quality improvmnt of th powr systm is achivd by th proposd hybrid filtr structur and control mthod. II. STRUCTURE OF HYBRID FILTER CONFIGURATION Th hybrid filtr structur consists of shunt passiv filtr and shunt activ filtr. Shunt passiv filtr is a sris combination of a capacitor and a ractor tund to a spcific harmonic frquncy. It provids low impdanc trap to harmonic to which th filtr is tund, usually to lowr ordr harmonics bcaus th major contribution of harmonics is du to lowr ordr harmonics. Rmaining highr ordr harmonics only ar to b filtrd by shunt activ filtr; hnc its powr rating can b rducd. A thr phas voltag sourc invrtr (VSI) is usd as th shunt activ filtr. Th hybrid filtr is connctd in paralll with th nonlinar load. Th diagram of hybrid filtr structur is shown in th fig.1. Fig.1. Th shunt hybrid filtr structur 7

14 Sindhu S. t.al: Implmntation of Thr Phas.. Th nonlinar loads considrd in this study ar thr phas diod bridg rctifir and thr phas thyristor convrtr. A proportional intgral voltag controllr is usd to maintain th constant dc link voltag of th invrtr. A hystrisis currnt comparator is usd to track th output currnt to gnrat propr PWM pulss to th invrtr. a 15kW AC-DC Diod bridg rctifir fding a variabl inductiv load. Th MATLAB modl of th systm is shown in Fig.2. III. CONTROL STRATEGY OF SHUNT ACTIVE FILTER Various control algorithms wr dvlopd in litratur such as instantanous ractiv powr thory, synchronous dtction, dc bus voltag algorithm tc [2]. Th instantanous ractiv powr thory and synchronous dtction algorithm oprats satisfactorily undr balancd conditions only. In this work, ICOSΦ algorithm is usd which is tstd satisfactorily undr distortd and transint conditions[4,1,11].th shunt activ filtr uss ICOSφ algorithm, In ICOSφ algorithm, mains rquird to supply only th ral componnt of th load currnt, rmaining parts of load currnt ractiv componnt and harmonics is to b supplid by th activ filtr [4]. Th xtraction of ral componnt of load currnt can b don as follows: Th load currnt contains fundamntal componnt and harmonic componnts. Th lowr ordr tund frquncy componnts ar filtrd by th passiv filtrs. Rmaining harmonic componnts ar filtrd with activ filtr. Ths harmonics ar snsd with th hlp of low pass (biquad) filtr. Its output is fundamntal componnt dlayd by 9 (i.. i m sin (ωt -φ -9 )). At th tim of ngativ zro crossing of th input voltag, i..,ωt = 18, instantanous valu of fundamntal componnt of load currnt is i m cosφ.th magnitud of th dsird sourc currnt Is( rf ) can b xprssd as th magnitud of ral componnt of th fundamntal load currnt in th rspctiv phass. i.. for phas a it can b writtn as Is( rf ) = R( ILa). Th dsird (rfrnc) sourc currnts in th thr phass ar givn as, isa( rf ) = Is( rf ) Ua = Is( rf ).sinω t i I U I t sb( rf ) = s( rf ) b = s( rf ).sin( ω 12 ) isc( rf ) = Is( rf ) Uc = Is( rf ).sin( ω t+ 12 ) (1) Th compnsation currnts to b injctd by th shunt activ filtr ar th diffrnc btwn th actual load currnts and th dsird sourc currnts. iacomp ( ) = ila isarf ( ); ibcomp ( ) = ilb isbrf ( ); iccomp ( ) = ilc iscrf ( ) ; (2) Fig.2: Th thr-phas systm with diod bridg rctifir A. Without filtr: Th prformanc of diod bridg rctifir fding an inductiv load was studid without any filtr in th systm. Th systm was simulatd undr balancd sourc and balancd load conditions. Th sourc currnt is highly distortd. B. With passiv filtr: Th 5th and 7th ordr of shunt passiv filtrs ar dsignd to sink in rspctiv harmonic currnts. Th capacitors for th passiv filtr ar slctd to supply th spcifid prcntag of th ractiv powr rquirmnt of th load. Th MATLAB modl of th systm with passiv filtrs is shown in Fig.3. Tabl 1: Paramtr valus of passiv filtr Harmonic Rsistor Inductor Capacitor 5 th.314ω 1mH 4µF 7 th.16ω 5.1mH 4µF Tabl 1 givs th paramtr valus of passiv filtr componnts for compnsation. Fig.3: Simulation modl of th thr-phas systm with Passiv filtr IV. SIMULATION RESULTS As cas studis, thr phas diod bridg rctifir and thr phas thyristor convrtr ar considrd as harmonic loads. Cas I: Diod bridg Rctifir Load A thr-phas 4 V, 5 Hz balancd supply is givn to Th passiv filtr hlps to rduc th major amount of distortions in sourc currnt. i.., th passiv filtr sinks th 5th and 7th harmonic currnts by providing a low impdanc path. C. With Activ Filtr In th nxt stag, th simulation is rpatd with th shunt activ filtr in th systm. Th circuit for ICOSφ [4] 8

15 Asian Powr Elctronics Journal, Vol. 5 No. 1, Aug 211 algorithm was simulatd in MATLAB/SIMULINK and installd in th systm. Th MATLAB modl of th systm with activ filtrs is shown in Fig.4. Fig.6: Simulation modl of th thr-phas systm with Hybrid filtr. Fig.4: Simulation modl of th thr-phas systm with I COSφ controllr basd shunt activ filtr Simulation rsults with addition of activ filtr ar shown in Fig.5.Th harmonics in sourc currnt is highly rducd and THD is within standard limits. Th sourc voltag and sourc currnt ar in phas and sinusoidal, and implis prfct ractiv compnsation. Crtainly, it taks tim dlay mor than 1 cycl for prfct compnsation. Fig.7: Sourc voltag, load currnt and sourc currnt of thr-phas systm with hybrid filtr- for diod bridg rctifir load Th simulation rsults for diod bridg rctifir load ar summarizd in Tabl 2. Th comparativ study shows that hybrid filtr much ffctivly rducs harmonic distortion in th sourc currnt with ffctiv ractiv powr compnsation. Th prformanc of th shunt hybrid filtr was vrifid xprimntally with diod bridg rctifir. Tabl 2: Prformanc of various filtr configurations with diod bridg rctifir Fig.5: Sourc voltag and sourc currnt of thr-phas systm with shunt activ powr filtr for th diod bridg rctifir load. C. With Hybrid Filtr Hybrid systm uss a shunt passiv filtr to rmov th lowr ordr harmonics and a shunt activ filtr to rmov th rmaining harmonics and ractiv powr compnsation. Th shunt activ filr uss th ICOSφ control algorithm. Th fig.6 is th simulation modl of th thr phas systm with hybrid filtr. Th total harmonic distortion with hybrid filtr is rducd to.47% and sourc currnt bcoms in phas with sourc voltag. Fig.7 shows wavforms of sourc voltag, load currnt, sourc currnt wavforms of diod bridg rctifir load with hybrid filtr. Paramtrs Fundamntal sourc currnt in rms (A) THD in Sourc Currnt (%) Without filtr With Passiv filtr With Activ filtr With Hybrid filtr

16 Sindhu S. t.al: Implmntation of Thr Phas.. V. ANALOG CIRCUIT IMPLEMENTATION OF HYBRID FILTER A laboratory modl of th shunt hybrid filtr - ICOSφ controllr basd shunt activ filtr and shunt passiv filtr - was st up for tsting with th nonlinar load, thr phas diod bridg rctifir. Fig.8 shows th hardwar st up for th xprimnt. A voltag sourc invrtr assmbly, which consists of a thr phas IGBT basd invrtr along with larg DC link capacitor, is usd as th shunt activ filtr. DC link capacitor of 165mF / 8V is usd to maintain stady voltag rquird by th invrtr. ralizd using op-amp 741 and IC 449B. Th isolation btwn powr circuit and controllr circuit is don using an optocouplr 6N136. Th output pulss ar amplifid using transistor amplifir BC 547[4]. Basd on ractiv powr rquirmnt of th systm undr th ratd load condition, passiv LC filtrs ar dsignd and insrtd. Th componnts of passiv filtrs inductor and capacitor ar dsignd for 6 th harmonic frquncy, such that major amount of 5 th and 7 th harmonics can b liminatd with a singl tund passiv filtr. VI. EXPERIMENTAL STUDY Th xprimntal rsults on a scald down balancd thr phas systm connctd to diod bridg rctifir fding a rsistiv load (23V, 3kW) ar prsntd in this sction. Fig.8. Hardwar stup Th oprations in th analog circuit can b xplaind as follows: Stp 1: Th sourc voltags, load currnts and activ filtr injction currnts ar snsd with hall ffct voltag and currnt snsors. Stp 2: Dtction of fundamntal componnt of load currnt: Low pass filtring by using biquad filtr is don to xtract fundamntal componnt of load currnt. Th advantags of using biquad filtr, rathr than othr low pass filtrs, ar it is asy to dsign, givs unity gain and xact 9 phas shift. Stp 3: Dtrmination of ral componnt of load currnt: Th circuit with th comparator and monostabl multivibrator 74LS123 is usd for gtting sharp output pulss at th ngativ zro crossing of th phas voltag. Ths pulss and output of th biquad filtr ar fd to a sampl and hold circuit to obtain instantanous valu of fundamntal componnt of load currnt at ngativ zro crossing of sourc voltag, i.., ral part of load currnt. Stp 4: Obtaining dsird sourc currnt wavforms: Th ral componnt of load currnt is multiplid with unit sinusoidal wavs to obtain dsird sourc currnt wavforms, using AD 633 JN multiplir. Stp 5: Driv PWM pulss to invrtr: Th rfrnc compnsation currnt is obtaind by subtracting rfrnc sourc currnt from load currnt. A comparator is usd to compar rfrnc compnsation currnt and actual filtr currnt. Whn rfrnc filtr currnt is mor than actual filtr currnt, output of th comparator is high and vic vrsa. Th comparator is Th passiv filtr is dsignd for 1% Var compnsation and it is tund to th sixth harmonic so as to avoid rsonanc condition and to sink both 5 th and 7 th harmonic currnts to crtain xtnt. This will rduc th siz of th passiv filtr and hnc th loading on th sourc also. In this cas study, combination of passiv filtr lmnts usd is 5mH-8μF. Th ICOSφ controllr snss load currnt, supply voltag and gnrat PWM pulss to IGBT invrtr. Th shunt activ powr filtr is connctd to thr phas supply at point of common coupling through 1mH, coupling ractanc. Th systm was opratd undr various sourc/load conditions and th rsults ar shown in th following sction. Th tst rsults ar analyzd using FLUKE mak powr quality analyzr. A: Balancd Sourc Balancd Load Th hybrid powr filtr, combination of shunt activ and shunt passiv filtrs, rducs total harmonic distortion in sourc currnt. Passiv filtr rducs th lowr ordr (5 th and 7 th ) harmonics and th shunt activ powr filtr injcts th rmaining harmonics in sourc currnt.rlvant rsults ar shown in Fig.9 and Fig.1. Fig.9: a-phas sourc voltag and sourc currnt a) without hybrid filtring b) with hybrid filtring Fig 1: a) Harmonic spctrum of sourc currnt a) without hybrid filtring b) with hybrid filtring 1

17 Asian Powr Elctronics Journal, Vol. 5 No. 1, Aug 211 B:Distortd sourc and Balancd Load Th distortd sourc voltags ar applid across th diod bridg rctifir fding rsistiv load. Whn thr is distortion in th supply voltags, th fundamntal componnts ar first drivd using suitably tund scond ordr low pass filtrs to mak th voltags balancd and sinusoidal. Th unit sin wav of ths balancd voltags ar usd as tmplats as rquird by th ICOSφ algorithm to gnrat compnsation currnts. Th xprimntal rsults ar shown in Fig 11 and Fig 12. Th xprimntal rsults ar summarizd in Tabl 3. Tabl 3 compars th prformanc of th tst systm with and without hybrid filtring. It can b sn that harmonics in th sourc currnt is highly rducd with th addition of th hybrid filtr. Also it is calculatd that siz of th activ filtr can b rducd up to 3% in this hybrid configuration. Tabl 3: Prformanc of various filtr configurations with diod bridg rctifir THD in sourc currnt (%) Without hybrid filtr With hybrid filtr R Y B R Y B Fig.11: a-phas sourc voltag and sourc currnt a) without hybrid filtring b) with hybrid filtring Fig 12: Harmonic spctrum of sourc currnt (a) without hybrid filtring (b) with hybrid filtr Balancd Sourc And Load Distortd Sourc And Balancd Load Balancd Sourc Unbalancd Load C. Balancd sourc Unbalancd Load Th unbalanc in thr phas currnts ar introducd by a star connctd unbalancd rsistiv load in shunt with diod bridg rctifir. Th shunt activ filtr using th ICOSφ algorithm maks sur that th sourc currnts in all th sam phass rmain balancd vn in cas of load unbalanc. Th activ filtr along with th passiv filtr rducs th THD in sourc currnts and th xprimntal rsults ar shown in Fig 13 and Fig 14. Fig.13: a-phas sourc voltag and sourc currnt (a) without filtring b) with hybrid filtring VII. CONCLUSION With th dvlopmnt of mor sophisticatd powr lctronic nonlinar dvics, mor and mor powr quality issus wr initiatd. As rmdis to ths problms, many filtring tchniqus such as passiv filtr, activ filtr, hybrid filtr tc. ar dvlopd. Th simulation rsults show th shunt hybrid filtr is much suprior in prformanc compard to othr configurations. Th thrphas hybrid filtr is implmntd in hardwar as combination of shunt passiv filtr and shunt activ filtr. Th thr-phas hybrid filtring systm works quit fficintly undr various sourc/load conditions such as balancd supply and balancd load, distortd sourc and balancd load,balancd supply and unbalancd load tc. ACKNOWLEDGMENT Th authors would lik to thank for th financial support from Dpartmnt of Scinc and Tchnology, Nw Dlhi, India and Amrita Vishwa VidyaPtham Univrsity, Coimbator, India, for th compltion of this work. REFERENCES Fig 14: Harmonic spctrum of sourc currnt (a) without hybrid filtring (b) with hybrid filtring [1] IEEE Guid for harmonic control and ractiv compnsation of Static Powr Convrtrs, IEEE Standard [2] Bhim Singh, Kamal Al-Haddad and Ambrish Chandra, A Rviw of Activ Filtrs for Powr Quality Improvmnt,IEEE Trans. on Industrial Elctronics, Vol. 46, No. 5, Octobr1999. [3] M.Izhar, C.M.Hadzr, M.Syafrudin, S.Taib, S.Idris, Prformanc 11

18 Sindhu S. t.al: Implmntation of Thr Phas.. for passiv and activ powr filtr in rducing harmonics in th distribution systm ", Proc. National Powr and Enrgy Confrnc, PECon 24, Nov24, pp [4] Manjula G.Nair and G. Bhuvanswari, Dsign, Simulation and Analog Circuit Implmntation of a Thr-phas Shunt ActivFiltr using th ICOS Ǿ Algorithm IEEE PEDS 25. [5] Bor-Rn Lin.t.al. "Analysis and opration of hybrid activ filtr for harmonic limination", Elctric Powr SystmsRsarch 22, Vol.62, pp [6] F.Z.Png, H.Akagi and A. Nava, "Compnsation Charactristics of th Combind Systm of Shunt Passiv and Sris Activ Filtrs", IEEE-T Ind. Applications, vol. IA-29, no.1, Fb 1993, pp [7] H.-L.Jou, J.-C.Wu, K.-D.Wu, "Paralll opration of passiv powr filtr and hybrid powr filtr for harrmonic supprssion IEE Proc. Gnration, transmission & Distribution, Vol 148(1) 148(1), Jan 21, pp [8] E.-H.Song, "A Nw Low Cost Hybrid Activ Powr Filtr using Variabl Capacitor Banks", Proc. Europan Powr and Enrgy S y s t m s C o n f r n c, 2 2. [9] D.Slla, R.Pnzo, tal."hybrid activ filtr for paralll harmonic compnsation", Th Europan Powr Elctronics Association Journal 1993.pp [1] Manjula G.Nair and G. Bhuvanswari, Dsign, Simulation and Analog Circuit Implmntation of a Thr-phas Shunt Activ Filtr using th ICOSǾ Algorithm IEEE Transactions on Powr Dlivry, Vol.23, Issu2, April 28, pp [11] Manjula G. Nair and G. Bhuvanswari, A novl shunt activ filtr algorithm simulation and analog circuit basd implmntation, Spcial issu on Powr Quality, Intrnational journal of Enrgy Tchnology and Policy (IJETP), 26, Vol. 4, 1/2, pp BIOGRAPHIES Sindhu.S was born in Ottapalam in Krala stat, India on Novmbr 24, Sh did M.Tch.(Elctronics and Communication Enginring) from Karunya Institut of Tchnology, Coimbator and M.Tch.(Powr Elctronics) from Amrita Vishwa Vidyaptham Univrsity, Coimbator.Sh is taching for two yars and prsntly, is Lcturr, Nhru Collg of Enginring and Rsarch cntr, Thrissur. Hr aras of intrst ar Powr lctronics, Powr quality, and Digital lctronics. M.R.Sindhu was born in Thrissur in Krala stat, India on May 6, Sh did B.Tch. (Elctrical and Elctronics Enginring) and M.Tch. (Powr Systms) from Calicut Univrsity and currntly doing Ph.D. in Amrita School of Enginring.Sh is taching for ight yars and prsntly, is Assistant Profssor, Amrita School of Enginring, Ettimadai, Amrita Vishwa Vidyaptham Univrsity. Hr aras of intrst ar Powr quality, Gntic Algorithm Application in Powr systms. Dr. Manjula G.Nair obtaind hr Mastrs dgr in Powr systms from Univrsity of Calicut, Krala and Ph.D. dgr from IIT- Dlhi. Sinc 1995, sh has bn with th Dpartmnt of Elctrical Enginring, Amrita School of Enginring, Amrita Vishwa Vidyaptham (Univrsity), India. Hr aras of intrst ar FACTS controllrs, Fuzzy and ANN basd control of Powr Systms, Powr Quality, Hybrid and Activ Filtrs. Ginns K John did his B.Tch. in lctrical and lctronics nginring from Mar Athanasius collg of nginring, Kothamangalam, Mahatma Gandhi univrsity, Kottayam, Krala, India and M.Tch in powr lctronics from Amrita School of Enginring, Amrita Vishwa Vidyaptham Univrsity, Ettimadai, Tamil Nadu, India. H is prsntly working as lcturr at Adi Shankara Institut of Enginring and Tchnology, Kochi, Krala. His aras of intrst ar powr quality, powr lctronics, lctrical drivs and control. 12

19 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 PI with Fuzzy Logic Controllr basd Activ Powr Lin Conditionrs Karuppanan P. 1 Kamala Kanta Mahapatra 2 Abstract This papr prsnts a proportional intgrator (PI) in conjunction with Fuzzy Logic controllr (FLC) basd Shunt activ powr lin conditionrs (APLC) for powr quality improvmnts. Th objctiv is to invstigat diffrnt control mthodologis for ral tim compnsation of currnt harmonics and ractiv powr du to non-linar loads at various powr conditions. Th compnsation procss includs controlling dc-bus capacitor voltag of th invrtr and stimating pak rfrnc currnt by using PI with fuzzy logic controllr. Th rfrnc currnts ar xtractd from unit sin vctor multiplid with stimatd pak rfrnc currnt. Th voltag sourc invrtr switching signals ar obtaind through hystrsis currnt controllr (HCC). Th prformanc of shunt APLC is valuatd through Matlab/Simulink simulation undr diffrnt stady stat and transint conditions using PI, FLC and PI in conjunction with FLC. Th rsults dmonstrat that combination of PI with FLC is a bttr solution that rducs th sttling tim of th dc-bus capacitor and supprsss currnt harmonics in th loads. Kywords Shunt Activ Powr Lin Conditionrs (APLC), PI controllr, Fuzzy Logic Controllr (FLC), Harmonics, Hystrsis Currnt Controllr (HCC). I. INTRODUCTION Th ac powr supply fds diffrnt kind of linar and non-linar loads. Th non-linar loads produc harmonics and ractiv powr rlatd problms [1]. This harmonics and ractiv powr caus poor powr factor and distort th supply voltag at th point of common coupling (PCC). This distortion is mainly inducd du to th lin impdanc or distribution transformr lakag inductanc. Th currnt harmonics crat problms in powr systms such as malfunctions in snsitiv quipmnt, ovrvoltag by rsonanc and harmonic voltag drop across th ntwork impdanc; that rsult in poor powr factor [2]. Traditionally ths problms ar solvd by passiv filtrs. But ths passiv filtrs introduc tuning problms, rsonanc, and ar larg in siz and it s also limitd to fw harmonics [3-4]. Rcntly activ powr-lin conditionrs (APLC) ar dvlopd to compnsat th currnt harmonics and ractiv powr simultanously in addition to powr factor corrction [5]. APLC kps th mains currnt balancd aftr compnsation rgardlss of ithr th load is non-linar and/or unbalancd [6]. Th shunt APLC can b dvlopd with currnt sourc invrtr or voltag sourc invrtr. Gnrally th voltag sourc invrtr (VSI) is prfrrd for th shunt activ powr circuit du to lowr losss in th dc-sid capacitor [7]. Th controllr is th most important part of th APLC and currntly lot of rsarch is bing conductd in this ara [8-1]. Convntional PI and proportional intgral drivativ (PID) controllrs hav bn usd to stimat th pak rfrnc currnts and control th dc sid capacitor voltag of th invrtr. Most of th activ filtr systms us PIcontrollr for maintaining th dc sid capacitor voltag [5-11]. Whn th sourc supplis a non-linar or ractiv load, it is xpctd to supply only th activ fundamntal componnt of th load currnt and th compnsator supplis th harmonic/ractiv componnt. Th outr capacitor voltag loop will try to maintain th capacitor voltag narly constant which is also a mandatory condition for th succssful opration of th APLC. Th systm losss ar providd by th sourc in stady stat. Th compnsator supplis th harmonic powr, which manifsts itslf only on th ractiv componnt of powr. In th transint conditions th load changs ar rflctd in th dc capacitor voltag as an incras (or dcras) as capacitor absorbs (or dlivrs) th xcss (or dficit) powr. This consrvation of nrgy philosophy is usd to obtain th rfrnc currnt for compnsator in this mthod. Th prturbations in th capacitor voltag ar rlatd to th prturbations in th avrag powr drawn by th non-linar load. This proprty is utilizd which facilitats xtracting compnsator rfrnc and maintains capacitor voltag. Howvr, th convntional PI controllr rquirs prcis linar mathmatical modl of th systm, which is difficult to obtain undr paramtr variations and non-linar load disturbancs. Anothr drawback of th systm is that th proportional and intgral gains ar chosn huristically [12-13]. Rcntly, fuzzy logic controllrs (FLC) ar usd in powr lctronic systms and activ powr filtr applications [14-18]. In th prsnt work w combin PI and FLC tchniqus for fficint powr lin conditioning. This controllr can handl non-linarity and is mor robust. This rsarch papr prsnts a novl controllr that uss PI in conjunction with Fuzzy logic controllr for activ powr lin conditionr. Th proposd PI with fuzzy logic controllr is usd to stimat pak rfrnc currnt bsids maintaining th DC sid capacitor voltag of th invrtr narly constant. Hystrsis currnt controllr is usd to gnrat th switching signals for switchs in th invrtr. Th shunt APLC is invstigatd undr diffrnt stady stat and transint conditions using PI, FLC and PI in conjunction with FLC and is found to b ffctiv for compnsation; th proposd PI with FLC rducs rippls in th dc sid capacitor. Th papr first rcivd 25 th Jun 21 and in rvisd form 26 Aug 21. Digital Rf: A ,2 Dpartmnt of Elctronics and Communication Enginring, National Institut of Tchnology-Rourkla, India karuppanan1982@yahoo.co.in, kkm@nitrkl.ac.in II. DESIGN OF SHUNT APLC Th basic compnsation principl of shunt APLC is to draw/supply compnsating currnt, from/to th distributor systm such that it cancls currnt harmonics on th 13

20 Karuppanan P. Et.al: PI with Fuzzy Logic Controllr sourc sid and maks th sourc currnt sinusoidal and is in phas with th sourc voltag. Th activ powr filtr is implmntd with puls width modulatd (PWM) currnt controlld voltag sourc invrtr (VSI). Th thr phas APLC consists of six powr transistors with frwhling diods, a dc capacitor, RL filtr, compnsation controllr (PI or FLC or PI in conjunction with FLC) and gat signal gnrator (hystrsis currnt controllr) as shown in th Fig 1. Ths PI and Fuzzy logic controllr algorithm is usd to xtract th dsird rfrnc currnt from th load currnt. Th hystrsis currnt controllr is mployd to gnrat th switching signals for driving switchs in th VSI. Th inductiv-filtr supprsss th harmonics causd by th switching opration of th IGBT invrtr. This inductiv-filtr provids smoothing and isolation for high frquncy componnts. Th currnt wav shap is limitd by th switching frquncy of th voltag sourc invrtr. 3-phas supply Fig. 1 structur of Shunt APLC systm Th thr phas sourc is connctd to a diod rctifir (non-linar) load. This nonlinar load currnt contains fundamntal componnt and highr ordr of harmonic currnt componnts. For this systm, th instantanous load currnt can b writtn as follows i ( t) = L Voltag Snsor = I n n= 1 1 Rs,Ls Currnt Snsor isa,isb,isc Vsa,Vsb,Vsc 6 Hystrsis currnt controllr Unit Sin Vctor PCC I sin( nωt + Φ ) sin( ωt + Φ1) + n n n= 2 ica,icb,icc PWM-VSI isa*,isb*,isc* Rfrnc currnt gnrator I sin( nωt + Φ Non-sinusoidal Load ila, ilb, ilc C DC V DC,rf n ) Vdc Snsor PI or Fuzzy Logic Controllr or PI with Fuzzy Logic Controllr R L L L Th load powr compriss fundamntal powr and ractiv powr including harmonic powr. Th instantanous load powr can b writtn as (1) Hr p f (t) is th fundamntal componnt of powr, p r (t) is th ractiv powr and p h (t) rprsnts harmonic powr. From this quation only th ral (fundamntal) powr drawn by th load is 2 1 s s t p f ( t) = VmI sin ω t *cosφ1 = v ( t)* i ( ) Th sourc currnt drawn from th mains aftr compnsation should b sinusoidal; this is rprsntd as is ( t) = p f ( t) / vs( t) = I1 cosφ 1 sinωt = Imax sinωt If th activ powr lin conditionr provids th total ractiv and harmonic powr, sourc currnt i s (t) will b in phas with th utility voltag and would b sinusoidal. At this tim, th activ filtr must provid th compnsation currnt: i ( t) = i ( t) i ( t) c L s APLC stimats th fundamntal from th load currnt and compnsats for th harmonic and ractiv componnt. (3) (4) Dsign of DC sid capacitor: Th DC-sid capacitor voltag is maintaind constant with small rippls in stady stat. It acts as nrgy storag lmnt to supply ral powr (diffrnc btwn load and sourc) during th transint priod as alrady prsntd in th introduction. Th ral/ractiv powr injction rsults in th rippl voltag of DC capacitor. Th slction of C DC should b such that it facilitats rducing voltag rippl. Dsign of filtr inductanc L C and rfrnc voltag: Th dsign of th filtr inductanc (L C ) and rfrnc voltag (V DC,rf ) componnts is basd on th following assumption; (1) Th ac sourc voltag is sinusoidal (2) To dsign L C th ac-sid lin currnt distortion is assumd to b 5%. (3) Fixd capability of ractiv powr compnsation of th APLC. (4) Th PWM-invrtr is assumd to oprat in th linar modulation indx ( i.. m a 1). Th dsird rfrnc voltag is compard with actual dc-bus capacitor voltag for rducing th rippls in transint conditions. III. PROPOSED CONTROL STRATEGIES Th proposd control stratgy consists of xtracting rfrnc currnt and hystrsis currnt controllr for IGBT invrtr. Th rfrnc currnt is xtractd from th nonlinar load currnt. Th magnitud of th rfrnc currnt is stimatd by PI or FLC or PI with fuzzy logic controllr. (5) 14 p ( t) = i ( t)* v ( t) L = V s m 2 sin ωt *cosφ + V I + V sin t * m I ω n= 2 = p ( t) + p ( t) + p ( t) f s r 1 h m 1 n sinωt *cosωt *sinφ sin( nωt + Φ n ) 1 (2) A) Rfrnc currnt control stratgy: Th rfrnc currnt gnration is basd on stimatd pak rfrnc currnts that ar multiplid with unit sin vctor outputs. Th proposd PI with fuzzy logic controllr is usd to stimat th pak rfrnc currnt. A.1) Unit sin vctor: Th voltag sourc is convrtd to th unit currnt(s) whil

21 Asian Powr Elctronics Journal, Vol. 5 No.1 Aug 211 corrsponding phas angls ar maintaind. According th ohms law th currnt is invrsly proportional to th rsistanc ( i = V / R). Unit sin vctor is drivd from th supply voltag tmplat. ia = sinω t, ib = sin( ωt 12 ), ic = sin( ωt + 12 ) (6) Th amplitud of th sin currnt is unit or 1 volt and frquncy sam sourc voltag and it is also in th sam phas. This unit currnt multiplid with pak valu of control output gnrats rfrnc currnt. A.2) PI with Fuzzy controllr: Figur 2 shows th block diagram of th proposd proportional intgral (PI) control with fuzzy logic controllr schm for APLC. Th DC-sid capacitor voltag is snsd and is compard with a rfrnc voltag signal and gnrats rror signal. Th rror signal = V dc, rf Vdc at th to th PI-controllr. Vdc,rf Vdc th n sampling instant is usd as input Fig. 2 PI with fuzzy logic Controllr block diagram Th rror signal passs through Buttrworth low pass filtr (LPF) that supprsss highr frquncy componnts and allows only fundamntal componnts. PI-controllr stimats th magnitud of pak rfrnc currnt Imax and controls th dc-sid capacitor voltag of th invrtr. Its transfr function is H ( s) = K LPF Vsa Vsb Vsc ( s) P + PI Controllr K s I Unit sin vctor Fuzzy Logic Controllr I max X i sa* Vsa whr, [ K P =.7] is th proportional constant that dtrmins th dynamic rspons of th DC-sid voltag and [ K I =23] is th intgration constant that dtrmins it s sttling tim. Th PI controllr output contains crtain rippls, so w nd anothr procssing unit to rduc this rippl; th FLC is connctd togthr with PI controllr for rducing th rippls. Fuzzy logic controllr block diagram shown in Fig 3, th transition btwn mmbrship and non mmbrship functions can b gradual. Th PI controllr output rror is usd as inputs for FLC. Th linguistic variabls ar rror E (n), chang of rror CE(n) and output I max. X X i sb * i sc * (7) Fig. 3 fuzzy logic Control block diagram Fuzzification: In a control systm, rror btwn rfrnc and output can b labld as zro (ZE), positiv small (PS), ngativ small (NS), positiv mdium (PM), ngativ mdium (NM). Th procss involvs convrting a numrical variabl to a linguistic variabl; fiv-sts triangular mmbrship function ar dvlopd for th fuzzification as shown in Fig 4. Fig. 4 FLC mmbrship functions (a) th input variabls (n) (b) chang of rror c (n) and (c) output variabl dfuzzification Rul Elvator: Th basic fuzzy st oprations ndd for valuation of fuzzy ruls ar ( ) OR and NOT ( ) AND, ( ) AND -Intrsction: μ = min[ μ ( X ), μ ( x)] A B OR -Union: μ = max[ μ ( X ), μ ( x)] A B Rul Bas NOT -Complmnt: μa = 1 μ A ( x) Dfuzzification: Th ruls of FLC gnrat rquird output in a linguistic variabl format (Fuzzy Numbr), according to ral world rquirmnts, linguistic variabls hav to b transformd to crisp output (Ral numbr). Databas: Th Databas stors th dfinition of th mmbrship function rquird by fuzzifir and dfuzzifir Rul Bas: Th Rul bas stors th linguistic control ruls rquird A A I max (n) PI Rul Evaluator Output Fuzzification (Dcision Dfuzzification making) CE (n) 1.5 NM NS Data Bas ZE PS PM NM (a) Input Variabl E (n), Fuzzification NS ZE PS PM NM (b) Input Variabl CE (n), Fuzzification NS ZE PS PM (c) Output Variabl (Imax), DFuzzification B B 15

22 Karuppanan P. Et.al: PI with Fuzzy Logic Controllr by rul valuator, th 25-ruls usd in this papr ar prsntd in tabl 1. (n) c(n) Tabl 1 Rul bas tabl Th dsird rfrnc sourc currnts aftr compnsation should b sinusoidal and it can b givn as i i i sa sb sc * = I * = I * = I max max max sinωt sin( ωt 12 sin( ωt + 12 ) ) (8) (9) (1) whr Imax th amplitud of th dsird sourc currnt and th phas angl can b obtaind from th sourc voltags using unit sin vctor. Th rfrnc currnts i i *, i * ar compard with actual sourc currnts ( sa*, sb sc ) ( i i, i ) NM NS ZE PS PM NM NM NM NM NS ZE NS NM NM NS ZE PS ZE NM NS ZE PS PM PS NS ZE PS PM PM PM ZE PS PM PM PM sa, sb sc to gnrat switching signals for PWMinvrtr using hystrsis currnt controllr. B) Hystrsis Band Currnt Control: Thr ar various currnt control mthods proposd for APLC configurations; but in trms of fastr currnt controllability and asy implmntation, th hystrsis currnt control mthod scors ovr othr currnt control tchniqus. isa isa* isb isb* isc isc* (t) (t) (t) I out I out I out Switching Logic g1 g2 g3 g4 g5 g6 (+h), th uppr switch of th invrtr arm is bcom OFF and th lowr switch is bcom ON. As a rsult, th currnt starts to dcras. If th rror currnt (t) crosss th lowr limit of th hystrsis band (-h), th lowr switch of th invrtr arm is bcom OFF and th uppr switch is bcom ON. As a rsult, th currnt gts back into th hystrsis band and th cycl rpats. if iactual ( t) > irf ( t) + h S = (11) 1 if iactual ( t) < irf ( t) h Hr th hystrsis band limit usd is h=.5. Th rang of th rror signal (t) dirctly controls th amount of rippl voltag in th output currnt from th PWM-VSI. IV. SIMULATION RESULT AND ANALYSIS Th SIMULINK toolbox in th MATLAB is usd to modl and tst th systm undr stady stat and transint conditions using PI, Fuzzy logic and combination of PI and fuzzy logic controllrs. Th systm paramtr valus ar; sourc voltag (Vs) is 23 Vrms, Systm frquncy (f) is 5 Hz, Sourc impdanc R S, L S is 1 Ω;.2 mh rspctivly, Filtr impdanc R c, L c is 1 Ω; 2.5 mh, Load impdanc R L, L L of diod rctifir RL load in stady stat: 2 Ω; 2 mh and in transint: 1 Ω; 1 mh rspctivly, DC link capacitanc (C DC ) is 16μF, Rfrnc Voltag (V DC ) is 4V and Powr dvics ar IGBT with a frwhling diod in anti paralll. PI with Fuzzy controllr: PI with Fuzzy logic controllr basd APLC systm compriss a thr-phas sourc, a nonlinar load (six puls diod rctifir RL load) and a PWM voltag sourc invrtr with a dc capacitor on dc sid. Th simulation of th sourc currnt aftr compnsation is prsntd in Fig. 6 (a) that indicats that th currnt bcoms sinusoidal. Th load currnt is shown in 6 (b). Th actual rfrnc currnt for phas is shown in Fig. 6(c). This wav is obtaind from our proposd controllr. Th APLC supplis th compnsating currnt that is shown in Fig. 6(d). Th currnt aftr compnsation is as shown in (a) which would hav takn a shap as shown in (b) without APLC. It is clarly visibl that this wavform is sinusoidal with som high frquncy rippls. W hav additionally achivd powr factor corrction as shown in Fig. 6(), phas (a) voltag and currnt ar in phas. 6 isa,sourc currnt 4 Fig 5 Structur of hystrsis currnt controllr Hystrsis band currnt control dmonstrats charactristics lik robustnss, xcllnt dynamics and fastst control with minimum hardwar. For th PWMvoltag sourc invrtr; hystrsis currnt controllrs ar configurd indpndntly for ach phas. Each currnt controllr dirctly gnrats th switching signal of th thr (a, b, c ) phass shown in Fig 5. In th cas of positiv input currnt, if th rror currnt (t) btwn th dsird rfrnc currnt i rf (t) and th actual sourc currnt i actual (t) xcds th uppr hystrsis band limit a) b) ila, Load currnt

23 isa Vsa Asian Powr Elctronics Journal, Vol. 5 No.1 Aug isarf, Rfrnc currnt 45 4 Vdc,capacitor voltag c) c) d) ica, APF currnt Fig. 8 simulation rsults for 3-phas APLC undr stady stat condition; wavform of DC sid capacitor voltag controlld by (a) PI controllr (b) FLC controllr (c) PI with FLC controllr ) Fig. 6 PI with Fuzzy logic controllr basd simulation rsults for thr-phas activ-powr-filtr undr th stady stat condition (a) Sourc currnt aftr APLC, (b) Load currnts, (c)rfrnc currnts by th Fuzzy logic algorithm, (d) Compnsation currnt by APLC and () unity powr factor First w conductd simulation ( tim T= to T=.4s ) with rctifir load with RL at output with valus 2 ohms and 2 mh rspctivly and thn RL load is suddnly changd to 1 ohms and 1 mh for transint condition. Th transint simulation wavforms ar plottd in a similar mannr and ar shown in Fig 7. a) isa,sourc currnt Th dc-sid capacitor voltag sttling tim in transint and stady stat conditions using diffrnt controllr ar prsntd in tabl 2 Tabl 2 Vdc sttling tim using PI, FLC and PI with FLC controllr Condition PI controllr Fuzzy controllr PI with Fuzzy Controllr Stady stat.12s.11s.65s Transint.13s.12s.6s Th PI with fuzzy logic controllr basd APLC systm ffctivly supprsss th harmonics, compnsats ractiv powr and improvs powr factor. Ral powr in watts (W) and ractiv powr in volt-amprs (VAR) ar masurd undr stady stat and transint condition and ar prsntd in tabl 3 Tabl 3 Activ and Ractiv powr masurmnt using PI, FLC and PI with FLC controllr ila, Load currnt Load Condition Without APLC Powr masurmnt With APLC b) c) ica, APF currnt Fig. 7 PI with Fuzzy logic controllr basd simulation rsults for thr-phas activ-powr-filtr undr th transint condition (a) Sourc currnt aftr APLC, (b) Load currnts and (c) Compnsation currnt by APLC Th DC sid capacitor voltag is ffctivly controlld by th PI or FLC and/or combination of PI with FLC shown in Fig 8. It is obsrvd that sttling tim is quit fast. Th combination of PI with FLC taks last sttling tim and has small rippls compard to individual PI and FLC controllrs. Stady stat Transint P=3.97 kw Q=219 VAR P=4.847 kw Q=268 VAR PI Fuzzy PI with Fuzzy PI Fuzzy PI with Fuzzy P=4.39 kw Q=81 VAR P=4.33 kw Q=72 VAR P=4.57 kw Q=75 VAR P=4.97 kw Q=41 VAR P=4.98 kw Q=4 VAR P=5.17 kw Q=36 VAR Th Fourir analysis of th sourc currnt is don to find magnituds of diffrnt harmonic componnts and is shown in Fig 9. a) Magnitud basd on "Bas Pak" - Paramtr Vdc, capacitor voltag Ordr of Harmonic a) b) Vdc, capacitor voltag Magnitud basd on "Bas Pak" - Paramtr b) Ordr of Harmonic Fig. 9 PI with FLC-controllr basd harmonics masurd with rspct to th magnitud undr th stady stat condition (a) Sourc currnt without APLC, (b) sourc currnts with activ powr lin conditionrs 17

24 Karuppanan P. Et.al: PI with Fuzzy Logic Controllr Th total harmonic distortion (THD) is computd. PI with FLC basd shunt APLC indicats that THD of th sourc currnt is lss than 5% aftr compnsation that is in complianc with IEEE-519 standards harmonic, shown in tabl 4 Tabl 4 THD masurmnt using PI, FLC and PI with FLC controllr Load Condition Without APLC THD masurmnt With APLC PI controllr Fuzzy controllr PI with Fuzzy logic Controllr Stady 26.28% 3.1% 2.87% 2.52% stat Transint 26.37% 3.18% 2.79% 2.32% V. CONCLUSION Proportional-Intgral in conjunction with fuzzy logic controllr basd Shunt APLC prforms quit wll and it compnsats both harmonic currnts and ractiv powr. Simulation rsults dmonstrat that sourc currnt aftr compnsation is sinusoidal and is in phas with sourc voltag. PI with FLC facilitats rduction of rippls in dcsid capacitor of th invrtr. Th PI, FLC and PI with FLC-controllrs ar invstigatd undr both stady stat and transint conditions and it is obsrvd that PI with FLC-controllrs provids suprior prformanc in trms of compnsation and sttling tim compard to othr mthods. Th PI with FLC basd APLC systm is in complianc with th IEEE-519 standards harmonics. [9] Muhammad H.Rashod Powr Elctronics-Handbook Acadmic Prss, an imprint of Elsvir-24. [1] Akira Naba, Satoshi Ogasawara, and Hirofumi Akagi A Novl Control Schm for Currnt-Controlld PWM Invrtrs - IEEE Transaction on Industry Appl,Vol 1A- 22,No.4,pp ,1986. [11] Abdlmadjid Chaoui, JanPaul Gaubrt, Fath Krim, Grard Champnois PI Controlld Thr-phas Shunt Activ Powr Filtr for Powr Quality Improvmnt - Elctric Powr Componnts and Systms, 35: , 27. [12] S. Saad, L. Zllouma Fuzzy logic controllr for thr-lvl shunt activ filtr compnsating harmonics and ractiv powr Elctric Powr Systms Rsarch, Elsvir, pp May-29. [13] S.K. Jain, P. Agrawal and H.O. Gupta Fuzzy logic controlld shunt activ powr filtr for powr quality improvmnt -IEE proc.lctr.powr.appl,vol.149,no.5,pp , Spt-22. [14] V. S. C. Raviraj and P. C. Sn Comparativ Study of Proportional Intgral, Sliding Mod, and Fuzzy Logic Controllrs for Powr Convrtrs IEEE Tran Industry Vol 33, No. 2, pp , March/Appl [15] Karuppanan P and KamalaKanta Mahapatra Fuzzy Logic Controlld Activ Powr Lin Conditionrs for Powr quality Improvmnts Intrnational Confrnc on Advancs in Enrgy Convrsion Tchnologis, pp , Jan- 21. [16] Marclo Godoy Simos, Bimal K. Bos, and Ronald J. Spigl Dsign and Prformanc Evaluation of a Fuzzy- Logic-Basd Variabl-Spd Wind Gnration Systm IEEE Trans on Industry Applications, Vol.33, No.4, pp , July/Aug [17] C. N. Bhnd, S. Mishra and S. K. Jain TS-Fuzzy- Controlld Activ Powr Filtr for Load Compnsation IEEE Trans on Powr Dlivry, Vol.21, No.3, pp , July-26. [18] G.K. Singh, A.K. Singh, R. Mitra A simpl fuzzy logic basd robust activ powr filtr for harmonics minimization undr random load variation scinc dirct-elctric Powr Systms Rsarch 77 pag no , 27. REFERENCES [1] W. K. Chang, W. M. Grady, Austin, M. J. Samotyj, Mting IEEE-519 Harmonic Voltag and Voltag Distortion Constraints with an Activ Powr Lin Conditionr. IEEE Trans on Powr Dlivry, Vol. 9, No.3, pp , July [2] E. H. Watanab, R. M. Stphan, M. Ards, Nw Concpts of Instantanous Activ and Ractiv Powrs in Elctrical Systms with Gnric Loads - IEEE Trans. Powr Dlivry, Vol.8, No.2, pp April [3] Bhim Singh, Kamal Al-Haddad & Ambrish Chandra, A Rviw of Activ Filtr for Powr Quality Improvmnts IEEE Trans on Indus.Elctronics, Vol.46, No.5, pp 96-97,Oct [4] Hirofumi Akagi, Edson hirokazu watanab and Mauricio Ards, Instantanius powr thory and applications to powr conditioning. IEEE-prss 27; chaptr 3-4. [5] W.M.Grady, M.J.Samotyj. A.H.Noyola, Survy of Activ Powr Lin Conditioning Mthodologis. IEEE Trans on Powr Dlivry, Vol.5, No.3, pp [6] Hldr J. Azvdo, Jos M. Frrira, Antonio P. Martins, Adriano S. Carvalho, An Activ Powr Filtr with Dirct Currnt Control for Powr Quality Conditioning Elctric Powr Componnts and Systms, Taylor & Francis, pp , 36:6, pp , 28. [7] Murat Kal and Engin O zdmir, Harmonic and ractiv powr compnsation with shunt activ powr filtr undr non-idal mains voltag Elctric Powr Systms Rsarch- Elsvir, 74 (25) pp , March 25. [8] Brod D.M, Novotny D.M, Currnt control of VSI-PWM Invrtr -IEEE Trans on Industry Appl, Vol.21, pp July/Aug BIOGRAPHIES P.Karuppanan rcivd B.E in Elctronics & Communication Engg from Madurai Kamraj Univrsity-India and M.E in VLSI Dsign from Anna Univrsity-India in 24 and 27 rspctivly. H has bn with National Institut of Tchnology-Rourkla, India as a Rsarch Scholar in th Dpt of Elctronics & communication Enginring sinc 28. His rsarch intrsts ar powr lctronics applications in powr quality, Analog and Digital VLSI dsign. Kamalakanta Mahapatra rcivd B.Tch dgr with Honours in 1985 from Univrsity of Calicut, Mastr s in 1989 from Sambalpur Univrsity and Ph.D from Indian Institut of Tchnology, Kanpur in th yar 2; all in Elctrical Enginring.Currntly, h is a Profssor in th Elctronics and Communication Enginring Dpartmnt of National Institut of Tchnology Rourkla; h assumd this position sinc Fbruary 24. H is a Fllow of th Institution of Enginrs (India), His rsarch intrst includs Powr Elctronics, Embddd Systms, FPGA basd Systm dsign and VLSI Dsign. 18

25 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 Dynamic Prformanc Analysis of Slf-commutating PWM CSI-fd Induction Motor Driv undr MATLAB Environmnt S. M. Tripathi 1 A. K. Pandy 2 Abstract In this papr, an attmpt has bn mad to invstigat analytically th dynamic prformanc of slfcommutating currnt sourc invrtr-fd induction motor driv with volts/hz control stratgy. Spd and currnt PI rgulators ar usd in ralization of closd loop control structur of th driv systm. Th closd loop mathmatical modling of th complt driv systm is prsntd in th synchronously rotating d -q rfrnc fram. Th dynamic prformanc curvs of th driv ar obtaind through MATLAB simulation and ar discussd in dtail. Kywords Currnt sourc invrtr, induction motor driv, puls width modulation (PWM), dynamic prformanc, V/f control. NOMENCLATURE d, q Dirct and quadratur axs v as, v bs, v cs v ds i ds Phas voltags of th PWM invrtr d-axis stator voltag in synchronously rotating rfrnc fram d-axis stator currnt in synchronous rotating rfrnc fram q-axis stator voltag in synchronously rotating v qs rfrnc fram i qs i dr i qr i as, i bs, i cs I DC I act q-axis stator currnt in synchronously rotating rfrnc fram d-axis rotor currnt in synchronously rotating rfrnc fram q-axis rotor currnt in synchronously rotating rfrnc fram Lin currnts of PWM invrtr DC link currnt Activ componnt of stator currnt * I act Rfrnc activ componnt of stator currnt I ract Ractiv componnt of stator currnt * I ract ω Rfrnc ractiv componnt of stator currnt Switching frquncy of th invrtr ω r Rotor spd of th induction motor ω rf Rfrnc spd ω sl Slip spd of th induction motor ω * sl I rf V inv V r R f L f Rfrnc slip spd Rfrnc DC link currnt Input voltag of th invrtr Rctifir output voltag Rsistanc of DC link inductor Inductanc of DC link inductor Th papr first rcivd 3 rd Jan 211 and in rvisd form 2 th May 211. Digital Rf: A Dpartmnt of Elctrical Enginring, Kamla Nhru Institut of Tchnology, Sultanpur (U.P.), India, mani_xcl@yahoo.co.in 2 Dpartmnt of Elctrical Enginring, M. M. M. Enginring Collg, Gorakhpur (U.P.), India, akp1234@gmail.com R s Rsistanc of stator winding pr phas L s Slf-inductanc of stator winding pr phas R r Rsistanc of rotor winding pr phas L r Slf inductanc of rotor winding pr phas L m Mutual inductanc pr phas 2 L 1 L s L r - L m C Capacitanc pr phas J Momnt of inrtia in kg-m2 B Viscous friction cofficint β Puls width of PWM rctifir V LL Lin-to-lin input voltag of th rctifir P Numbr of pols I c Instantanous phas currnt of capacitor V s Instantanous stator phas voltag d-axis capacitor currnt in synchronously rotating i dc rfrnc fram q-axis capacitor currnt in synchronously rotating i qc rfrnc fram k p i Proportional gain of currnt rgulator k i i Intgral gain of currnt rgulator k Proportional gain of spd rgulator ps k i s p k Intgral gain of spd rgulator Diffrntial oprator (d/dt) or complx frquncy Maximum valu of fundamntal invrtr lin currnt DC link currnt k 1 Slop of stator activ currnt (I act ) vs. slip spd (ω sl ) k 2 Slop of stator ractiv currnt vs. slip spd (ω sl ) Ratd valu of capacitor currnt pr phas k 11 [ Ratd angular frquncy (ω )] 2 I. INTRODUCTION Th spd control of induction motors is possibl ovr a wid rang by fding th motor through variabl frquncy VSI or CSI. Du to th controlld currnt opration of th invrtr, slip-rgulatd CSI is prfrrd ovr VSI. Th currnt sourc at th front nd maks th systm naturally capabl of powr rgnration [1] [4]. In this papr, th closd loop schm of slf-commutating currnt sourc invrtr-fd induction motor driv mploying two PI rgulators is prsntd. Th slction of paramtrs for currnt and spd PI rgulators of a slfcommutating CSI-fd induction motor driv ar mad on th basis of systm rlativ stability, frquncy scanning, and transint rspons of th driv, as thoroughly discussd in [5]. II. SYSTEM DESCRIPTION Th CSI-fd induction motor driv consists of a thrphas AC sourc, a PWM rctifir, a DC link smoothning ractor, a currnt-controlld invrtr, a thr-phas squirrl cag induction motor, and a thr-phas capacitor bank, as shown in Figur 1. A fast-rspons spd- 19

26 S. M. Tripathi t.al: Dynamic Prformanc Analysis rgulating driv can b ralizd by incorporating PI rgulators in th fdback loops [6] [9]. Two PI rgulators ar usd on in th spd fdback loop and th othr in th currnt fdback loop. Th outr spd rgulator compars th rfrnc spd and th actual rotor spd and procsss th spd rror to obtain th rfrnc slip * spd ( ω sl ) which is rquird to stimat th rfrnc * stator activ currnt ( I act ) and rfrnc stator ractiv * currnt ( I ract ) of th induction motor and hnc, rfrnc DC link currnt ( I rf ). It is also usd in th calculation of switching frquncy ( ω ) of th invrtr. Th following mathmatical quations ar usd: k * i s ωsl = k p + ( ωrf ωr ) s p (1) * * I k ω + constant (2) act = 1 sl * * I k ω + constant (3) ract = 2 sl ω = ω + ω (4) r * sl Th currnt PI rgulator is usd to rgulat th rror btwn th rfrnc DC link currnt and actual DC link currnt. Th output of currnt PI rgulator dcids th puls widths of th PWM rctifir pulss and hnc, controls th output voltag of th puls width modulatd rctifir, which in turn controls th DC link currnt. Th output voltag of th rctifir in trms of currnt rgulator paramtrs is givn by th following xprssion: ki i V ( ) r = k p + I rf I (5) i DC p Th rfrnc DC link currnt is dtrmind using th quation: ( ) ( ) * 2 * 2 2 I rf = I act + I ract I c. (6) ' k For th V / f control opration of th driv I c may b xprssd as 2 I = ω (7) c k 11 I c ( ratd ) 11 = ( ω ( ratd ) whr, k 2 ) III. MATHEMATICAL MODEL OF THE DRIVE Th modling of th PWM CSI-fd induction motor driv is carrid out in synchronously rotating rfrnc fram for th following: A. Thr-phas PWM rctifir B. Thr-phas PWM invrtr C. DC link D. Thr-phas induction motor with load E. Thr-phas capacitor bank A. Thr-phas PWM rctifir Th PWM rctifir output voltag dpnds on th numbr of pulss pr cycl and thir widths. Th convrtr is modld for twlv numbrs of qual pulss pr cycl. It lads to two pulss pr 6 ach of β width. Th avrag output voltag of th PWM rctifir can b xprssd as follows: 3 2 5π β V r = V 4sin sin (8) LL π 12 2 Sinc β is varid from 1% to 9% of (π/6) radians, hnc, (β/2) is vry small and it can b approximatd as follows: sin (β/2) (β/2). Thrfor, V = ( β / 2) (9) r V LL B. Thr-phas PWM invrtr Th fundamntal componnt of th lin currnts of th thr-phas puls width modulatd invrtr i as, i bs, and i cs forms a balancd st of thr-phas currnts with maximum valu as I as(max) and can b xprssd as follows: I as (max) = ki DC (1) whr, k is obtaind through Fourir analysis of invrtr lin currnt wavforms, and this is givn by th following: maximum valu of fundamntal invrtr lin currnt k = DC link currnt ( ) Th valu of k dpnds on th oprating frquncy of th invrtr and varis from.8485 to.997 for variation in oprating frquncis from 1 to 5 Hz. Sinc th invrtr output fundamntal currnt pak is takn along th q axis of th rfrnc fram, th transformd phas currnt quations in th d -q rfrnc fram ar as follows: I DC Fig. 1: Variabl spd slf-commutating PWM currnt sourc invrtr fd induction motor driv 2

27 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 i s = ; i qs = ki ; i = DC ds (11) Assuming powr loss in th invrtr to b ngligibl, i.., input powr = output powr, w can driv th following: 3 V invi inv = v asias + vbsibs + vcsics = ( v qs iqs + vds ids ) (12) 2 Substituting th valus of i qs, i ds, and I inv in trms of I DC, th following quation is obtaind: V inv = 1.5 k (13) v qs C. DC link Th rctifir output voltag V r is th sum of th invrtr input voltag Vinv and DC link voltag, hnc r qs ( R f pl f ) I DC V = 1. 5 k V + + (14) D. Thr-phas induction motor with load Th induction motor can b modld in th d -q rfrnc fram using th following assumptions: Th thr-phas stator windings of th motor ar balancd and sinusoidally distributd in spac. Th air gap flux is maintaind at ratd valu. Th motor lin currnts ar sinusoidal du to capacitor at th motor trminals. Th DC link currnt is rippl fr. Th invrtr switching transints ar ignord. Thr is no cor loss in th motor. Th motor can b dscribd by fourth-ordr matrix quation in d -q rfrnc fram as follows: v Rs + pls ωls plm ωl qs m iqs v -ωls Rs + pls -ω Lm pl ds m = ids (15) + pl m ωsl Lm Rr plr ωsl Lr iqr ωsl Lm plm -ωsl Lr Rr + plr idr Th lctromagntic torqu quation of th motor is xprssd as follows: 3 P T =.. Lm ( iqs idr iqr ids ) (16) 2 2 Th quation of motion of th driv is givn by th following: dω r T = Tl + J + Bω r (17) dt Th load torqu quation is xprssd as T l T L.( ω ω ) = (18) r bas E. Thr-phas capacitor bank Th capacitor currnt is rlatd to th stator voltag of th induction motor, as shown blow: dvs ic = C (19) dt Transforming (19) in th synchronously rotating rfrnc fram d -q, w hav th following: d ( idc cos ωt iqc sin ωt) = C ( vds cos ωt vqs sin ωt) (2) dt Diffrntiating (2) and comparing th trms on both sids, d-axis and q-axis currnts ar xprssd as follows: i = C (pv ω v ) (21) dc ds qc qs + i qs = C (pv ω v ) (22) ds IV. DYNAMIC PERFORMANCE ANALYSIS A thr-phas capacitor bank of 15 µf pr phas is prfrrd at th motor trminals for th nar sinusoidal currnt ovr a wid rang of oprating frquncy [6]. Th dynamic prformanc of th driv is invstigatd through MATLAB simulation by implmnting th dsignd valus of rgulator paramtrs and using th mathmatical modl of th driv along with analyzing th currnt and spd transint rsponss of th driv for th following cass: 1. Start-up 2. Dcras in load torqu 3. Incras in load torqu 4. Spd dclration 5. Spd acclration 6. Spd acclration and dcras in load torqu 7. Spd dclration and incras in load torqu 8. Spd dclration and dcras in load torqu 9. Spd acclration and incras in load torqu 1. Spd rvrsal Th currnt and spd rsponss of th driv mploying aforsaid transint conditions on by on ach aftr an intrval of 1 sconds ar shown in Figur 2. Howvr, th dynamic prformanc of th driv can b analyzd wll by considring th spd and currnt rsponss of th driv sparatly for ach transint condition as dpictd in Figurs 3-4. Fig. 2: Spd and currnt rsponss of th driv mploying diffrnt transint conditions ach aftr an intrval of 1 sconds. 21

28 S. M. Tripathi t.al: Dynamic Prformanc Analysis Fig. 3: Spd rsponss of th driv sparatly for ach transint cas. 22 Fig. 4: Currnt rsponss of th driv sparatly for ach transint cas.

29 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 Cas 1: Start-up Initially th motor is at stand still. A stp spd command of ratd valu ( rad/s) from standstill is furnishd. Spd PI rgulator sts th spd of th rotor at th rfrnc spd slctd without xcding th prmissibl ovr shoot limit of th spd in 3.24 sconds as dpictd in Figur 3 (cas-1). Th DC link currnt corrsponding to rotor spd ( rad/s) and load torqu (1.31 N-m) is ralizd 5.56 A as shown in Figur 4 (cas-1). Cas 2: Dcras in load torqu Th load torqu on th motor running at rad/s is rducd to 1. N-m immdiatly aftr 1 sconds and as a rsult th rotor spd tnds to incras but it again sttls to rad/s in 3.19 sconds as dpictd in Figur 3 (cas-2). Th stady-stat valu of th DC link currnt corrsponding to rotor spd ( rad/s) and load torqu (1. N-m) dcrass to 5.68 A as shown in Figur 4 (cas-2). Cas 3: Incras in load torqu Th load torqu on th motor running at rad/s is now incrasd to 1.31 N-m immdiatly aftr 2 sconds and as a rsult th rotor spd tnds to dcras but it again sttls to rad/s in 3.21 sconds as shown in Figur 3 (cas-3). It can b obsrvd from Figur 4 (cas-3) that th DC link currnt corrsponding to rotor spd ( rad/s) and load torqu (1.31 N-m) acquirs th sam stady-stat valu (5.56 A) as in th cas-1. Cas 4: Spd dclration Th rfrnc spd of th motor running at rad/s is changd to 2 rad/s immdiatly aftr 3 sconds and th motor in turn starts dclrating and sttls to 2 rad/s in 3.17 sc. as shown in Figur 3 (cas-4). Th stady-stat valu of th DC link currnt corrsponding to rotor spd (2 rad/s) and load torqu (1.31 N-m) dcrass to 2.87 A as dpictd in Figur 4 (cas-4). Cas 5: Spd acclration Th rfrnc spd of th motor running at 2 rad/s is changd to 25 rad/s immdiatly aftr 4 sconds and th motor in turn starts acclrating and sttls to 25 rad/s in 3.69 sconds as shown in Figur 3 (cas-5). Th stady-stat valu of th DC link currnt corrsponding to rotor spd (25 rad/s) and load torqu (1.31 N-m) incrass to 3.34 A as dpictd in Figur 4 (cas-5). Cas 6: Spd acclration and dcras in load torqu Th rfrnc spd of th motor running at 25 rad/s is changd to rad/s and th load torqu on th motor is dcrasd to 1. N-m togthr immdiatly aftr 5 sconds and as a rsult th rotor spd starts acclrating and it sttls to rad/s in 2.87 sconds as dpictd in Figur 3 (cas-6). It can b obsrvd from Figur 4 (cas-6) that th DC link currnt corrsponding to rotor spd ( rad/s) and load torqu (1. N-m) acquirs th sam stady-stat valu (5.68 A) as in th cas 2. Cas 7: Spd dclration and incras in load torqu Th rfrnc spd of th motor running at rad/s is changd to 25 rad/s and th load torqu on th motor is incrasd to 1.85 N-m togthr immdiatly aftr 6 sconds and as a rsult th rotor spd starts dclrating and it sttls to 25 rad/s in 3.65 sconds as dpictd in Figur 3 (cas-7). It can b obsrvd from Figur 4 (cas-7) that th stady-stat valu of th DC link currnt corrsponding to rotor spd (25 rad/s) and load torqu (1.85 N-m) dcrass to 4.23 A, though this valu is highr than th stady-stat valu of cas 5 on account of incrasd load torqu. Cas 8: Spd dclration and dcras in load torqu Th rfrnc spd of th motor running at 25 rad/s is changd to 2 rad/s and th load torqu on th motor is dcrasd to 1. N-m togthr immdiatly aftr 7 sconds and as a rsult th rotor spd starts dclrating with an arly swing and it sttls to 2 rad/s in 3.43 sconds as dpictd in Figur 3 (cas-8). It can b obsrvd from Figur 4 (cas-8) that th DC link currnt corrsponding to rotor spd (2 rad/s) and load torqu (1. N-m) dcrass to A, which is lowr than th stady-stat valu of cas 4 on account of dcrasd load torqu. Cas 9: Spd acclration and incras in load torqu Th rfrnc spd of th motor running at 2 rad/s is changd to rad/s and th load torqu on th motor is incrasd to 1.85 N-m togthr immdiatly aftr 8 sconds and as a rsult th rotor spd starts acclrating with a rlativly tiny arly swing and it sttls to rad/s in 3.2 sconds as dpictd in Figur 3 (cas-9). It can b obsrvd from Figur 4 (cas-9) that th DC link currnt corrsponding to rotor spd ( rad/s) and load torqu (1.85 N-m) incrass to 6.23 A, which is th highst among th stady-stat valus of th cass 1, 2, 3 and 6 on account of vry high load torqu. Cas 1: Spd rvrsal Figur 3 (cas-1) shows th rspons of th motor driv to th rvrsal of spd. Th motor is running stably at positiv st rfrnc spd of ratd valu ( rad/s) and immdiatly aftr 9 sconds th st spd is changd to rad/s. In rspons to this chang, th spd rgulator is actuatd and th driv systm control structur implmnts th braking at controlld frquncis followd by its rvrs motoring up to th st rfrnc spd in 3.84 sconds. It can b sn from Figur 4 (cas-1) that th DC link currnt corrsponding to rotor spd ( rad/s) and load torqu (1.85 N-m) attains th prvious stady-stat valu (6.23 A). As summarizd in Tabl-1, th DC link currnt and driv sttling tim corrsponding to diffrnt transint conditions statd aforsaid, it is found that th stady-stat valu of th DC link currnt is incrasd / dcrasd with incras / dcras in motor spd and / or in load torqu. Th spd PI rgulator maintains th spd to its st rfrnc valu for variation in th load torqu within th prscribd limit. Th spd sttling taks plac in th tim duration sconds. Th dynamic prformanc 23

30 S. M. Tripathi t.al: Dynamic Prformanc Analysis curvs and facts in Tabl-1 show th ffctivnss of spd and currnt PI rgulators. Cas Tabl-1: Summary of diffrnt cass Stp-chang in Rfrnc Spd (rad/s) Stp-chang in Load Torqu (N-m) DC Link Currnt (A) Driv Sttling Tim (s) From To From To V. CONCLUSIONS A closd-loop schm incorporating spd and currnt PI rgulators of th V/Hz controlld PWM slf-commutating CSI-fd induction motor driv has bn discussd. A mathmatical modl of th induction motor driv has bn dvlopd by considring diffrnt sctions of th modl to invstigat th dynamic prformanc of th driv systm. Th xploration of th dynamic rspons curvs obtaind through MATLAB simulation has confirmd that th control structur of th driv taks car of transints in a propr tim. It is also obsrvd that th lvl of th transint currnt nvr xcds th prmissibl valu. Thrfor, it is concludd that th motor control schm taks car of th ovr currnt of th invrtr dvics. Th proposd schm has confirmd that thr ar quick and instantanous changs in th DC link currnts in accordanc with any disturbancs in th rfrnc spd / load torqu thrby provids fast rspons of th driv systm. APPENDIX Nam plat ratings of induction motor 1 hp, thr-phas, 4 V, 5 Hz, 4-pol, 1425 rpm, star Induction motor paramtrs R s = 3.52 Ω R r = 2.78 Ω L s =.165 H L r =.165 H L m =.15 H J =.1289 kg-m 2 DC link paramtrs =.25 Ω, L f =.4 H R f REFERENCES [1] P. Agarwal and V. K. Vrma, Prformanc Evaluation of Currnt Sourc Invrtr-fd Induction Motor Driv, Journals of Institution of Enginrs, Vol.72, pp , Fbruary [2] P.N. Enjti, P.D. Ziogas and J.F. Lindsay, Programmd PWM Tchniqu to Eliminat Harmonics: A Critical Evaluation, IEEE Transactions on Industry Applications, Vol. 26, No. 2, pp , March/April 199. [3] S.R. Bows and R.I. Bullough, Optimal PWM Microprocssor Controlld Currnt Sourc Invrtr Drivs, IEEE Procdings, Vol. 135, Pt. B, No. 2, pp , March [4] Y. Xiao, B. Wu, S. Rizzo and R. Sotudn, A Novl Powr Factor Control Schm for High Powr GTO Currnt Sourc Convrtr, Confrnc Rcord IEEE-IAS, pp , [5] A.K. Pandy and S.M. Tripathi, Dtrmination of Rgulator Paramtrs and Transint Analysis of Modifid Slf-commutating CSI-fd IM Driv, Journal of Elctrical Enginring and Tchnology, Koran Institut of Elctrical Enginrs, Vol. 6, No. 1, pp , January 211. [6] A.K. Pandy, Pramod Agarwal and V.K. Vrma, Optimal Capacitor Slction for Modifid Slf-commutatd CSI-fd Induction Motor Driv, IEEE ISIE 26, Montral, Qubc, Canada, pp , July 9-12, 26. [7] P. Agarwal and V.K. Vrma, Paramtr Coordination of Microcomputr Controlld CSI-fd Induction Motor Driv, IE (I) Journal EL, Vol. 88, pp , Dcmbr 27. [8] Pramod Agarwal, V.K. Vrma and A.K. Pandy, Prformanc Evaluation of a Slf-commutating CSI-fd Induction Motor Driv for Diffrnt Oprating Conditions, IETE Journal of Rsarch, Vol. 54, Issu 4, pp , July/Aug. 28. [9] Pramod Agarwal, A.K. Pandy and V.K. Vrma, Prformanc Invstigation of Modifid Slf-commutatd CSI-fd Induction Motor Driv, Asian Powr Elctronics Journal, Vol. 3, No. 1, pp , Spt 29. BIOGRAPHIES Saurabh Mani Tripathi is prsntly working as Assistant Profssor of Elctrical Enginring at Kamla Nhru Institut of Tchnology, Sultanpur, (U.P.), India. H obtaind his B.Tch. dgr in Elctrical and Elctronics Enginring in 26 and did his M.Tch. in Powr Elctronics and Drivs in 29 from U.P. Tchnical Univrsity, Lucknow. H has publishd svral rsarch paprs and authord svral books on modrn control systm and basic systm analysis. His aras of intrst includ lctrical machins, control systms, powr lctronics, and lctric drivs. Ashok Kumar Pandy rcivd his Ph.D. dgr in Elctrical Enginring from Indian Institut of Tchnology, Roork in 23. H did his M.Tch. in Powr Elctronics, Elctrical Machins and Drivs from Indian Institut of Tchnology, Dlhi in Currntly, h is working as an Associat Profssor with th Dpartmnt of Elctrical Enginring at M.M.M. Enginring Collg, Gorakhpur, (U.P.), India. His aras of intrst includ powr lctronics, lctrical machins, and drivs. H is a fllow of Institution of Enginrs (IE), India and Institution of Elctronics and Tlcommunication Enginrs (IETE), India. 24

31 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 Voltag Sag Rstorr with Diod-Clampd Multilvl Bridg K. Ding 1, K. W. E. Chng 2, S. L. Ho 3, K. P. Wong 4, S. X. Wang 5 Abstract Voltag sag rstorr is dvlopd using a multi-lvl diod clampd invrtr with a numbr of sris-connctd bulk capacitor for diffrnt voltag lvl. Although th multilvl circuit has mor componnt count than th two-lvl circuit it is mor suitabl for high voltag applications. Th rstorr is bypassd undr normal oprating conditions and is connctd to th load dpnding upon voltag sag dtction. Th switchs of th invrtr ar controlld by PWM signals. In th papr th opration of th multilvl circuit is simulatd in SABER to study th oprating capability of th multilvl invrtr. A comparativ study btwn th traditional two-lvl circuit and th proposd multilvl circuit is providd to highlight th prformanc of th multilvl circuit. Th proposd topology is dsignd, tstd and confirmd by xprimntal rsults. Th proposd circuit can liminat th convntional problm of filtr and th dynamic prformanc is xcllnt. Ovrall prformanc of th circuit is satisfactory. (a) Indx Trms Voltag sag, Powr intrruption, Powr systm, Diod-Clampd, Multilvl I. INTRODUCTION Th rliability for th rcnt yars for th powr distribution has bn significantly improvd to prvnt th powr intrruption by powr lctronic convrtr systms [1, 2]. Bsids th lctromagntic intrfrnc and harmonics, th voltag sags ar also th most common powr disturbanc and powr quality problms [2-14]. Th voltag sags ar causd by faults on adjacnt lins or starting of motors. This is gtting mor important nowadays bcaus of th snsitivity of th high spd computr controlld quipmnt. Th non-zro impdanc of a powr grid causs voltag drop at th point whr th load is connctd. Usually, ths drops ar vry small such that th voltag rmains within normal rangs [15]. But undr havy load condition whr thr is a larg incras in currnt, or whn th impdanc of th systm is high, a significant voltag drop may occur. Such voltag variations ar not dsirabl for snsitiv loads[8, 16]. Voltag sags ar dfind as a dcras in root man squar (rms) voltag at th powr frquncy. Voltag sag is not a complt intrruption of powr but a momntary drop in th magnitud of th voltag. It is a tmporary drop blow 9 prcnt of th nominal voltag lvl. Most voltag sags do not go blow 5 prcnt of th nominal voltag, and thy normally last from 3 to 1 cycls or 5 to 17 millisconds[3]. Sags do not gnrally disturb incandscnt or fluorscnt lighting, motors, or hatrs. Th papr was publishd in Intrnational Confrnc Powr Elctronics Systms and Applications 29, and it is now invitd and rvisd for publication in APEJ. Digital Rf: A19711DVR 1,2,3,4,5 Dpartmnt of Elctrical Enginring, Hong Kong Polytchnic Univrsity, Hong Kong, China. kding@polyu.du.hk, chng@polyu.du.hk, slho@polyu.du.hk, kpwong@polyu.du.hk, wsx@int.polyu.du.hk (b) Fig. 1. Singl-phas voltag sag rstorr with multilvl diod-clampd bridg (a) Thr-lvl (b) Fiv-lvl circuit Howvr, som lctronic quipmnt lacks sufficint intrnal nrgy storag and, thrfor, cannot rid through sags in th supply voltag [15]. Powr convrsion solution has bn usd rcntly to mitigat sags. Thy ar for xampls dsigning invrtr drivs for procss quipmnt to b mor tolrant of voltag fluctuations or th installation of voltag corrction dvics. Survy has found that th installation of voltag sag rstorr is a bttr solution rathr than to dvlop a high prformanc front-nd convrtr for ach snsitiv quipmnt. Th dvic is also calld a dynamic voltag rstorr (DVR) [17]. DVR is on of th custom powr dvics capabl of protcting snsitiv loads from all supply-sid disturbancs. Numrous circuit topologis and mthods ar availabl for DVR[2, 5, 6, 8-11, 13, 17-36]. DVR is diffrnt from unintrruptabl powr supply bcaus UPS ahs to handld th full powr for th snsitiv quipmnt, whras DVR is only to handl th rducd powr from th nominal valu. Thrfor it is mor cost ffct and usually is highr dynamic prformanc. It also only nds to oprat 25

32 K. Ding t.al: Voltag Sag Rstorr with.. whn ndd rathr than lik th UPS which is ndd to onlin all th tims. Th main limitation of som of th solutions is th us of 5 Hz intrfacing transformr. As a rsult th powr lctronics circuits ar limitd in application by prsnc of low frquncy transformr, which must b abl to handl full ratd powr[37]. In ordr to addrss this issu, dynamic voltag sag corrctors(dysc) without an intrfacing transformr ar proposd[32, 37, 38]. Th topology is drivd from a voltag boost circuit and is small in siz and wight. Th standard DySC products, up to 5-kVA moduls, do not includ a sris transformr, and includ littl nrgy storag. Th topology is also diffrnt from th singl invrtr with transformr that is usd proprly in wind powr gnration [39] For high voltag application, th switchs with high voltag rating hav to b usd in such circuits. In this papr, a singl-phas voltag sag rstorr with multilvl diod-clampd bridg is proposd by which th circuit can b usd at high voltag but with switchs of low voltag rating. Subharmonic PWM modulation mthod usd for multilvl convrtrs is mployd for controlling th powr switchs in th circuit. Simulation rsults ar providd to validat th fasibility of th proposd concpt. Th diod-clampd multilvl bridg invrtr circuit is discussd in II, opration of th voltag sag rstorr is prsntd in III, and simulation rsults ar givn in IV followd by xprimntal rsults and conclusions. II.DIODE-CLAMPED MULTILEVEL BRIDGE rangs from to n-1. E is th minimum voltag lvl th multilvl convrtr can gnrat. Assuming th DC bus voltag of th convrtr is 2E, it can b asily found from Fig. 2, that whn T 11,T 12 ar on T 13,T 14 ar off or T 12,T 13 ar on T 11,T 11 and T 14 ar off or T 11,T 12 off T 13,T 14 on, th output voltag of V o is +E,, -E, rspctivly. So th S rangs from, 1, 2 and thr voltag lvls can b synthsizd. B. Subhamonic PWM mthod Subhamonic PWM is a convntional control mthod suitabl for multilvl convrtr. Th control principl of th SHPWM mthod is to compar svral triangular carrir signals with only on sinusoidal rfrnc signal pr phas. For xampl, in an n-lvl invrtr, n-1 triangular carrir signals of th sam frquncy f c and th sam pak-to pak amplitud A c, ar disposd such that th bands thy occupy ar contiguous. V tri+4 V tri+3 V tri+2 V tri+1 V tri 1 V sin A. Diod-Clampd multilvl convrtr Th schmatic of a singl phas Diod-clampd multilvl convrtr is shown in Fig. 2. In gnral, th output voltag of a givn multilvl convrtr can b calculatd from (1) as: n 1 V o = ( S ) E (1) 2 V tri 2 V tri 3 V tri 4 Fig. 3 Principl of Subhamonic PWM mthod. 2E E + G + E C 1 C 2 T 11 T 12 T 13 T 14 + Fig. 2 Diod-clamp multilvl bridg whr V is th output voltag of th multilvl convrtr, n is th numbr of th output lvls; S is th switching stat that V o Th zro rfrnc is placd in th middl of th carrir st. Th modulation wav is a sinusoid of frquncy f m and amplitud A m. At vry instant, ach carrir is compard with th modulation wavform gnrating th gating signal for th switchs in th rspctiv lvls. Comparison of th rspctiv triangular signals with th sin signal rsults in switching on of th dvics if th rfrnc signal is gratr than th triangular carrir assignd to that dvic lvl; othrwis, th dvic is turnd off. For xampl, in a nin-lvl invrtr shown in Fig. 4, ight triangular carrirs ar compard with a sinusoid modulation wavform as shown in Fig. 3. Whnvr V sin >V tri+4 th switching stat S is 8 rsulting in an output voltag of V ac qual to +4E, and whnvr V tri+4 >V sin >V tri+3, th switching stat S is 7 rsulting inv ac qual to +3E and so on. On th othr hand whn V sin <V tri-4, th switching stat S is and th output voltag V ac is -4E. Thus diffrnt switching combination can b slctd according to th switching stat S to gnrat diffrnt voltag lvls. Th pattrn gnration is simpl and can b asily to b implmntd. 26

33 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 III. VOLTAGE SAG RESTORER WITH MULTILEVEL DIODE-CLAMPED BRIDGE Th voltag sag rstorr proposd hr is similar to th convntional voltag sag rstorr but for th us of multilvl half-bridg diod-clampd invrtr. As shown in Fig. 1, th singl phas voltag sag rstorr is drivd from voltag doublr [2, 32, 33, 37, 38] and a half-bridg multilvl diod-clampd invrtr. Th invrtr is configurabl to work in voltag boost or bypass mod, and is capabl of providing 1% stp-up to th ac grid voltag. Undr normal working conditions, th anti-paralll SCRs ar closd, and a normal lin voltag is providd dirctly from th input lin. Whn any voltag sag is dtctd, th SCRs ar opnd and th multilvl invrtr bridg is controlld to rsurrct th voltag to th load. Fig. 4: Schmatic of th main circuit of th proposd systm IV. SIMULATION VERIFICATION Th proposd DVR systm basd on thr-lvl diod-clampd invrtr bridg is simulatd using th mixd-mod circuit simulation SABER program for a 2kVA load to vrify th ffctivnss of th proposd tchniqu. A simulation modl of th systm shown in Fig. 1(a) is carrid out. Th schmatic of th modl is shown in Fig. 4 and th control circuit is shown in Fig.5. Th voltag sag dtction is implmntd in th RMS voltag dtction block as in Fig. 6. Th main paramtrs usd in th simulation ar givn as: C 1 = C 2 =47 F, L s =5mH C s =1 F and th switching frquncy f s is 1 khz. Fig. 7 illustrats th voltag rstoration prformancs of th thr lvls DVR systm during sourc-sid singl-phas voltag sag. For duration of voltag sag of.25s, and th voltag is dippd from 31V to 18V, th output voltag is abl to b maintaind at constant 3V pak. Thr is a littl transint of lss than 3% of voltag transint, but th ovrall prformanc is highly satisfactory. Masurd thr-lvl PWM output voltag and invrtr output ar shown in Fig. 8. Th masurd driving signals and DC-link capacitor voltag ar shown in Fig. 9 and Fig. 1 rspctivly. It can b sn that thr ar voltag dcras gradually du to th voltag sag, and it rturns to 31V at t=.5s. Each capacitor voltag in th multi-lvl will also xprinc such variation abnd th prospod convrtr can also compnsat for th voltag sag and provid constant output voltag. 27

34 K. Ding t.al: Voltag Sag Rstorr with.. Fig. 5: Schmatic of th control circuit of th proposd systm z 1 v rms [k] v[k] z N S[k] 1 N Fig 6: RMS voltag dtction block Fig. 7: Masurd sourc-sid singl-phas voltag and th output voltag across load (2kVA). Uppr: sourc-sid singl-phas voltag, vgrid; Lowr: output voltag, vout. 28

35 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 Fig. 8: Masurd thr-lvl PWM voltag and invrtr output voltag Uppr: invrtr thr-lvl PWM voltag; Lowr: invrtr output voltag Fig. 9: Masurd gat driving signals of switchs in diod-clampd invrtr bridg, PWM1~PWM4 Fig. 1: Masurd DC-link capacitor voltag Uppr: DC voltag across lowr capacitor; lowr: DC voltag across uppr capacitor 29

36 K. Ding t.al: Voltag Sag Rstorr with.. V. EXPERIMENTAL VALIDATION A multilvl diod-clampd invrtr basd DVR systm is dvlopd in th Lab. Th xprimntal rsult is givn in Fig. 11. Th input voltag drops to 5% of th nominal voltag with th sag duration of 5ms. Th output voltag is not affctd by th voltag sag during th sag duration as shown in CH 1. Fig.11: 1-Phas, 5%, 25cycl voltag Sag, 5Hz, CH1: Output Voltag, 4V/Div, CH2: Input Voltag, 4V/Div, CH3: Voltag Sag Signal, 1V/Div, Tim Bas: 1ms/Div VI. CONCLUSION A multilvl diod-clampd invrtr basd DVR systm is proposd in this work. Th circuit is drivd from th multi-lvl concpt for th invrtr and is applid to th voltag sag compnsation. In th circuit, th dc-bus voltag is split into svral lvls by sris-connctd bulk capacitors with nutral at th mid point. Th advantags of th proposd topology whn compard with two-lvl topology ar: 1) Voltag strss across IGBT is rducd by half; 2) it can rsult in highr voltag lvls; 3) Rsulting in smallr siz filtr du to rducd harmonic contnt; 4) Suitabl for high voltag application with lowr rating switchs such as for 1kV powr transmission lin. Th disadvantags of th proposd topology ar: 1) Highr componnt count; 2) Complicatd control and larg packag layout. Also, th proposd topology is dsignd, simulatd, tstd and is usd to vrify th proposd circuit. Both simulation and xprimntal rsults ar confirmd th succssful opration of th proposd circuit. REFERENCES [1] W. Bingsn and G. Vnkataramanan, "Dynamic Voltag Rstorr Utilizing a Matrix Convrtr and Flywhl Enrgy Storag", IEEE Transactions on Industry Applications, vol. 45, pp , 29. [2] K. W. E. Chng, S. L. Ho, K. P. Wong, T. K. Chung, and Y. L. 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37 Asian Powr Elctronics Journal, Vol.5 No.1, Aug 211 [23] M. J. Nwman, D. G. Holms, J. G. Nilsn, and F. Blaabjrg, "A dynamic voltag rstorr (DVR) with slctiv harmonic compnsation at mdium voltag lvl,", IEEE Transactions on Industry Applications, vol. 41, pp , 25. [24] E. K. K. Sng, S. S. Choi, and D. M. Vilathgamuwa, "Analysis of sris compnsation and DC-link voltag controls of a transformrlss slf-charging dynamic voltag rstorr,", IEEE Transactions on Powr Dlivry, vol. 19, pp , 24. [25] L. Poh Chiang, D. M. Vilathgamuwa, T. Sng Khai, and H. L. Long, "Multilvl dynamic voltag rstorr,", IEEE Powr Elctronics Lttrs, vol. 2, pp , 24. [26] J. G. Nilsn, M. Nwman, H. Nilsn, and F. Blaabjrg, "Control and tsting of a dynamic voltag rstorr (DVR) at mdium voltag lvl,", IEEE Transactions on Powr Elctronics, vol. 19, pp , 24. [27] A. Ghosh, A. K. Jindal, and A. Joshi, "Dsign of a capacitor-supportd dynamic voltag rstorr (DVR) for unbalancd and distortd loads,", IEEE Transactions on Powr Dlivry, vol. 19, pp , 24. [28] A. Florio, A. Mariscotti, and M. Mazzucchlli, "Voltag sag dtction basd on rctifid voltag procssing,", IEEE Transactions on Powr Dlivry, vol. 19, pp , 24. [29] D. M. Vilathgamuwa, A. A. D. R. Prra, and S. S. Choi, "Voltag sag compnsation with nrgy optimizd dynamic voltag rstorr,", IEEE Transactions on Powr Dlivry, vol. 18, pp , 23. [3] C. Po-Tai, H. Chian-Chung, P. Chun-Chiang, and S. Bhattacharya, "Dsign and implmntation of a sris voltag sag compnsator undr practical utility conditions,", IEEE Transactions on Industry Applications, vol. 39, pp , 23. [31] C. Li, T. Tayjasanant, W. Xu, and X. Liu, "Mthod for voltag-sag-sourc dtction by invstigating slop of th systm trajctory,", IEE Procdings- Gnration, Transmission and Distribution, vol. 15, pp , 23. [32] D. Divan, A. Bndr, W. Kranz, and R. Schnidr, "Dual sourc dynamic sag corrctors-a cost ffctiv topology for nhancing th rliability of dual sourc systms," prsntd at Industry Applications Confrnc, th IAS Annual Mting. [33] A. Bhadkamkar, A. Bndr, R. Schnidr, W. Kranz, and D. Divan, "Application of zig-zag transformrs in a thr-wir thr-phas dynamic sag corrctor systm," prsntd at IEEE 34th Annual Powr Elctronics Spcialist Confrnc, 23. [34] M. Vilathgamuwa, A. A. D. Ranjith Prra, and S. S. Choi, "Prformanc improvmnt of th dynamic voltag rstorr with closd-loop load voltag and currnt-mod control,", IEEE Transactions on Powr Elctronics, vol. 17, pp , 22. [35] V. K. Ramachandaramurthy, C. Fitzr, A. Arulampalam, C. Zhan, M. Barns, and N. Jnkins, "Control of a battry supportd dynamic voltag rstorr,", IEE Procdings- Gnration, Transmission and Distribution, vol. 149, pp , 22. [36] B. H. Li, S. S. Choi, and D. M. Vilathgamuwa, "Transformrlss dynamic voltag rstorr,", IEE Procdings- Gnration, Transmission and Distribution, vol. 149, pp , 22. [37] D. M. Divan, Dynamic Voltag Sag Corrction, U. S. Patnt , Sp. 2. [38] W. E. Brumsickl, R. S. Schnidr, G. A. Luckjiff, D. M. Divan, and M. F. McGranaghan, "Dynamic sag corrctors: cost-ffctiv industrial powr lin conditioning,", IEEE Transactions on Industry Applications, vol. 37, pp , 21. [39] Ramirz, D.; Martinz, S.; Platro, C.A.; Blazquz, F.; d Castro, R.M., " Low-Voltag Rid-Through Capability for Wind Gnrators Basd on Dynamic Voltag Rstorrs", IEEE Transactions on Enrgy Convrsion, Vol 26, Issu 1, 211, pp BIOGRAPHIES Kai Ding obtaind th B.E., M.E., and Ph.D. dgrs from Dpartmnt of Elctrical & Elctric Enginring, Huazhong Univrsity of Scinc and Tchnology, Wuhan, China, in 1998, 21, and 24, rspctivly. At prsnt, h is a Rsarch Fllow in Powr Elctric Rsarch Cntr of Dpartmnt of Elctrical Enginring, Hong Kong Polytchnic Univrsity. His rsarch intrsts includ multilvl convrtrs, ful cll tchniqu, lctrical vhicl, battry managmnt systm, dynamic voltag rstorr, powr lctronics applications in lctric powr systm and computr simulation. K.W.E.Chng (M 9-SM 6) obtaind his BSc and PhD dgrs both from th Univrsity of Bath in 1987 and 199 rspctivly. Bfor h joind th Hong Kong Polytchnic Univrsity in 1997, h was with Lucas Arospac, Unitd Kingdom as a Principal Enginr and ld a numbr of powr lctronics projcts H rcivd th IEE Sbastian Z D Frranti Prmium Award (1995), outstanding consultancy award (2), Faculty Mrit award for bst taching (23) from th Univrsity, Faculty Enginring Industrial and Enginring Srvics Grant Achivmnt Award (26) and Brussls Innova Enrgy Gold mdal with Mntion (27), Consumr Product Dsign Award (28), Elctric vhicl tam mrit award of th Faculty (29). H has publishd ovr 25 paprs and 7 books. H is now th profssor and dirctor of Powr Elctronics Rsarch Cntr of th univrsity. His rsarch intrsts ar all aspcts of powr lctronics, motor drivs, EMI, lctric vhicl and nrgy saving. S.L. Ho obtaind both his BSc (first class honours) and PhD dgrs in Elctrical Enginring from th Univrsity of Warwick. Whn h was rading for his PhD dgr h also workd as a part-tim projct nginr at th Glynwd Cntral Rsourcs Unit. H producd a numbr of patnts in patint support systms during his rsarch studis. Th product was also commrcialisd and licnsd world-wid by th tim h finishd his PhD studis. H thn joind th thn Hong Kong Polytchnic as Assistant Lcturr and is currntly th Had of th Dpartmnt and Chair Profssor in Elctricity Utilisation. Kit Po Wong was a graduat of Hong Kong Tchnical Collg in H obtaind MSc and PhD from UMIST in 1972 and 1974 rspctivly. In 21, h was awardd th highr doctorat dgr DEng also from UMIST. Profssor Wong is a Fllow of Hong Kong Institution of Enginrs, Fllow of Institut of Elctrical and Elctronic Enginrs USA, Fllow of Institution of Enginrs UK and Fllow of Institution of Enginrs Australia. Wang Shuxiao rcivd B.S dgr in automation control from Northwst Txtil Scinc and Tchnology Univrsity, China, in 1997, and th M.S. dgr from Xi an Polytchnic Univrsity in 23. H rcivd Ph.D dgr from th Hong Kong Polytchnic Univrsity in 28. His rsarch intrsts includ automation control, BMS, solar panl MPPT chargr, DVR and intllignt motor drivr. 31

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