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1 PSIM Tutorial Processor-In-the-Loop Simulation July
2 With PSIM s PIL Module, one can perform processor-in-the-loop (PIL) simulation with the power stage implemented and simulated in PSIM and the control code for the TI DSP running on the actual DSP hardware. This tutorial describes, in step by step, how to set up and perform the PIL simulation. The process involves the following steps: - Preparing the code for PIL simulation; and - Setting up in PSIM - Setting up the hardware To illustrate this process, we use a simple buck converter circuit as an example. This example is located in the sub-folder examples\pil\buck Converterr (F28335) in the PSIM directory. To keep the original example unchanged, we will copy the whole folder to c:\pil\buck Converter (F28335), and use it as the working folder in this tutorial. 1. Preparing the Code for PIL Simulation The schematic of the buck converter is shown below. 0.6m V Vo u 2.5 il 2 Verr V k2 K 1000 k1 K 0.4 z U1 1 z Vm V 10 V ILd_S Z1 ZOH The circuit is a buck converter with average current mode control, switching at 20 khz. The unit delay block U1 represents the one-cycle delay inherent in digital control. The first step in PIL simulation is to prepare the code. The code can be either written manually by users or automatically generated by PSIM using the SimCoder function. In this tutorial, we will use the code generated by PSIM
3 Creating Code The circuit above is modifiedd by adding an A/D converter after the current sensor, replacing the carrier wave and comparator with a PWM generator, and defining the hardware target. For further information on how to use SimCoder, please refer to tutorials Auto Code Generation for F2833x Target.pdf in the tutorials folder. Both the A/D converter and PWM generator are from PSIM s F2833x Target library, and they model the A/D converter and PWM generator functions of the actual F28335 DSP. The modified circuit is shown below, with the A/D converter and PWM generator highlighted in yellow. 0.6m V Vo u Verrr V k1 K 0.4 k2 K 1000 z il V ILd_S Vm V 1-ph PWM Z1 ZOH A B F28335 ADC A0 D0 A1 D1 A2 D2 A3 D3 A4 D4 A5 D5 A6 D6 A7 D7 B0 D8 B1 D9 B2 D10 B3 D11 B4 D12 B5 D13 B6 D14 B7 D15 F28335 PSIM can simulate this circuit and generate code automatically that is ready to run on the DSP hardware. To generate the code, in PSIM, go to Simulate >> Generate Code. A sub-folder buck converter (simcoder) (C code) will be generated that contains the C code and other necessary files for CodeComposerStudioo (CCS). Make a copy of this sub-folder, and rename it to buck converter (PIL) (C code) for the modified code for PIL simulation. Modifying Code for PIL Simulation After the code is available (either written manually or from SPIM), the next step is to identify variables that need to interface with PSIM. The codee will be represented in a PIL block. Signals from the rest of the PSIM circuit to this block will be inputs (such as measured voltages/currents), and signals from this block too PSIM will be outputs (such as PWM modulation waves). Typical input/output variables are: - Inputs: Variables after the A/D converter - Outputs: Variables before the PWM generator, and any other internal variables for display/debuggingg purposes - 3 -
4 For example, in this example, the input variable iss the A/D converter output, and the output variable is the modulation signal before the PWM generator. If we wish to monitor the internal signal Verr, Verrr will be an additional output variable. These variables are often in an interrupt service routine. Note that variables before, not after, the PWM generator are the output variables. The PWM generator outputs are the actual PWM gating signals that appear at the output ports, and they cannot be sent to PSIM. The PWM gatingg signals need to be generated in PSIM. Only two changes need to be made to the code: - All input/output interface variables need to be definedd as global variables. - The codes that assign values to ADC outputs need to be commented out. This is because there is no input at the actual ADC port, and the values must come from PSIM. Below is the original interrupt service routinee code before the change in the file buck_converter simcoder_.c in the sub-folder buck converter (simcoder) (C code) : fgblvm = 0; fgblild_s = 0; fgblverr = 0; interrupt void Task() { fsump1, fb4, fk2, fk1, fsum1, fz1, fti_adc1, fvdc2; PS_EnableIntr(); } fti_adc1 = PS_GetDcAdc(0 0); fvdc2 = 2; fz1 = fti_adc1; fsum1 = fvdc2 fz1; fk1 = fsum1 * 0.4; fk2 = fsum1 * 1000; { static e out_a = 0; fb4 = out_a + 1.0/ /20000 * (fk2); out A = fb4; } fsump1 = fk1 + fb4; PS_SetPwm1RateSH(fSUMP1); fgblvm = fsump1; fgblild_s = fz1; fgblverr = fsum1; PS_ExitPwm1General(); - 4 -
5 From the code, we can identify the ADC output ass fti_adc1, the PWM generator input as fsump1, and the error signal Verr as fsum1, all highlighted in yellow. Use a text editor to open the file buck_converter simcoder_.c in the sub-folder buck converter (simcoder) (C code), and make the changes as discussed above. Below is the code after the change: fti ADC1 = 0, fsum1 = 0, fsump1 = 0; fgblvm = 0; fgblild_s = 0; fgblverr = 0; interrupt void Task() { // fsump1, fb4, fk2, fk1, fsum1, fz1, fti_adc1, fvdc2; fb4, fk2, fk1, fz1, fvdc2; // } PS_EnableIntr(); fti_adc1 = PS_GetDcAdc(0 0); fvdc2 = 2; fz1 = fti_adc1; fsum1 = fvdc2 fz1; fk1 = fsum1 * 0.4; fk2 = fsum1 * 1000; { static e out_a = 0; fb4 = out_a + 1.0/ /20000 * (fk2); out A = fb4; } fsump1 = fk1 + fb4; PS_SetPwm1RateSH(fSUMP1); fgblvm = fsump1; fgblild_s = fz1; fgblverr = fsum1; PS_ExitPwm1General(); The modified lines are highlighted in yellow. The changes are: - The variables fti ADC1, fsum1, and fsump1 are defined as global variables, and their definitions within the interrupt function are removed. - The assignment of the ADC variable fti ADC1 is commented out. Now compile the project of the modifiedd code. In CCS, go to Project >> Import Legacy CCS v3.3 Project, and select buck_converter simcoder_.pjt in the sub-folder buck converter (PIL) (C code). Note that importing the legacy CCS v3.3 project needs to be done only once
6 Once it is converted to CCS v5.5, the project file cann be opened directly even if the source code is modified later. In CCS, go to Project >> Build All to build thee project. This will generate the hardware executable file buck_converter simcoder_.out in the folder buck converter (PIL) (C code) )/RamDebug. Now we can move on to the setup in PSIM. 2. Setting Up in PSIM To prepare the schematic for PIL simulation, modifyy the original circuit in Page 1 by removing the control circuit (except the PWM generator) and replacing it with a PIL block from the PSIM library under Elements >> Control >> PIL Module. The modified schematic file is shown as follows. 0.6m V Vo u 2.5 il V Vm V Verr PIL BLOCK 10 Notice that the unit delay block U1 is not present in this circuit. This is because the one-cycle delay is already included in the PIL block. The definition of the PIL block for this example is shown as below: - 6 -
7 The PIL block parameters are explained as below: Target Config Target Program No. of Inputs No. of Outputs Breakpoint Func. Frequency Delay Gain Data Type Target configuration file.ccxml used in CCS for the specific DSP hardware. The configurationn file must match the hardware connected to the computer for the PIL simulation. In this example, the TI Experimenter Kit is used, and the configuration file F28335.ccxml is provided in the schematic folder. Target hardware executable.out file. In this example, it is buck_converter simcoder_.out. Number of inputs to the PIL block. It is 1 for fti_adc1 in this example. Number of outputs from thee PIL block. It is 2 for fsump1 and fsum1 in this example. Names of the breakpoint functions where breakpoints need to be set for input variables. If there are more than one function, function names are separated by comma with noo space (for example, Task1,Task2 ). Sampling frequency for input variables. In this example, it is 20 khz for fti_adc1. Sampling delay from the beginning of the PWM cycle to the moment when the ADC sampling occurs. It ranges from 0 to 1, where 0 means theree is no delay, and 0.5 means that the sampling occurs at half of the PWM cycle. Note that for variables of the same sampling frequency, sampling delays must be thee same. In this example, it is 0. Gain of the input variables. In this example, it is 1. Type of the variable data. It can be: Default, Float, Integer, IQ1, IQ2, IQ30-7 -
8 When set to Default, the data type will be the same as the default data type in Simulation Controll >> SimCoder. In this example, it is Float. Data Size Size of the variable data. It can be: 1-bit, 8-bit, 16-bit, 32-bitt In this example, it is 32-bit. Variable Name of the input/output variable that interfaces with PSIM. In this example, three variables aree defined: fti_adc1, fsump1, fsum1. Function Function of the input/output t variable that interfaces with PSIM. In this example, all variables are inn one function Task. Note that at the moment, the operation of the PIL simulation with multiple sampling frequencies has not been validated yet. It is recommended that, when there are multiple sampling frequencies, sample all the input variables with the highest sampling frequency, and then down sample the selected variables after ADC. For example, if there are two inputs with one at 10 khz and the other at 1 khz, sample both of them at 10 khz, and then down sample the second input at 1 khz through a 1-kHz zero-order-hold. This completes the PSIM setup for the PIL simulation. 3. Setting Up the Hardware The only hardware setup needed for the PIL simulation is to connect the controller hardware to the computer. In this example, a TI Experimenter Kit is connected to the computer through the USB cable, as shown below. TI Experimenter Kit Once the controller hardware is connected, run simulation in PSIM. If the connection is properly established, you should see the following dialog: - 8 -
9 Do not close this dialog during simulation. You will be able to display waveforms during or at the end of simulation in the same way as you would in a regular PSIM simulation. PSIM s PIL simulation is very easy to use and set up. It providess a powerful tool to validate your controller code without the physical presence off the power stage, and allows you to perform various tests that would be difficult to do onn the actual hardware setup (for example, fault analysis)
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