DEVICE SPECIFICATION AP4800TH

Transcription

1 1 Description Features Applications Typical Application: Architecture: Block Diagram: Oscillator Enable : PFC Enable Pinning / Pad Coordinates: Absolute Maximum Ratings Detailed Block Description: Oscillator igh Frequency F0 : Oscillator Low Frequency F1 : Timer : FIL detection : EOL detection : V detection : I detection : Voltage reference IREF IREF Vclamp DRIVE output PFC output Electrical Characteristics: Marking: Package outlines...10

2 1 2 DEVICE SPECIFICATION 1 Description is an integrated circuit for driving electronically ballasted fluorescent lamps. It provides the drive function for the power MOSFETs bridge of the lamp converter and PFC input voltage booster. The IC also includes two oscillators, a timer, A PFC controller, a lamp voltage monitor and current control function and protections. 2 Features PFC controller Voltage control and overcurrent protection Lamp converter, current controlled operating Power-up/power-down function Slow start with embedded timer Protection against lamp removal/failure Package SOP 14 3 Applications Flour Lamp Ballast 4 Typical Application: L2 D5 CN1 1 2 F1 FUSE RV1 L3 C7 C25 4 GND AC D1 3 DC 1.8m T7 APQ04SN60A ES1J C3 22u/450V R20 330K CN_01_ u/275V 511K/320VAC UU u/275V AC KB206 C15 0.1u/400V R4 100R LL4148 D7 R1 100R R21 330K R22 330K R19 PAD1 C23 R29 18K 2.2n/1KV 1.2R C16 330p R24 22K R31 R30 R12 C5 22n/100V 27K 27K 27K D6 SM4937A(1A/600V) C1 R10 R16 R7 270K 3.9K T1 L1B 390R 2.2N/1.25KV APQ04SN60A 4Ts DIAC1 C17 R5 0.15uF/100V C9 10n D12 CN2 10R T3 LL4148 DB3 1 BC L1A C2 U R_1_2OSC VDD C4 3m/230TS C13 0.1u/ 450V 1n/1KV R6 3 47p/1KV 2 13 D15 470K COSC DRIVE LL4148 D10 C10 LL p/1KV 4 C IREF PFC 0.22u T2 R8 R9 R11 470K CN_01_04 47K 4 11 APQ04SN60A TIMER GND 3.9K D11 L1C 5 10 TIMOUT EOL 4Ts C18 R3 LL uF/100V C C6 NA FIL R2 33K 330p 150K 0.47u 7 8 C24 R18 I_sense V-sense C8 D13 R17 1.5K AP u R15 C12 68K 6.8n 100K 4.7u 15V AC 220V T5 28W 2 of 10

3 Architecture: 4.1 Block Diagram: SUPP C_OSC R_1_2 _OSC Iref1 IREF1 Iref1 VVREF Freq selection OSC 0 : Kz 1 : Kz CK SUPP DRIVE PFC TIMER Iref/12 Timer s Reset Timer 5.5*Iref Enable Osc INT_SUP TIMOUT IREF Iref IREF VVREF COMMON V reference VVREF ( from BGAP ) Time out BG_EN 1 INT_SUP EOL 4.714R R - + B VVREF Ref Voltage Generator (BGAP) FIL 4.714R R D R Q SUPP VDD VSENSE 4.714R R + - CK 1 D Q R INT_SUP ISENSE + - GND 3 of 10

4 4.2 Oscillator Enable : Supply FIL FIL comp.out EOL 7 7 TIME OUT Timer duration Timer duration EOL comp. out OSC ENABLE Freq 0 Freq 1 Freq 0 Freq 0 Freq PFC Enable. V sense CLOCK I sense PFC enable PFC pin 4 of 10

5 5 Pinning / Pad Coordinates: Pins placement may be changed during design to optimise device area.. Name Pin I/O Description R_1_2_OSC 1 I C_OSC 2 I IREF 3 I TIMER 4 I Reference current for Oscillator igh Frequency (F0). External resistor R R_1_2_OSC connected to ground. R R_1_2_OSC value must be evaluated according to Note 1. Setting of Oscillator igh Frequency (F0). External capacitor C C_OSC connected to ground. C C_OSC value must be chosen according to Note 1. Reference current for Timer and Oscillator igh and Low frequency (F0 and F1). External resistor R IREF connected to ground. R IREF value must be evaluated according to Note 1. Setting of Timer duration. External capacitor C TIMER connected to ground. C TIMER value must be chosen according to Note 1. TIMOUT 5 O Startup output timeout indicator 6 NC ISENSE 7 I Current detection VSENSE 8 I Voltage detection FIL 9 I Filament detection. EOL 10 I End Of Life detection GND 11 Power Ground supply. PFC 12 O PFC output driver DRIVE 13 O LS output driver VDD 14 Power Positive supply. Note 1. Evaluation and setting of external components should be done in the following order: 1. Select Oscillator igh Frequency (F0) and determine the value of C C_OSC according to the following rule: If F0 > 101kz then C C_OSC = 220 pf ; If F0 < 101kz then C C_OSC = 330 pf ; 2. Select Oscillator Low Frequency (F1) in kz and calculate R IREF and R R_1_2_OSC values according to the following equations: R IREF = 1.225*5.5 2 *1.47 * F1* C C _ OSC = F1* C C _ OSC R R_1_2_OSC = *1.47 *( F0 F1) * RC C _ OSC = ( F0 F1) * C C _ OSC 3. Select Timer duration (t TIMER ) and calculate C TIMER value according to the following equations: C TIMER = ttimer 12 * RIREF 5 of 10

6 6 Absolute Maximum Ratings Parameter Symbol Conditions Power supply voltage VDD 0V to Vclamp EOL, FIL, V Sense, DRIVE, Inputs and VIO 0V to Vclamp PFC, TIMOUT, VCC outputs C_OSC, R_1_2_OSC, voltages VIO1 0V to 7V Timer, I Ref, I Sense DC consumption IDD 10 ma Continuous power dissipation Pd 200 mw Normal operation ambient temperature Ta -40 to +85C Storage temperature range Tstor -40C to +125C Max Junction temperature Tj -55C to +150C Stressed above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified conditions may affect device reliability or cause malfunction. 6 of 10

7 7 Detailed Block Description: 7.1 Oscillator igh Frequency F0 : Based on reference currents (obtained from pin R_1_2_OSC and pin IREF) and capacitor on pin C_OSC. Designed to deliver frequency range kz according to external components values Inhibited during start-up period up to reaching oscillator start supply voltage () 7.2 Oscillator Low Frequency F1 : Based on reference current (obtained from pin IREF) and capacitor on pin C_OSC. Designed to deliver frequency range kz according to external components values Inhibited during start-up period up to reaching oscillator start supply voltage () 7.3 Timer : Based on reference current (obtained from pin IREF) and capacitor on pin TIMER Designed to deliver time range 0-1.5s according to external components values Inhibited during start-up period up to reaching oscillator start supply voltage () 7.4 FIL detection : Enables Oscillator and Timer when reaching FILin threshold level, indicating presence of lamp filament (7V). Enables DRIVE output. If voltage level on FIL input is below the threshold (see Item3, Electrical characteristics), then Oscillator and Timer are disabled, DRIVE and PFC output are 0V. Inhibited during start-up period up to reaching oscillator start supply voltage () 7.5 EOL detection : Disables Oscillator and Timer when reaching EOLin threshold level, indicating End-Of-Life (7V). Disables DRIVE and PFC outputs (0V) This function is inhibited during starting period up to the end of the timer duration (Time out) 7.6 V detection : Disables PFC driver (0V) when reaching Vin threshold level, indicating over-voltage (7V) Inhibited during start-up period up to reaching oscillator start supply voltage () 7.7 I detection : Use reference voltage VVREF as a threshold voltage Iin (1.225V) Disables PFC driver (0V) when reaching Iin threshold level Inhibited during start-up period up to reaching oscillator start supply voltage () 7.8 Voltage reference Delivers reference voltage VVREF = 1.225V for the threshold of input comparators Delivers reference voltage VVREF to the IREF blocks 7.9 IREF Delivers common reference current for Oscillator and Timer Reference current value is determined by VVREF and external resistor 7 of 10

8 7.10 IREF1 Delivers common reference current for Oscillator Value of the current is determined by VVREF and external resistor 7.11 Vclamp Protects the circuit against breakdown in case of excessive start-up current or in case of failure to start creating over-voltage on Vdd pin Separate voltage reference for clamping over the maximum normal supply voltage 7.12 DRIVE output Push-pull output driving low side power transistor of the output converter Insure fast on and off switching of the gate of the power transistor up to 1nF gate capacitance The DRIVE output state is low (0V) during the period of start up or OSC disable 7.13 PFC output Push-pull output driving low side power transistor of the output converter Insure fast on and off switching of the gate of the power transistor up to 1nF gate capacitance The PFC output state is low (0V) during the period of start up or OSC disable 8 Electrical Characteristics: All values are specified at nominal voltage VDD = 13 V; Tamb = 25 C; all voltages are referenced to GND; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Start-up state VDD(start) oscillator start supply voltage V IDD(start) oscillator start-up supply current ma VDD(stop) oscillator stop supply voltage V VDD(start)- hysteresis V VDD(stop) Vclamp-VDD(start) V Reference voltage VVREF reference voltage VDD=13V V reference voltage spread with temperature Tamb=25 C to 130 C 0.64 % PFC output driver Io(source) output source current VO=2V 200 ma Io(sink) output sink current VOL=Vdd-2V 300 ma VOL Iout = 10 ma V VO Iout = 10 ma Vdd- Vdd- V 0.4 V 0.15 V LS output driver Io(source) output source current VO=2V 200 ma Io(sink) output sink current VOL=Vdd-2V 300 ma VOL Iout = 10 ma V VO Iout = 10 ma Vdd- 0.4 V Vdd V V 8 of 10

9 Time-out output Time out output from timer 100μA load Open drain,vdd capability. EOL input EOLin Rising Edge Threshold voltage 5% precision 7 V ysteol ysteresis 100 mv Zin EOL Input impedance 100 K Ohm FIL input FILin Rising Edge Threshold voltage 5% precision 7 V ystfil ysteresis 100 mv Zin FIL Input impedance 100 K Ohm V input Vin Rising Edge Threshold voltage 5% precision 7 V ystv ysteresis 100 mv Zin V Input impedance 100 K Ohm I input Iin Rising Edge Threshold voltage 5% precision V ysti ysteresis 100 mv Zin I Input impedance Ohm Oscillator Freq 0 Oscillator Freq 1 Timer TIMER Stability within temperature range (notes 1, 2, 5) Stability within temperature range (notes 1, 3, 5) Stability within temperature range (notes 1, 4, 5) Tamb=-20 C to +80 C Tamb=-20 C to +80 C Tamb=-20 C to +80 C V 1.5 % 1.5 % 1.5 % Clamp voltage Vclamp Limiting voltage circuit on Vdd Power-down V Note 1 : only intrinsic stability, without external components precision. Note 2 : within frequency range khz Note 3 : within frequency range 30-70khz Note 4 : within timing range 0 1.5s Note 5 : Reference voltage VVREF ( tolerance ±3%) is generated from the BandGap block. 9 Marking: 9 of 10

10 10 Package outlines 亞德電子科技股份有限公司 alpha pacific Technologies Co., Ltd. 台灣省台北縣三重市 Tel 重新路 5 段 609 巷 18 號 Fax 樓之 6 Internet 10 of 10