AN-EVAL 2x8-ISO1I813T

Transcription

1 SOFAC TM valuation Board for galvanically isolated 8-Channel Digital nput Cs with C compatible characteristics for industrial applications SO1813T VAL - Board Application Note V 1.0, ndustrial & Multimarket

2 dition Published by nfineon Technologies AG Munich, Germany 2011 nfineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, nfineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. nformation For further information on technology, delivery terms and conditions and prices, please contact the nearest nfineon Technologies Office ( Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest nfineon Technologies Office. nfineon Technologies components may be used in life-support devices or systems only with the express written approval of nfineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. f they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

3 Table of Contents Table of Contents Table of Contents ntroduction Board Characteristics Functional Description Power Supply Oscillator Parallel nterface μc Control Mode Serial nterface Sensor nput Stage Wire Break Detection Filter Setting DC/DC Supply Connectors Schematic PCB Layout Bill of Material Transformer References Application Note 3 V 1.0,

4 Table of Contents Application Note 4 V 1.0,

5 ntroduction 1 ntroduction Application This Application Note describes an valuation Board with two isolated 8 Channel C compatible Digital nput Cs for a wide range of industrial applications. The board is designed to allow easy exploration of the features of the SOFAC TM Digital nput part. t contains two SO1813T as an electrically isolated 8 bit data input interface in TSSOP-48 package. These parts are used to detect the signal states of up to eight independent input lines according to C Type 1/2/3 (e.g. twowire proximity switches) with a common ground. An 8 bit parallel/serial µc compatible interface allows to connect the C directly to a µc system. The input interface supports also a direct control mode and is designed to operate with 3.3/5V CMOS compatible levels. The data transfer from input to output side across the galvanic isolation uses nfineon s Coreless Transformer Technology. V F VBB VCC 330n TS WB DC NA SW1 8 sensors N0 12k N7 12k 2k 2k 0H 0L 7H 7L S R A L Z D S R A L Z digital filter digital filter L O G C SW2 /RR SYNC /CS parallel or serial interface µc e.g. X166 Rosc GNDF GNDBB SO1813T GND Figure 1 Typical Application Application Note 5 V 1.0,

6 Board Characteristics SO1813T Figure 2 VAL 2x8-SO1813T 2 Board Characteristics Table 1 Board Characteristics Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition V BB nput Voltage V BB V VNx nput Voltage V Nx V V CC nput Voltage V CC V Logic Signals uc V L x V CC V nterface V H 0.7 x V CC V CC +0.3V V Oscillator Frequency khz set to 500kHz using R OSC 22k For a complete description of the characteristics of the SO1813T please consult respective Data Sheet available at: Note: this board is intended to be used in the lab to explore the functionality of the SO1813T device. t is not designed to be used in professional applications! Application Note 6 V 1.0,

7 Functional Description 3 Functional Description This board contains two SO1813T as an electrically isolated 8 bit data input interface in TSSOP-48 package. These parts are used to detect the signal states of up to eight independent input lines according to C Type 1/2/3 (e.g. two-wire proximity switches) with a common ground. For operation in accordance with C , it is necessary for the SO1813T to be wired with resistors rated R N and R LD. (it is recommended to use resistors with an accuracy of 2%, in any case < 5% - mandatory, temperature-coefficients < 200ppm are allowed) A parallel/serial µc compatible interface allows to connect the Board directly to a µc system. f the parallel interface is used, only C1 can be operated. n serial mode either C1 can be used with 8 Bit SP or C1 and C2 can be put into a Daisy Chain configuration with 16 Bit SP. The isolated data transfer from input to output side is realized by the integrated Coreless Transformer Technology. K1 VBB 470n VBB TS WB VCC Rosc K4 VCC N0 N7 12k 12k 2k 2k 0H 0L 7H 7L S R A L Z D S R A L Z digital filter digital filter L O G C /RR AL /WR /RD /CS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 K9 /RR AL /WR /RD /CS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GNDbb GNDBB SO1813T GND K11 K10 GND K12 K8 K2 VBB 470n VBB TS WB VCC Rosc N0 N7 N0 12k N7 12k 2k 2k 0H 0L 7H 7L S R A L Z D S R A L Z digital filter digital filter L O G C /RR /CS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GNDbb GNDbb GNDBB SO1813T GND Figure 3 Block Diagram Application Note 7 V 1.0,

8 Functional Description 3.1 Power Supply The C contains 2 electrically isolated voltage domains that are independent from each other. The microcontroller interface is supplied via pin VCC and the input stage is supplied via pin VBB. The different voltage domains can be switched on at different time. f the VCC and VBB voltage have reached their operating range and the internal data transmission have been started successfully, the C indicates the end of the Start-Up procedure by setting the pin /RR to logic high. 3.2 Oscillator The frequency of the internal oscillator can be set by the resistor R OSC. This internal oscillator provides the clock for the data sampling and transmission as well as for the digital averaging filter. For adjusting the frequency of the oscillator the values of R OSC can be taken out of the diagram in the SO1813T datasheet. 3.3 Parallel nterface The SO1813T contains a parallel interface that can be selected by pulling the pin SL to logic low state (see also Table 2). This interface can be directly controlled by the microcontroller output signals. Table 2 Mode Select Mode K13 K9 K10 K11 K12 K8 Parallel (C1) 2-3 close open close open 1-2 Serial 8 Bit (C1) 1-2 close open close open 1-2 Serial 16 Bit 1-2 open close open close μc Control Mode CS - Chip select. The system microcontroller selects the SO1813T by means of the pin CS. Whenever the pin is in a logic low state, data can be transferred from or to the μc. RD, WR (Read / Write) By pulling one of these pins down, a read or write transaction is initiated on the AddressData bus and the data becomes valid. These pins have internal Pull-Up resistors. AL (Address Latch nable) the pin AL is used to select between address (AL is in a logic High state) or data (AL is in a logic Low state). When AL is pulled high, addresses are transferred and latched over the bit AD0 to AD7. During the Low State of AL all read or write transactions hit the same adress. This pin has an internal Pull- Down resistor. The pins AD0.. AD7 are the bidirectional input / outputs for data write and read. Depending on the state of the AL, RD, WR pins, register addresses or data can be transferred between the internal registers and e.g. the microcontroller. The μc Control Mode can be operated by connecting a Processor Board to the corresponding Signals of Connector K4. The timing requirements for the μc Control Mode are shown in Figure 5. Application Note 8 V 1.0,

9 Functional Description VCC VCC AL /CS /RD /WR AD0 Nx AD1 AD2 AD3 AD4 AD5 AD6 AD7 MCU (e.g. X166) or ASC SO1813T SL parallel _interface_uc.vsd Figure 4 μc Control Mode /CS t CSD AL t RD_su t RDlow t RDhigh t RD_hd /RD t AD_su t AD_hd t ADvalid t float t clrrdy AD[7:0] GLRR address (04h) GLRR data GLRR data GLRR 00h Rd_timing_813T - Parallel _Timing_Read Figure 5 Timing Diagram μc Control Mode Read /CS AL t WR_su t CSD t WRhigh t WR_hd /WR t AD_su t AD_hd t WR_su t WR_hd t lat AD[7:0] COFLx address COFLx data 0FH COFLx data 0AH COFLx 00h 0Fh Wr_timing_813T - Parallel _Timing_Write Figure 6 Timing Diagram μc Control Mode Write Application Note 9 V 1.0,

10 Functional Description 3.4 Serial nterface The SO1813T contains two serial interfaces that can be activated by pulling the SL pin to logic High state. The interface can be directly controlled by the microcontroller output ports. The output pins SDO and SSO are in state Z as long as CS=1. Otherwise, the bits are sampled with the falling edge of CS. With every falling edge of SCLK the bits are provided serially to the pin SDO and SSO, respectively. At the same time, the inputs to SD, SS are registered into input-ffo buffers (sampled with the rising edge of SCLK). When all internally sampled bits have been transferred to SDO/SSO, the buffered bits from the inputs SD/SS are provided to these pins (daisy-chain support). The timing requirements for the serial interface are shown in Figure 8. The serial interface can be set to 8 Bit operation by using C1 only or to 16 Bit operation by using C1 and C2 in daisy-chain mode. For this purpose the jumpers K8, K9, K10 have to be set in the according manner (see also Figure 7) C1 SCLK SD SCLK SD Nx SS SSO SDO /CS SS /CS K8 C2 SCLK SD K10 K9 Nx SS SSO K12 K11 SSO SDO SDO /CS Figure 7 SP Configuration /CS inactive t SCLK_su active t CSD SCLK tsu receive edge thd transmit edge t SCLK tcsh SD, SS MSB LSB t CS_valid t SCLK_valid t float SDO, SSO MSB LSB Serial_Bus_Timing Figure 8 Timing Diagram Serial Mode Application Note 10 V 1.0,

11 Functional Description 3.5 Sensor nput Stage The sensor input structure is shown in Figure 9. Due to its active current a -V-characteristic as shown in Figure 10 is maintained. This -V-curve is well within the C standard requirements of Type 1 and Type 3 sensors, respectively. Type 2 sensors are supported as well with the restriction that 2 input channels have to be used in parallel i.e. only 4 channels are available. Additionally R N and R LD has to be modified according Figure 9. t is recommended to choose for the external resistors R N, R LD an accuracy of 2 % (< 5% is mandatory) otherwise the /V-characteristic shown in Figure 10 cannot be attained. The nput Type 1, 2, 3 can be selected by modifying R TS according Table 3. Table 3 Type Select nput Characteristic Type 1 Type 2 Type 3 according C R TS 33R 33k 330k P24 VBB TS RTS nputx Nx 2k (1,5k *) xh DATAx 12k (8.5k *) R N RLD xl 0V GNDBB *) : for Type2 Figure 9 Sensor nput Application Note 11 V 1.0,

12 Functional Description V F =30V 15V/11V VNxDset V NxDclr V NxDhys active current sink 5V -3V 0.5mA 2mA/3mA 15mA NxsnkC,M Data Bit must be zero Data Bit must be one Figure 10 Sensor nput Characteristic 3.6 Wire Break Detection The wire-break detection current can be adjusted by the R WB -resistor value connected to the pin WB (Figure 11). The minimum wirebreak-current can be choosen only when a LD- or Zener-Diode is connected to the pin xl with a forward current in the range of few ua in the voltage range below 1 V. n the case of a connected resistor at xl a great current is flowing across the external resistor Rext and the xl-resistor (R LD ). This part cannot be measured internally and has to be added to the internal current part. n this case the minimum adjustable current is 230uA (R LD = 2kOhm). The currently assembled WB resistor of 33kOhm leads to a WB detection limit of uA for Type 1/3 Sensor nterfaces. The WB bits in the status register have a sticky (latched) property and remains set as long as they are not cleared by a read access and the fault condition is not detected anymore. n case that a relay contact is connected to the input interface, the contact needs to be bypassed with a resistor to provide the needed WB current f the wire-break function is not needed, it can be switched off by setting the MWB bit in the registers COFL0-7. Application Note 12 V 1.0,

13 Functional Description Wire-Break-Current Versus RWB Wire-Break-Current[uA] RWB[kOhm] WBmin_LD WBmax_LD WBmin_Rled WBmax_Rled Figure 11 Wire Break Detection for Type 1/3 25 C) Wire-Break-Current Versus RWB Wire-Break-Current[uA] RWB[kOhm] WBmin_LD WBmax_LD WBmin_Rled WBmax_Rled Figure 12 Wire Break Detection for Type 2 25 C) Application Note 13 V 1.0,

14 Functional Description n the case of Type 2 two sense inputs need to be switched in parallel to achieve 2 * 3 ma (Figure 12). n each sense input a mimimum wirebreak current of 60 ua can be measured which means in sum a minimum wirebreak current of 120 ua. t is not recommended to use external resistors at the pins xl in case of wirebreak measurements. The recommended value would be R LD = 1.2 kohm which has been choosen in order not to produce a large voltage drop between xl and GNDBB which in turn would limit the voltage drop across the sink. But the low value of R LD would cause a high external current in case of wirebreak-measurements which has to be multiplied by two due to the parallel circuitry of the sense inputs. 3.7 Filter Setting The sensor data bits can be filtered by a configurable digital input filter. f selected, the filter changes its output according to an averaging rule with a selectable average length. When the sensor state changes without any spikes and noise the change is delayed by the averaging length. Sensor spikes that are shorter than the averaging length are suppressed. The averaging length is selected for each channel individually using the configuration registers COFL0-7. The programmed filter time apply for both the data and the diagnostics of one channel. See SO1813T datasheet for the different setting options including filter bypass. The filters are dimensioned for the nominal internal sampling fscannom. The corresponding filter delays can be adjusted by changing the oscillator frequency i.e. by tuning the resistor at the pin R OSC. The filters are dimensioned for the nominal internal sampling fscannom. The corresponding filter delays can be adjusted by changing the oscillator frequency i.e. by tuning the resistor at the pin R OSC. Application Note 14 V 1.0,

15 Functional Description 3.8 DC/DC Supply DC_NA VCC 21 5 uc Supply (5V / 3.3V) PP Output driver SW uF VBB 1uF Clk : 2 Temp. Sense 100nF DCK SW2 GND N1 N2 GNDBB GND 1, 7, 18 Tr uc-domain uc Supply (GND) dcdc _typapp.vsd Sense-Domain Figure 13 Typical Circuitry for Self Powered Mode with Push-Pull Converter The C can as well operate in self powered mode. n this case, the Process Side can be supplied at VBB with an isolated push-pull converter connected to the Micro-controller Side and driven by the pins SW1 and SW2. The internal driver stage at SW1 and SW2 is designed to power up two SO1813T parts. The DC/DC-Converter is driven by the internal clock. Parameters are calculated with the internal clock = 500 khz. By setting the bit DCK in the GLCFG register a prescaler by 2 can be activated. This may be useful to improve the M behaviour. Should the user adjusts another different frequency the transformer has to be adjusted accordingly. The built in short-circuit protection uses a temperature sensor located close to the drivers (Figure 13) and disables the driver stages when a predefined temperature is reached. That means that the drivers are switched off at a temperature of 160 C and switched on at a temperature of <=150 C The transformer will be offered by PCOS as a dedicated product for this SO1813T part. Order number for 3.3V to 500kHz: DS-T (see also Chapter 8). Special effort have to be spent on a proper layout, in order to minimize the noise caused by the DC/DC converter. As it can be seen in Figure 13 the current path of the DC/DC converter has to be layouted separately, using the ground pin 24. Please Note: the transformer as well as the necessary diode and capacitors are not assebled on the board. The recommended parts can be seen in the bill of material (Chapter 7). Application Note 15 V 1.0,

16 Connectors 4 Connectors Table 4 K1, K2 Connector Pin Number K1 (C1) K3 (C2) 1 V BB V BB 2 nput0 nput0 3 nput1 nput1 4 nput2 nput2 5 nput3 nput3 6 nput4 nput4 7 nput5 nput5 8 nput6 nput6 9 nput7 nput7 10 GND BB GND BB Table 5 K4 Connector Pin Number Serial Mode Parallel Mode 1 VCC VCC 2 RR RR 3 SYNC SYNC 4 RD 5 DS0 WR 6 DS1 AL 7 CS CS 8 SD D0 9 SSO D1 10 D2 11 D3 12 CRCRR D4 13 SCLK D5 14 SS D6 15 SDO D7 16 GND GND Application Note 16 V 1.0,

17 Connectors 1 1 SO1813T Figure 14 Board Assembly Application Note 17 V 1.0,

18 Schematic 5 Schematic Figure 15 Schematic Page 1 Application Note 18 V 1.0,

19 Schematic Figure 16 Schematic Page 2 Application Note 19 V 1.0,

20 PCB Layout 6 PCB Layout Figure 17 Board Layout - Component Side Figure 18 Board Layout - Bottom Side (mirror view) Application Note 20 V 1.0,

21 Bill of Material 7 Bill of Material Nr Count Pos. Value Package 1 2 C1, C7 470nF, 50V C11 10uF,10V C_AL_B 3 2 C2, C8 100nF, 50V C3 1uF, 50V C4 10uF, 10V C5, C6, C9, C10 4,7nF, 500V D1, D2, D3, D4, D5, D6, D7, D8, D10, D11, D12, D13, D14, D15, D16, D17 LD, gn KPHCM- 2012CGCK 0805-DOD 8 2 D18, D19 LD, rt KPHCM- 2012C-T 0805-DOD 9 0 D9 BAS70-05 SOT C1, C2 SO1813T TSSOP K1, K3 MKDS 1/10-3,81 KLMM_10_3, K9, K10, K11, K12 Connector 2pol 1X K6, K7, K8, K13, K14, K15, K16 Connector 3pol 1X K17, K18 Connector 1pol 1X K4 Connector 16pol 1X16-90 R1, R2, R3, R4, R5, R6, R7, R8, R24, R25, R26, 2k, 1% R27, R28, R29, R30, 1206 R R17, R40 1k R18, R41 33k R19, R42 33R R20, R43 100R R21, R44 22k R9, R10, R11, R12, R13, R14, R15, R16, R32, R33, R34, R35, 12k, 1% 1206 R36, R37, R38, R T1 DS-T ,3 SMD 24 5 Spacer D8mm, H2,8mm Application Note 21 V 1.0,

22 Transformer 8 Transformer n corporation by courtesy of PCOS Application Note 22 V 1.0,

23 References References [1] SO1813T, solated 8 Channel Digital nput with C Type 1/2/3 Characteristics, Data Sheet, nfineon Technologies Application Note 23 V 1.0,

24 Published by nfineon Technologies AG