OptiMOS 2 Power-Transistor

Transcription

1 IPI9N3LA, IPP9N3LA OptiMOS 2 Power-Transistor Features Ideal for high-frequency dc/dc converters Qualified according to JEDEC ) for target applications N-channel - Logic level Product Summary V DS 25 V R DS(on),max 9.2 mω I D 5 A Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Superior thermal resistance 75 C operating temperature dv /dt rated Pb-free lead plating; RoHS compliant PG-TO PG-TO22-3- Type Package Marking IPI9N3LA PG-TO N3LA IPP9N3LA PG-TO N3LA Maximum ratings, at T j =25 C, unless otherwise specified Parameter Symbol Conditions Value Unit Continuous drain current I D T C =25 C 2) 5 A T C = C 46 Pulsed drain current I D,pulse T C =25 C 3) 35 Avalanche energy, single pulse E AS I D =45 A, R GS =25 Ω 75 mj Reverse diode dv /dt dv /dt I D =5 A, V DS =2 V, di /dt =2 A/µs, T j,max =75 C 6 kv/µs Gate source voltage 4) V GS ±2 V Power dissipation P tot T C =25 C 63 W Operating and storage temperature T j, T stg C IEC climatic category; DIN IEC 68-55/75/56 ) J-STD2 and JESD22 Rev..9 page

2 IPI9N3LA, IPP9N3LA Parameter Symbol Conditions Values Unit min. typ. max. Thermal characteristics Thermal resistance, junction - case R thjc K/W SMD version, device on PCB R thja minimal footprint cm 2 cooling area 5) Electrical characteristics, at T j =25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS = V, I D = ma V Gate threshold voltage V GS(th) V DS =V GS, I D =2 µa Zero gate voltage drain current I DSS V DS =25 V, V GS = V, T j =25 C -. µa V DS =25 V, V GS = V, T j =25 C - Gate-source leakage current I GSS V GS =2 V, V DS = V - na Drain-source on-state resistance R DS(on) V GS =4.5 V, I D =3 A mω V GS = V, I D =3 A Gate resistance R G - - Ω Transconductance g fs V DS >2 I D R DS(on)max, I D =3 A S 2) Current is limited by bondwire; with an R thjc =2.4 K/W the chip is able to carry 64 3) See figure 3 4) T j,max =5 C and duty cycle D <.25 for V GS <-5 V 5) Device on 4 mm x 4 mm x.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 7 Rev..9 page

3 IPI9N3LA, IPP9N3LA Parameter Symbol Conditions Values Unit min. typ. max. Dynamic characteristics Input capacitance C iss pf Output capacitance C oss V GS = V, V DS =5 V, f = MHz Reverse transfer capacitance C rss Turn-on delay time t d(on) ns Rise time t r V DD =5 V, V GS = V, Turn-off delay time t d(off) I D =25 A, R G =2.7 Ω Fall time t f Gate Charge Characteristics 6) Gate to source charge Q gs nc Gate charge at threshold Q g(th) Gate to drain charge Q gd V DD =5 V, I D =25 A, Switching charge Q sw V GS = to 5 V Gate charge total Q g - 3 Gate plateau voltage V plateau V Gate charge total, sync. FET Q g(sync) V DS =. V, V GS = to 5 V nc Output charge Q oss V DD =5 V, V GS = V - 4 Reverse Diode Diode continous forward current I S A T C =25 C Diode pulse current I S,pulse Diode forward voltage V SD V GS = V, I F =5 A, T j =25 C V Reverse recovery charge Q rr V R =5 V, I F =I S, di F /dt =4 A/µs - - nc 6) See figure 6 for gate charge parameter definition Rev..9 page

4 IPI9N3LA, IPP9N3LA Power dissipation 2 Drain current P tot =f(t C ) I D =f(t C ); V GS V P tot [W] T C [ C] T C [ C] 3 Safe operating area 4 Max. transient thermal impedance I D =f(v DS ); T C =25 C; D = Z thjc =f(t p ) parameter: t p parameter: D =t p /T limited by on-state resistance µs µs.5 DC µs Z thjc [K/W].2..5 ms ms..2. single pulse. V DS [V] t p [s] Rev..9 page

5 5 Typ. output characteristics 6 Typ. drain-source on resistance I D =f(v DS ); T j =25 C R DS(on) =f(i D ); T j =25 C IPI9N3LA, IPP9N3LA parameter: V GS parameter: V GS 7 3 V 4.5 V 3.2 V 3.5 V 3.8 V 4. V V V R DS(on) [mω] V V V 3.2 V 3 V V 2 3 V DS [V] Typ. transfer characteristics 8 Typ. forward transconductance I D =f(v GS ); V DS >2 I D R DS(on)max g fs =f(i D ); T j =25 C parameter: T j g fs [S] C 25 C V GS [V] Rev..9 page

6 9 Drain-source on-state resistance Typ. gate threshold voltage IPI9N3LA, IPP9N3LA R DS(on) =f(t j ); I D =3 A; V GS = V V GS(th) =f(t j ); V GS =V DS parameter: I D µa R DS(on) [mω] 8 98 % typ V GS(th) [V].5 2 µa T j [ C] T j [ C] Typ. Capacitances 2 Forward characteristics of reverse diode C =f(v DS ); V GS = V; f = MHz I F =f(v SD ) parameter: T j 25 C Ciss Coss 75 C 75 C 98% C [pf] I F [A] 25 C 98% Crss V DS [V] V SD [V] Rev..9 page

7 IPI9N3LA, IPP9N3LA 3 Avalanche characteristics 4 Typ. gate charge I AS =f(t AV ); R GS =25 Ω V GS =f(q gate ); I D =25 A pulsed parameter: T j(start) parameter: V DD 2 5 C C 25 C 5 V 5 V 8 2 V I AV [A] V GS [V] t AV [µs] 2 Q gate [nc] 5 Drain-source breakdown voltage 6 Gate charge waveforms V BR(DSS) =f(t j ); I D = ma V GS Q g 26 V BR(DSS) [V] V gs(th) 22 2 Q g(th) Q sw Q gate T j [ C] Q gs Q gd Rev..9 page

8 IPI9N3LA, IPP9N3LA PG-TO : Outline PG-TO22-3-2: Outline Packaging Rev..9 page

9 IPI9N3LA, IPP9N3LA PG-TO22-3-2: Outline Packaging Rev..9 page

10 IPI9N3LA, IPP9N3LA Published by Infineon Technologies AG 8726 Munich, Germany 28 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office ( Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev..9 page