Type Ordering Code Package BTS 7750 GP Q67006-A9402 P-TO

Transcription

1 TrilithIC BTS 7750 GP Data Sheet Overview. Features Quad D-MOS switch driver Free configurable as bridge or quad-switch Optimized for DC motor management applications ow R DS ON : 70 mτ high-side switch, 45 mτ lowside switch (typical 25 C) Maximum peak current: typ C= Very low quiescent current: typ C= Small outline, thermal optimized PowerPak Full short-circuit-protection Operates up to 40 V Status flag diagnosis Overtemperature shut down with hysteresis Internal clamp diodes Isolated sources for external current sensing Under-voltage detection with hysteresis PWM frequencies up to khz P-TO Type Ordering Code Package BTS 7750 GP Q67006-A9402 P-TO Description The BTS 7750 GP is part of the TrilithIC family containing three dies in one package: One double high-side switch and two low-side switches. The drains of these three vertical DMOS chips are mounted on separated leadframes. The sources are connected to individual pins, so the BTS 7750 GP can be used in H-bridge- as well as in any other configuration. Both the double high-side and the two low-side switches of the BTS 7750 GP are manufactured in SMART SIPMOS technology which combines low R DS ON vertical DMOS power stages with CMOS control circuitry. The high-side switch is fully protected and contains the control and diagnosis circuitry. Also the low-side switches are fully protected, the equivalent standard product is the BTS 34 D. In contrast to the BTS 7750 G, which consists of the same chips in an P-DSO-28 package, the P-TO PowerPack offers a much lower thermal resistance, which opens up applications with even higher currents in the automotive and industrial area. Data Sheet

2 .3 Pin Configuration (top view) Molding Compound I NC S Heat-Slug D NC 4 SH GND 5 6 Heat-Slug 2 IH 7 DHVS 8 7 DHVS ST 9 IH2 0 SH2 NC I2 NC Heat-Slug 3 D2 S2 5 Figure Data Sheet

3 .4 Pin Definitions and Functions Pin No. Symbol Function I Analog input of low-side switch 2 NC Not connected 3 S Source of low-side switch 4 NC Not connected 5 SH Source of high-side switch 6 GND Ground of high-side switches 7 IH Digital input of high-side switch 8 DHVS Drain of high-side switches and power supply voltage 9 ST Status; open Drain output 0 IH2 Digital input of high-side switch 2 SH2 Source of high-side switch 2 2 NC Not connected 3 I2 Analog input of low-side switch 2 4 NC Not connected 5 S2 Source of low-side switch 2 6 D2 Drain of low-side switch 2 Heat-Slug 3 or Heat-Dissipator 7 DHVS Drain of high-side switches and power supply voltage Heat-Slug 2 or Heat-Dissipator 8 D Drain of low-side switch Heat-Slug or Heat-Dissipator Pins written in bold type need power wiring. Data Sheet

4 .5 Functional Block Diagram DHVS 8, 7 ST 9 Diagnosis Biasing and Protection IH IH2 GND IN OUT H 0 H H H R O R O2 6 SH2 D2 5 SH Protection 8 D I Protection I S S2 Figure 2 Block Diagram Data Sheet

5 .6 Circuit Description Input Circuit The control inputs IH,2 consist of TT/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs are protected by ESD clamp-diodes. The inputs I and I2 are connected to the internal gate-driving units of the N-channel vertical power-mos-fets. Output Stages The output stages consist of an low R DS ON Power-MOS H-bridge. In H-bridge configuration, the D-MOS body diodes can be used for freewheeling when commutating inductive loads. If the high-side switches are used as single switches, positive and negative voltage spikes which occur when driving inductive loads are limited by integrated power clamp diodes. Short Circuit Protection The outputs are protected against output short circuit to ground output short circuit to the supply voltage, and overload (load short circuit). An internal OP-Amp controls the Drain-Source-Voltage by comparing the DS-Voltage- Drop with an internal reference voltage. Above this trippoint the OP-Amp reduces the output current depending on the junction temperature and the drop voltage. In the case of overloaded high-side switches the status output is set to low. The fully protected low-side switches have no status output. Overtemperature Protection The high-side and the low-side switches also incorporate an overtemperature protection circuit with hysteresis which switches off the output transistors. In the case of the highside switches, the status output is set to low. Undervoltage-ockout (UVO) When V S reaches the switch-on voltage V UVON the IC becomes active with a hysteresis. The High-Side output transistors are switched off if the supply voltage V S drops below the switch off value V UVOFF. Data Sheet

6 Status Flag The status flag output is an open drain output with Zener-diode which requires a pull-up resistor, c.f. the application circuit on page 4. Various errors as listed in the table Diagnosis are detected by switching the open drain output ST to low. A open load detection is not available. Freewheeling condition does not cause an error. 2 Truthtable and Diagnosis (valid only for the High-Side-Switches) Flag IH IH2 SH SH2 ST Remarks Inputs Outputs Normal operation; identical with functional truth table Overtemperature high-side switch 0 Overtemperature high-side switch2 Overtemperature both high-side switches H H H H stand-by mode switch2 active switch active both switches active 0 detected 0 detected 0 0 detected detected Undervoltage not detected Inputs: Outputs: Status: 0 = ogic OW Z = Output in tristate condition = No error = ogic HIGH = Output in sink condition 0 = Error = don t care H = Output in source condition = Voltage level undefined Data Sheet

7 3 Electrical Characteristics 3. Absolute Maximum Ratings 40 C < T j < 50 C Parameter Symbol imit Values Unit Remarks min. max. High-Side-Switches (Pins DHVS, IH,2 and SH,2) Supply voltage V S V Supply voltage for full short V S(SCP) 28 V circuit protection HS-drain current I S 0 * A T C = 25 C; DC HS-input current I IH 5 5 ma Pin IH and IH2 HS-input voltage V IH 0 6 V Pin IH and IH2 Note: * internally limited Status Output ST Status pull up voltage V ST V Status Output current I ST 5 5 ma Pin ST ow-side-switches (Pins D,2, I,2 and S,2) Drain-Source-Clamp voltage V DS 42 V V I =0V; I D ma Supply voltage for short V DS(SCP) 36 V V I =5V circuit protection 20 V V I =0V S-drain current I D 2 * A T C = 25 C; DC S-input voltage V I V Note: * internally limited Temperatures Junction temperature T j C Storage temperature T stg C Data Sheet

8 3. Absolute Maximum Ratings (cont d) 40 C < T j < 50 C Parameter Symbol imit Values Unit Remarks min. max. Thermal Resistances (one HS-S-Path active) S-junction case R thjc.7 K/W HS-junction case R thjc H.7 K/W Junction ambient R thja = T j(hs) /(P (HS) +P (S) ) R thja 26 K/W device soldered to reference PCB with 6cm 2 cooling area ESD Protection (Human Body Model acc. MI STD 883D, method and EOS/ ESD assn. standard S ) Input S-Switch V ESD 2 kv Input HS-Switch V ESD kv Status HS-Switch V ESD 2 kv Output S and HS-Switch V ESD 8 kv all other pins connected to Ground Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 3.2 Operating Range 40 C < T j < 50 C Parameter Symbol imit Values Unit Remarks min. max. Supply voltage V S V UVOFF 42 V After V S rising above V UVON Input voltages V IH V Input voltages V I V Output current I ST 0 2 ma Junction temperature T j C Note: In the operating range the functions given in the circuit description are fulfilled. Data Sheet

9 3.3 Electrical Characteristics I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Parameter Symbol imit Values Unit Test Condition min. typ. max. Current Consumption HS-switch Quiescent current I S 5 8 A IH = IH2 = 0 V T j = 25 C 2 A IH = IH2 = 0 V Supply current I S ma IH or IH2 = 5 V V S = 2 V ma IH and IH2 = 5 V V S = 2 V eakage current of highside switch I SH K 6 A V IH = V SH = 0 V eakage current through logic GND in free wheeling condition I KC = 0 ma I FH = 3 A I FH + I SH Current Consumption S-switch Input current I I 8 30 A V I = 5 V; normal operation A V I = 5 V; failure mode eakage current of lowside switch I D K 2 0 A V I = 0 V Under Voltage ockout (UVO) HS-switch Switch-ON voltage V UVON 4.5 V V S increasing Switch-OFF voltage V UVOFF V V S decreasing Switch ON/OFF hysteresis V UVHY V V UVON V UVOFF Data Sheet

10 3.3 Electrical Characteristics (cont d) I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Parameter Symbol imit Values Unit Test Condition min. typ. max. Output stages Inverse diode of high-side switch; Forward-voltage Inverse diode of lowside switch; Forward-voltage Static drain-source on-resistance of highside switch Static drain-source on-resistance of lowside switch V FH V I FH = 3 A V F V I F = 3 A R DS ON H mτ I SH =A T j = 25 C R DS ON mτ I S =A; V G = 5 V T j = 25 C Static path on-resistance R DS ON 285 mτ R DS ON H +R DS ON I SH =A; Short Circuit of highside switch to GND Initial peak SC current I SCP H A T j = 40 C A T j = + 25 C A T j = + 50 C Short Circuit of highside switch to V S Output pull-down-resistor R O kτ V DS = 3 V Short Circuit of lowside switch to V S Initial peak SC current I SCP A T j = 40 C A T j = 25 C 4 8 A T j = 50 C Data Sheet

11 3.3 Electrical Characteristics (cont d) I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Parameter Symbol imit Values Unit Test Condition min. typ. max. Thermal Shutdown Thermal shutdown junction temperature Thermal switch-on junction temperature T j SD C T j SO C Temperature hysteresis αt 0 C αt = T jsd T jso Status Flag Output ST of highside switch ow output voltage V ST V I ST =.6 ma eakage current I ST K 0 A V ST = 5 V Zener-limit-voltage V ST Z 5.4 V I ST =.6 ma Switching times of highside switch Turn-ON-time; to 90% V SH t ON s R oad = 2 τ V S = 2 V Turn-OFF-time; to 0% V SH t OFF s R oad = 2 τ V S = 2 V Slew rate on 0 to 30% V SH dv/dt ON. V/ s R oad = 2 τ V S = 2 V Slew rate off 70 to 40% V SH -dv/ dt OFF.5 V/ s R oad = 2 τ V S = 2 V Note: switching times are guaranteed by design Data Sheet

12 3.3 Electrical Characteristics (cont d) I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Parameter Symbol imit Values Unit Test Condition min. typ. max. Switching times of lowside switch Turn-ON-time 70 to 50% V SH V I = 0 to 0 V t ON s R oad = 2 τ V S = 2 V Turn-OFF-time; t OFF s R oad = 2 τ to 0% V S V S = 2 V Slew rate on 70 to 50% V SH V I = 0 to 0 V Slew rate off 50 to 70% V SH V I = 0 to 0 V Note: switching times are guaranteed by design -dv/dt ON.0 V/ s R oad = 2 τ V S = 2 V dv/dt OFF.0 V/ s R oad = 2 τ V S = 2 V Control Inputs of highside switches GH, 2 H-input voltage V IH High 2.5 V -input voltage V IH ow V Input voltage hysterese V IH HY 0.3 V H-input current I IH High A V IH = 5 V -input current I IH ow 5 20 A V IH = 0.4 V Input series resistance R I kτ Zener limit voltage V IH Z 5.4 V I IH =.6 ma Control Inputs G, 2 -threshold-voltage V I th V I D = 2 ma Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T A = 25 C and the given supply voltage. Data Sheet

13 V S =2V I S C S 470nF C 00µF I FH,2 DHVS I ST K 8, 7 I ST ST 9 V DSH2 V DSH -V FH2 -V FH Diagnosis Biasing and Protection V ST V ST I IH IH 7 V STZ V IH I IH IH2 0 R O R O2 6 SH2 D2 I SH2 I D2 V IH2 GND 6 I D K 2 V UVON I GND 5 SH I SH V UVOFF I KC Protection 8 D I D I D K I I I Protection V I V I th I I2 I2 3 V I2 3 5 V DS V DS2 V I th 2 S S2 -V F -V F2 I SCP I SCP 2 I S I S2 Figure 3 Test Circuit HS-Source-Current Named during Short Circuit Named during eakage- Cond. I SH,2 I SCP H I D K Data Sheet

14 Watchdog Reset Q TE 4278G I V S =2V R Q 00 kτ C Q 22µF D C D 47nF D0 Z39 C S 0µF WD R V CC DHVS 8, 7 R S ST 9 0 kτ Diagnosis Biasing and Protection IH 7 IH2 0 R O R O2 6 SH2 D2 µp GND 6 5 SH M Protection 8 D I Protection I2 3 GND 3 S 5 S2 In case of V DS <-0.6V or reverse battery the current into the µc might be limited by external resitors to protect the µc Figure 4 Application Circuit Data Sheet

15 4 Package Outlines P-TO (Plastic Transistor Single Outline Package) (5) 9.25 ±0.2 ±0.3 ± ± ± ± ) 8.3 ) 4.4 B 0. A ) 8.4 ) x ±0..27 ±0. 4.7± ±0.3 8 max. 0.5 ± M A B ) Typical All metal surfaces tin plated, except area of cut. GPT095 GPS0523 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book Package Information. SMD = Surface Mounted Device Dimensions in mm Data Sheet

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