A NEW DIFFERENTIAL CONFIGURATION SUITABLE FOR REALIZATION OF HIGH CMRR, ALL-PASS/NOTCH FILTERS

Transcription

1 A NEW DIFFEENTIAL CONFIGUATION SUITABLE FO EALIZATION OF HIGH CM, ALL-PASS/NOTCH FILTES SHAHAM MINAEI, İ.CEM GÖKNA, OGUZHAN CICEKOGLU. Dogus University, Department of Electronics and Communication Engineering, Acibadem, 347, Istanbul, TUKEY. www3.dogus.edu.tr/sminaei Tel: Bogazici University, Electrical and Electronics Engineering Department, Bebek, 8085, Istanbul, TUKEY. Fax: Keywords: Differential Me, All-Pass Filters, Notch Filters, Current Conveyor

2 Abstract: In this paper, a new configuration suitable for realization of differential inputdifferential output first order, second order all-pass and notch filters with high CM is given. The proposed configuration uses two negative type second-generation current conveyors (CCII-), and three admittances. Two first order and one second order all-pass filters and a notch filter (tunable if current controlled conveyor CCCII is used) are extracted from the proposed configuration. Tracking error, element mismatch, sensitivity analysis, simulation and experimental results are included.. INTODUCTION All-pass filters, also called phase equalizers are widely used for phase shifting while keeping the amplitude of input signal constant over the frequency range of interest. They can be used to equalize the undesired phase change as a result of processing the signal; they can also be used in the synthesis of multiphase oscillators. Notch filters on the other hand are used to eliminate a single frequency called the notch frequency. Several all-pass and notch filter realizations using active elements are available in the literature [-8]. These circuits use active elements such as second-generation current conveyors (CCII) [-7, 9-, 5, 7], operational amplifiers [, 7], current differencing buffered amplifiers (CDBA) [3], four terminal floating nullors (FTFN) [8,4], third-generation current conveyors (CCIII) [6, 8] together with passive elements. However all of these phase equalizers are single input-single output structures [-8]. Due to recent advances in integrated circuit technology it is possible to place analog as well as digital components on the same chip, thus obtaining mixed me signal processing circuits. Mixed-me signal processing attracts increasing attention since it simplifies design, enables compactness and reduces cost. However signal interference from the digital to the analog part remains a serious problem to overcome; hence, for such circuits differential building blocks are accepted as a go solution. Therefore it is desired to process signals in differential form rather than simply as referenced to ground. Another advantage of differential operation over the singleended case is that the amplitude of the signal increases by a factor of [9]. An important parameter of differential active structures is the common-me rejection ratio (CM). Differential signals have the advantage of canceling common-me interference from unwanted signals and/or noise. This paper presents a general configuration for realizing differential-input differential-output voltage-me all-pass/notch filter circuits in Section ; it consists of two CCIIs and three

3 admittances and, has very high CM, independent of matching element values. In Section 3, two first order, one second order all-pass and notch low sensitivity filter circuits are derived. In all of the filter circuits the CCIIs can be replaced by a current controlled conveyor (CCCII); one of these filter circuits has only external capacitors, which makes it much more feasible for IC implementation. For all the circuits the pole frequency can be controlled electronically by adjusting the bias currents of the CCCIIs without disturbing the unity gain of the filter. The advantages of the configuration are exhibited by considering the effects of the tracking error and element mismatch on the output, CM and differential gain, in Section 4. Section 5 contains comparative simulation results of all the filter circuits using transistor level implementation for the current conveyors. In Section 6 two of the proposed filters are constructed practically, while Section 7 concludes the paper.. THE POPOSED CONFIGUATION CCII has become very popular because of its high performance coupled with functional versatility. It has led to a wide application for implementation of high performance electronic functions operating in voltage me or current me [0]. The circuit symbol of CCII is shown in Fig. and its terminal relations in expression (): I I y x z I 0 y x z () Figure. Circuit symbol of the CCII. The symbol of the CCCII proposed in [] is shown in Fig. and is characterized by: I I y x z x 0 0 I 0 y x z () 3

4 Figure. Circuit symbol of CCCII. Here the parasitic resistance x is the input resistance at terminal X and for BJT realizations it can be expressed as T x (3) I o where T is the thermal voltage and I 0 is the bias current of the CCCII []. Conventionally the + or signs of I Z in equalities () and () denote the positive and negative type of current conveyors respectively. The proposed general differential configuration is presented in Fig. 3. The differential input is connected to the Y terminals of the conveyors and the differential output voltage is taken across the Z terminals. Figure 3. Proposed differential configuration. Defining id i i, the outputs as: ic i i, and o o, routine analysis of the circuit yields Y o ic ( ) id (4) Y 4

5 Then the differential output is: Y o ic ( ) id (5) Yˆ Y Yˆ Y ( Y Yˆ ) (6) o o YYˆ id If the output is expressed in terms of id and ic as then, A A (7) dm id cm ic and Y Ŷ Y (Y Ŷ ) A dm (8) Y Ŷ A 0 (9) cm are obtained. Note that the common-me gain (A cm ) of the circuit is equal to zero, independent of passive elements mismatches. Therefore the common-me rejection ratio of the filter can be found theoretically as which implies that the circuit has potentially high CM. Adm CM 0 log0 (0) A cm 3. FILTE CICUITS DEIED FOM THE CONFIGUATION From the proposed differential configuration given in Fig. 3, different realizations for all-pass and notch filters can be extracted. 3.. First Order All-Pass Sections If in Fig. 3, the admittances are taken to be Y, ˆ Y and Y then the sc configuration yields a first-order C all-pass filter; the filter circuit is shown in Fig. 4. 5

6 Figure 4. High CM first order C All-Pass Filter. Single ended and differential outputs of the circuit are obtained as: o o ( Cs) ic ( ) Cs id () ( Cs) ( Cs) ic ( ) Cs id () ( Cs) id Cs ( ) Cs (3) By expressing the output as given in (7) and ( )Cs (4) Cs A dm A 0 (5) result. Selecting = = the differential transfer function reduces to cm id Cs Cs and the filter has the following phase response ( ) arctan( C) (7) (6) 6

7 Equation (6) implies that the proposed circuit realizes transfer functions of a first order voltage me all-pass filter with a gain of unity in magnitude. From equation (7) it can be seen that the circuit yields a phase shift from 0 o to -80 o. By C-C transformation, namely letting Y sc, Yˆ sc and Y in the sc configuration shown in Fig. 3, a new first-order all-pass filter can be obtained as shown in Fig. 5. Figure 5. High CM first order filter after C-C transformation. outine analysis of the circuit shown in Fig. 5 yields for the outputs of the circuit o C ( Cs) ic C C CC s id, (8) C ( C s) o C ( Cs) ic C C CC s id, (9) C ( C s) and C C s (0) C id Cs for the differential output. Then differential and common me gains are: C Cs C () C s A dm 7

8 and A 0 () cm Note that the common-me gain (A cm ) of the circuit is always equal to zero. Selecting C =C =C the differential transfer function reduces to and the filter has the following phase response id Cs Cs (3) ( ) 80 arctan( C) (4) From (3) and (4) it can be seen that the circuit realizes a first order voltage me all-pass filter with a gain of unity in magnitude and yields a phase shift from 80 o to 0 o. The pole frequency for both circuits shown in Figs. 4 and 5 is found as: f p (5) C From equation (5) one can realize that the pole frequency can be adjusted by changing the value of the capacitor C or the resistor without disturbing the unity gain of the phase equalizer. p p Moreover the sensitivity of the pole frequency is: S S. In order to obtain a circuit more suitable for IC implementation, CCCII-s are used instead of CCII-s in the circuit of Fig. 5 resulting in a realization using only external capacitors as shown in Fig. 6. In fact in the circuit shown in Fig. 6, the parasitic resistances at terminals X of the CCCII-s replace the resistor in the circuit shown in Fig. 5. f f C Figure 6. High CM first order only C all-pass filter. 8

9 All the equalities (8)-(5) are valid for the proposed circuit shown in Fig. 6 by replacing with x + x ; the transfer function becomes: id ( x x ) Cs (6) ( ) Cs x x with phase response ) 80 arctan( C( x )) (7) ( x and pole frequency f p (8) ( ) C x From equality (8) one can easily deduce that the pole frequency of the circuit can be adjusted by changing the value of the capacitor C and/or the electronically adjustable resistors x, x according to (3), without disturbing the unity gain property. x 3.. Second Order ealizations The proposed configuration can be used for realizing second order filters. By choosing, Y Yˆ sc and Y for the admittances shown in Fig. 3 a second order all- sc pass/notch filter can be obtained as shown in Fig. 7. Figure 7. High CM second order All-Pass/Notch Filter. 9

10 The differential output voltage in this case is given by By expressing the output as given in (7) C C s ( ) s CC C CC o o id (9) s ( ) s C C C C and are obtained. A dm s C C ( C C (30) s ( C C C )s C C )s C C A 0 (3) cm 3... All-Pass-Section For realizing the second order all-pass filter the following condition must be satisfied: C C C C C C which forces the following relation between resistor values Then the filter has the phase response: ) C, (3) C ( (33) C ( ) arctan C C ( C C (34) ) As opposed to the first order realizations this circuit yields a phase shift from 0 o to -360 o and better pole frequency sensitivity. The pole frequency and the related sensitivities are: f p (35) C C f p p S S / for i=,. i f C i 0

11 3... Notch Filter Another advantage of the circuit shown in Fig. 7 is its tunability by adjusting the value of resistor (via the bias current I 0 in the BJT implementation) to obtain a notch filter. Using: in the expression (30) for the gain yields: s ( C C ( (36) C ) s C C A dm (37) C As implied by (37) the notch frequency occurs at f n )s C C with same sensitivities. C C 4. TACKING EO AND MISMATCH ANALYSIS Taking into account the current conveyor non-idealities the terminal relations in () can be expressed as I Z =I X X = Y and I Y =0 (36) where =- i and =- v. Here i and v ( i << and v <<) represent the current and voltage tracking errors of the current conveyors, respectively. eanalyzing the proposed configuration shown in Fig. 3 and expressing the output in the form given in (7) yield: ( )( Y Y Yˆ Y ) ( )( Y Y Yˆ Y ) o o ic YYˆ YYˆ id (37) and A dm A cm ( )( ẐY ZY ) (38) )( Zˆ Y Z ) (39) ( Y where Z=/Y. Note that: i) Z, Z ˆ, Y, being rational functions, the denominator in (38) therefore all pole frequencies are independent of tracking errors and the notch frequency is independent of voltage tracking errors,.

12 ii) in this case the common-me gain (A cm ) of the configuration is not equal to zero. The common-me rejection ratio of the filter can be found theoretically as: A ˆ ˆ dm YY ( )( YY YY ) CM 0 log0 0 log0 (40) A ( )( Y Y Yˆ Y ) cm which shows that the CM of the filter has a very high value because both of the parameters and are close to unity, iii) for nominal values of all parameters is related to id by: = ( Z Y ) id (4) In the sequel will be assumed to simplify the analysis and not without justification since the designer must exercise special care to ensure the rejection of the common me voltage at the output as expressed in (37). Letting Zˆ Z Z and for the disturbed output, ZY ( i ) ( Z Z) Y ( i id ) (4) and using (4) equality (43) is obtained for the deviation in the output. ( i i ) Z ( i Z Y id ) (43) Neglecting second order terms and that Z Y =, the expression for the relative error then becomes : Z ( i i ) ZY Z (44) To get a feeling of what equality (44) means let 0, then i i Z / jc which decreases in the worst case to Z as e.g. for = x + x = 300(as is the case for only C all-pass filter simulation with I I 0A for CCCIIs), o o Z, a very small deviation at the output 300

13 5. SIMULATION ESULTS All the circuits have been simulated using the SPICE simulation program to verify the theoretical analysis. 5.. First Order C All-Pass Filter Simulation For the conveyor CCII- in the first order all-pass filter the schematic implementation shown in Fig. 8 [] with a DC supply voltage. 5 has been used. Figure 8. CMOS implementation of the CCII-. Transistors are simulated using 0.35m TSMC CMOS technology with parameters given in Table. and dimensions in Table. For the first order all-pass filter shown in Fig. 4 the element values are selected as: C=00pF and = =0k, I B =00A, I B =00A which result in a 90 o phase shift at f p =58.8 khz and is very close to its ideal value (f p =59. khz). The magnitude and phase characteristics of the simulated circuit are shown in Fig. 9 from which it can be seen that the simulation results agree quite well with the theoretical analysis. Table. 0.35m TSMC Mel parameters of MOS transistors.model NM NMOS (LEEL=3 TOX=7.9E-9 NSUB=E7 GAMMA= PHI=0.7 TO= DELTA=0 UO= ETA=0 THETA= KP= E-4 MAX= E4 + KAPPA= SH= NFS=E TPG= XJ=3E-7 LD=3.678E- WD= E-8 + CGDO=.8E-0 CGSO=.8E-0 CGBO=E-0 CJ=E-3 PB= MJ= CJSW= E-0 + MJSW= ).MODEL PM PMOS (LEEL=3 TOX=7.9E-9 NSUB=E7 GAMMA= PHI=0.7 TO= DELTA=0 UO=.3980 ETA= E-4 THETA= KP= E-5 MAX=.855E5 + KAPPA=.5 SH= NFS=E TPG=- XJ=E-7 LD= E-3 WD=.4987E-7 + CGDO=3.09E-0 CGSO=3.09E-0 CGBO=E-0 CJ=.49508E-3 PB= MJ=0.5 + CJSW= E-0 MJSW=0.5) 3

14 Table. Transistor dimensions of the CCII-. Transistor W [m] L [m] M, M M 3, M 4, M 6, M M 5, M 8 M Figure 9. The magnitude and phase characteristics of the first order all-pass filter of Figure First order only C All-Pass Filter Simulation The only C filter shown in Fig. 6 has been simulated using the CCCII- schematic implementation shown in Fig. 0 [] with a DC supply voltage of.5. Q 0 Q 9 Q Q 8 7 I Q 7 + CC Q 8 Y I Q Q X Z I O Q 3 Q 4 Iy I x Q3 Q 4 I 4 I 3 Q Q 5 Q Q 6 I z Q Q EE Figure 0. Schematic implementation for the CCCII. The PNP and the NPN transistors have been simulated using the parameters of the P00N and N00N bipolar transistors [3]; they are shown in Table 3. 4

15 Table 3. Mel parameters of BJT s N00N and P00N.MODEL N00N NPN (IS=E-08 BF=37.5 AF=59.4 IKF=6.974E-3 ISE=36E-6 + NE=.73 B=0.758 A=0.73 IK=.98E-3 E= B=54.6 BM=5 C=50 + CJE=0.4E- JE=0.5 MJE=0.8 CJC=0.983E-3 JC=0.5 MJC=0.3 XCJC= CJS=0.93E- JS=0.64 MJS=0.4 FC=0.5 TF=0.45E-9 T=0.45E-8 EG=.06 + XTB=.538 XTI=).MODEL P00N PNP (IS=73.5E-08 BF=0 AF=5.8 IKF=.359E-3 ISE=5.E-6 + NE=.650 B= A=9.96 IK=6.478E-3 E=3 B=37 BM=4.55 C=50 + CJE=0.80E- JE=0.5 MJE=0.8 CJC=0.64E- JC=0.8 MJC=0.4 XCJC= CJS=.03E- JS=0.55 MJS=0.35 FC=0.5 TF=0.60E-9 T=0.60E-8 EG=.06 + XTB=.866 XTI=.7) The element values are selected as: C=00pF, I o =I o =0A ( x = x =650) which result in a 90 o phase shift at f p =608 khz and is very close to its ideal value (f p =6.kHz). Magnitude and phase characteristics of the simulated circuit are shown in Fig. and the simulation results agree quite well with the theoretical analysis. Figure. The magnitude and phase characteristics of the only C all-pass filter. 5.3 Second Order All-Pass Filter Simulation The second order all-pass circuit shown in Fig. 7, has been simulated with the schematic implementation shown in Fig. 8 and MOS mel parameters and dimensions given in Table and, respectively. The element values are selected as: C =C =00pF and = =0k, I B =00A, I B =00A which result in a 80 o phase shift at f p =60 khz and is very close to its ideal value (f p =59. khz). Magnitude and phase characteristics of the simulated circuit are shown in Fig. and the simulation results agree quite well with the theoretical analysis. 5

16 Figure. The Magnitude and Phase characteristics of the second-order all-pass filter. 5.4 Notch Filter Simulation Keeping the same element values as for second order all-pass filter but changing to 30 k the characteristic shown in Fig. 3 is obtained for the notch filter. The theoretical notch frequency being f n =9.8 khz, the simulated notch frequency was found to be f n =90. khz showing very go agreement. Figure 3. Magnitude characteristic of the notch filter. 6. EXPEIMENTAL ESULTS The first and second order C all-pass filters shown in Figs. 4 and 7 are constructed on National Instrument experimental board (Elvis) using AD844-type current conveyor (CCII+) IC of Analog Devices, % tolerance discrete resistors and polystyrene capacitors. The supply voltages are chosen as 5. To implement a CCII-, two CCII+ are used as shown in Fig. 4. 6

17 Figure 4. Implementation of a CCII- using two CCII+. The circuit of Fig. 4 is constructed with = =0k, C=0nF. The experimental result shows that the input and output signals are in 90 o phase difference at a pole frequency of.60 khz as shown in Fig. 5. Fig. 6 shows the experimental results for the circuit of Fig. 7 obtained with = =0k, C =C = 0nF which results in a 80 o phase difference between input and output signals at the circuit pole frequency.60khz. Figure 5. Experimental results of the first order C all-pass filter (vertical scale: 00m/divider, horizontal scale: 00µs/divider, blue color: output; green color: input). 7

18 Figure 6. Experimental results of the second order all-pass filter (vertical scale: 00m/divider, horizontal scale: 00µs/divider, blue color: output; green color: input). 7. CONCLUSION In this paper a fully differential high CM general configuration for realizing first and second order all-pass and notch filters has been presented. The proposed configuration contains two CCII-s and three admittances. Two realizations for first order all-pass filter and one realization for second order all-pass filter have been given; it has been also shown that the second order filter can be tuned to behave like a notch filter. The pole frequency of the proposed filters and the notch frequency can be changed without disturbing the gain of the circuit. The non-ideality effects of current conveyors and element mismatches on the CM, voltage gains, pole and notch frequencies of the filters have been investigated and shown to be of negligible effect. The experimental and simulation results are given and shown to be in go agreement with theoretical analysis. 8. EFEENCES [] A. M. Soliman, Inductorless realization of an all-pass transfer function using the current conveyor. IEEE Transactions on Circuit Theory, CT-0, pp. 80-8, 973. []. I. Salawu, ealization of an all-pass transfer function using the second generation current conveyor. Proceedings of the IEEE, 68, pp

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