Critical Design Review

Transcription

1 LART-CS08(Train Spotting) Critical Design Review March 10, 2008 ECE 492 Spring 2008

2 System Block Diagram Low-Level Networking UI/Controller

3 W4 W8 W3 W7 System Block Diagram W1 W6 W5

4 System Block Diagram

5 System Timing Analysis Delay 1 1msec Delay 2 41usec Delay 3 2.5msec Sensor Trigger PIC RS-232 PC Delay msec Delay 5 9.2msec Delay 4 10msec Delay 7b 5.6msec Slave Delay 7a 20usec Hardware Path-a Delay = = msec Path-b Delay = = msec Critical Path Train Speed = 50cm/sec Delay 8a 1.1usec Delay 8b 1msec Rails Switch Critical Distance = 5cm 100msec

6 Technical System Requirements Requirements Software Network Hardware R001 rail switch control R002 engine power control R003 train proximity monitoring R004 expandability and adaptability R005 control and monitoring speed R006 applications programming interface R007 maintenance user interface R008 demonstration application R009 modifications of the CFE layout R010 power input

7 General Project Requirements Requirements Software Network Hardware GPR001 documentation GPR002 environmental GPR003 EMI/EMC GPR004 hazmats GPR005 safety and good practice GPR006 reliability GPR007 maintainability GPR008 sourcing sustainability GPR009 global sustainability GPR010 ethics report GPR011 project demonstration GPR012 final disposal of projects

8 Other System Requirements Ethical Requirements Requirements Software Network Hardware ER001 trains will not crash ER002 train acceleration Maintainability Requirement Requirements Software Network Hardware MR001 Mean Time To Repair Reliability Requirements Requirements Software Network Hardware RR001 Mean Time Between Failure RR002 System life

9 System Risk Assessment High risk subsystems RS-232 communication (PC to PIC) Digital to PWM on PIC API Lower risk subsystems GUI Automatic control software Hardware that resides on the end of the system Low level hardware to power circuits/rails Switch control hardware Sensor hardware

10 System Risk Assessment Subsystems Calculated Risk Factor Risk Level UI/API Group: Maintenance/Demo User Interface Low UI/API Group: Maintenance/Demo Control Medium UI/API Group: API Medium Networking Group: RS-232Communication Medium Networking Group: Sensor Polling High Networking Group: Rail control Medium Networking Group: Switch control High Low-Level Group: Overall system power Medium Low-Level Group: Rail power Medium Low-Level Group: Rail Switching Medium Low-Level Group: Sensors Medium

11 Cost Analysis Direct Costs: Octopus-550, PICs, heat sinks, serial cables, power supply etc. (detailed on Bill of Materials): $1, $600 for board fabrication Total direct costs: $2, Indirect Costs: Labor (2590 $20/hr), Total indirect costs: $51, Total Costs for project: $53,833.53

12 Management Plan Post CDR Management team (Alex, Taha, Shrijan) More streamlined communication Update Weekly task/schedule Write status letters Documentation divided up among team Fabrication done in 2 batches Integration led by networking group Software coding to be completed by April 7th

13 Management Plan Post CDR 03/23 03/30 04/04 04/14 04/28 03/12 Solder, Test & Improve Boards Batch1 2 nd Batch of Boards Fabrication Solder 4-5 people 04/07 boards Batch2 Test & Integrate Subsystems 8-9 people Software coding Software Integration & Testing 03/30 04/04 Networking Team, codes CRC + Watchdog timer

14 Software Top Level Diagram

15 API UML Diagram (1)

16 API UML Diagram (2) To ControllerMain (C3) To DemoControl (C2) -rails : List<Rail> -switches : List<Switch> -sensors : List<Sensor> -name : string -builddecode : BuilderDecoder (C4) -railvalues : Map<Rail,Integer> -switchvalues : Map<Switch,Integer> -maxrails : int -maxswitches : int Station (O1) -sensorvalues : Map<Sensor, Boolean> +Station() +Station(in name : String, in builddecode : BuilderDecoder (C4), in maxrails : int, in maxswitches : int) +addrail(in r : Rail (O3)) +addswitch(in s : Switch (O4)) +addsensor(in s : Sensor (O3)) +getname() : String +setname(in name : String) +setbuilddecode(in builddecode : BuilderDecoder (C4)) +setrailvalue(in rail : Rail (O3), in value : int) +setswitchvalue(in sw : Switch (O4), in value : int) +build(in railvalues : int[], in switchvalues : int[]) +getrailvalue(in r : Rail (O3)) : int +getswitchvalue(in s : Switch (O4)) : int +getsensorvalue(in s : Sensor (O3)) : boolean To MaintenanceControl (C1) -position : Rail (O3).railPosition -rail : Rail (O3) -num : int Sensor (O3) -value : boolean +Sensor() +Sensor(in rail : Rail (O3), in num : int, in position : Rail (O3).railPosition) +setposition(in position : Rail (O3).railPosition) +getposition() : Rail (O3).railPosition +getrail() : Rail (O3) +setrail(in rail : Rail (O3)) +getnum() : int +setnum(in num : int) +getvalue() : bool BuilderDecoder (C4) -ports : List<SerialPort> -listeners : List<SensorListener> +BuilderDecoder() +build(in station : int, in railvalues : int[], in switchvalues : int[]) +serialevent(in e : SerialPortEvent) +addsensorlistener(in s : SensorListener) From Switch (O4) From Rail (O2)

17 API UML Diagram (3)

18 Demonstration GUI

19 Maintenance GUI Trainspotting Maintenance Mode File Help Operating Mode Maintenance Mode Exit Demonstration Mode Station 1 3 rd Street Station > -> > -> STOP!?!

20 XML Document Hierarchical Structure LARTS Station Rail Sensor Switch

21 XML Document (Station) Station Name Number of Rails Number of Switches Number of Sensors Example: <NAME>Station 1-3rd Street Terminal</NAME> <NUMRAILS>7</NUMRAILS> <NUMSENSORS>6</NUMSENSORS> <NUMSWITCHES>2</NUMSWITCHES>

22 XML Document (Rail) Rail Name Number Left Connection Right Connection Row Length Example: <STATIONNAME>Station 1</STATIONNAME> <NUM>1.0</NUM> <LEFTCON>-1.0</LEFTCON> <RIGHTCON>1.1</RIGHTCON> <ROW>1</ROW> <LENGTH>300</LENGTH>

23 XML Document (Sensor) Sensor Name Number Rail Number Rail Position Example: <STATIONNAME>Station 1</STATIONNAME> <NUM>0</NUM> <RAILNUM>1.0</RAILNUM> <RAILPOS>RAIL_MIDDLE</RAILPOS>

24 XML Document (Switch) Switch Station Name Number Left Rail Right Rail Left Position Right Position Direction Polarity Example: <STATIONNAME>Station 1</STATIONNAME> <NUM>0</NUM> <LEFTRAIL>1.1</LEFTRAIL> <RIGHTRAIL>1.6</RIGHTRAIL> <LEFTPOS>RAIL_LEFT</LEFTPOS> <RIGHTPOS>RAIL_MIDDLE</RIGHTPOS> <DIRECTION>RIGHT</DIRECTION> <POLARITY>NORMAL</POLARITY>

25 Block Diagram: Networking

26 Detailed Block Diagram

27 System Overview PC-PIC and PIC-PIC communication is done via 9600Kbs MasterPIC: Receives packets from PC, distributes rail info to SlavePICs Controls Switching Polls sensors, and sends back packets to PC SlavePIC Powers rails via PWM

28 MasterPIC Functionality Sends initial byte with station number Receives packets from PC on interrupt basis. If there was error, sends back error byte Distributes rail info to 3 SlavePICs Sensors are polled every 1msec. If a sensor became active, packet is sent to MasterPC. If error byte is sent, sends back last sensor packet again MasterPIC keeps a queue for switch control

29 PC-to-PIC Packet Structure Switch Byte Rail Bytes CRC SW0-7 R8 R7 R6 R5 R4 R3 R2 R1 R0 1 Byte 1 Byte 9 Bytes Switch Byte Structure Rail Byte Structure X EM STOP <-Polarity-> ( ) < Speed > (0-F) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 11bytes

30 Block Diagram: Networking PIC-to-PC Sensor Packet Structure Sensor Bytes CRC 15 S S 14 S 14 S 13 S 13 S 12 S 12 S 11 S 11 S 10 S 10 S 9 S 8 S 2 S 7 S 6 S 5 S 4 S 3 1byte 1byte 1byte PIC-to-PC Station Number & Error Byte S 1 1Bit S 0 3bytes

31 PIC-to-PC Station/Error Byte PIC-to-PC Station Packet CRC X X X X X <-----Station-----> Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PC-PIC Error Byte < ERROR > Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

32 Timer 1 Timer 2 Switch Queue 2 timers with 2-task deep queues When packet arrives, switching task is placed in the first empty queue If both queues are busy, task is added to any queue When timer counts 5.6msec, it moves to next available task Each task is simply the switch byte containing relevant info

33 PIC-to-PIC Communication PIC-to-PIC uses RS-232 on single wire ether Each PIC has a unique ID PIC-to-PIC packet has address bytes Packets are received on interrupt basis If there s collision, PIC waits for 16msec, and sends again

34 PIC-to-PIC Packet Structure Standard Packet Structure Rail Bytes Preliminary Bytes CRC R2 R1 R0 Length FROM TO 1 Byte 3 Bytes 3 Bytes Error Packet Structure CRC ERROR Length FROM TO 1 Byte 1 Byte 3 Bytes 5bytes 7bytes

35 SlavePIC Functionality Receives packets from MasterPIC on interrupt basis. If there was error, sends back error byte Creates 3 PWM signals with unique duty cycles Outputs 2 polarity signals per PWM Duty cycle ranges from 36% - 96% Speed changes are implemented gradually via 3 timers for each PWM signal

36 Block Diagram: Low Level Low-Level A/C D/C Converter 0V / 5V Sensors 5V 5V To PICs Switches 18V H-Bridge Switch C. Power Board 0V / 22V 0V / 22V PWM (18V) PWM (18V) Rails 22V Four Major Components: Power conversion / Distribution Sensor / Train Proximity Monitoring system Rail Switching system Rail Power / Speed Control System All Components will occur at all five stations Sensor C.

37 Block Diagram: Low Level Power Conversion / Distribution 120V AC, 60 Hz signal from a wall outlet will be transformed to 24V DC / 1A DC voltage changed into four sources (22V, 18V, and two 5V sources) using a voltage regulator chip

38 Block Diagram: Low Level Sensor / Train Proximity Monitoring Sends TTL level voltages to the PIC indicating if the train is near the sensor or not Runs off a 5V DC source One full circuit contains nine (9) reed switches Sends a logic High when no train is neat the sensor, and a logic Low when a train is present

39 Block Diagram: Low Level Rail Switching In the figure here ground is represented by the input on the top, Vcc (22V DC) is on the bottom This circuit will discharge across the rail switch depending on which switch is closed. Only one switch can be closed at a time The switch is actually a transistor (NTE196). This device will turns on and off when the PIC tells it to do so (sends a designated voltage)

40 Block Diagram: Low Level Rail Power / Speed Control Pulse Width Modulated (PWM) and polarity signal input from the PIC The chip amplifies this signal to the amplitude of pin 8 and 16 (18V in this case) Outputs go to rails and power the trains LEDs will be utilized as visual feed back to see which rails are being powered

41 Draft Acceptance Test Plan Technical Requirements R001: Rail Switch Control - Test by visual inspection Switch must throw track majority of the way across to the other side R002: Engine Power Control - Test GUI by visual inspection Correct operation of 16 speeds and power to selected tracks No speed variation over track segments Over current circuit R003: Train Proximity Monitoring - Test by visual inspection and analysis R004: Expandability/ Adaptability - Test by visual inspection and analysis Multiple trains, documentation for expandability R005: Control and Monitoring Speed - Test by measurement and analysis Time delay must not affect performance R006: Application Programming Interface - Test by documentation Well commented code and API documentation R007: Maintenance User Interface - Test GUI through a qualified user User manual, manually control, visually monitor components R008: Demonstration Application - Test by having non-tech user use system User manual, user friendly easy to follow R009: Modification of the CFE - Test by visual inspection Supported by sub-system diagrams R010: Power Input - Test by visual inspection Sub-system diagrams

42 Draft Acceptance Test Plan General Project Requirements and Ethical Requirements GPR001: Documentation, GPR005: Safety and Good Practice - Tested throughout project process GPR002: Environmental, GPR003: EMI/EMC, GPR004: Hazmat - Visual inspection of components GPR006: Reliability - Analyze, inspect, measure to meet Reliability Requirements GPR007: Maintainability - Test by visual inspection and analysis Documented API, Sub-system diagrams and supplier availability GPR008: Sourcing Sustainability - Test by checking BOM available from 2 suppliers GPR009: Global Sustainability Test by life cycle assessment of 5 years All components RoHS compliant GPR010: Ethics Report Addressed by fully documented ethics report GPR011: Project Demonstration Test by Visual inspection Complete Final Project Presentation GPR012: Final Disposal of Projects Test by Visual inspection Correct labeling of components that are put in storage Sealed container, locked container ER001: Crashing Trains - Test by visual inspection and analysis ER002: Acceleration and Deceleration - Test by visual inspection and measurement

43 Questions?? Any questions??

44 Risk Assessment: UI Maintenance/Demo User Interface These interfaces are designed for the user to control all signals (speed and direction) that will be sent out to the stations. Methodology Maturity Methodology Complexity Software Maturity Software Complexity Dependency of Schedule on External Functional Groups Dependency of Performance on External Functional Groups Potential for Failure Factor = ( )/6 = Degradation of Technical/Operational Performance at System Level Schedule Impact Cost Impact Consequence for Failure Factor = ( )/3 = 0.4 Risk Factor: P+C (P*C) = (0.067 * 0.4) = low risk

45 Risk Assessment: UI Maintenance/Demo Control These control modules monitor the maintenance and demonstration operations to make sure the correct signals going out to the stations. Methodology Maturity Methodology Complexity Software Maturity Software Complexity Dependency of Schedule on External Functional Groups Dependency of Performance on External Functional Groups Potential for Failure Factor = ( )/6 = 0.23 Degradation of Technical/Operational Performance at System Level Schedule Impact Cost Impact Consequence for Failure Factor = ( )/3 = 0.33 Risk Factor: P+C (P*C) = (0.23 * 0.33) = medium risk

46 Risk Assessment: UI API The API is the underlying framework of the lower level methods that communicate between serial port and the PC. Methodology Maturity Methodology Complexity Software Maturity Software Complexity Dependency of Schedule on External Functional Groups Dependency of Performance on External Functional Groups Potential for Failure Factor = ( )/6 = 0.1 Degradation of Technical/Operational Performance at System Level Schedule Impact Cost Impact Consequence for Failure Factor = ( )/3 = 0.33 Risk Factor: P+C (P*C) = (0.1 * 0.33) = medium risk

47 Requirements Analysis: UI Requirements Maintenance Demonstration API R001 rail switch control R002 engine power control R003 train proximity monitoring R004 expandability and adaptability R005 control and monitoring speed R006 applications programming interface R007 maintenance user interface R008 demonstration application R009 modifications of the CFE layout R010 power input

48 Requirements Analysis: UI Requirements Maintenance Demonstration API GPR001 documentation GPR002 environmental GPR003 EMI/EMC GPR004 hazmats GPR005 safety and good practice GPR006 reliability GPR007 maintainability GPR008 sourcing sustainability GPR009 global sustainability GPR010 ethics report GPR011 project demonstration GPR012 final disposal of projects ER001 trains will not crash ER002 train acceleration

49 Test Procedures - UI Start at the lowest level and work up Test each class of the API individually Unit tests using JUnit framework Test BuilderDecoder using oscilloscope Test maintenance interface Change rail and switch values Use breakpoints in the code Use oscilloscope Write a test program and watch sensor display

50 Test Procedures UI Test demo app using a test program to simulate changing sensors Test control logic using printouts, breakpoints, or oscilloscope Integration Test communication with PICs send and receive packets Test maintenance interface with the whole system allows us to test every component Test control logic of the demo app on the whole system

51 Cost Analysis: UI Direct Costs Octopus ~ $125 Indirect Costs Labor ~ $1200 Computers ~ $4500 Total Costs ~ $5800

52 Gradual Speed Change Each PWM/Rail pair has a dedicated 16-bit timer Once a change in speed is received, timer is started to count until a designated time is reached (i.e 1msec) When time is reached, timer overflows, creates interrupt, and increments/decrements current duty cycle by 1% This goes on until current duty cycle reaches desired duty cycle Desired Duty Cycle Diff. Timer X Current Duty Cycle

53 Visual Feedback UI/Controller Group has GUI Networking Group has LEDs on TxD & RxD of PIC-PC and on ether of PIC-to-PIC Low-Level Group has LEDs on PWM outputs of the H- Bridge

54 Requirements Analysis: Networking

55 Requirements Analysis: Networking

56 Networking Board Layout

57 Networking Board Layout N9 I0 N5 N6 (PIC2 PIC) 1K 5V I0

58 Networking Board Layout GND N6 PIC Board LED Circuit N8 N3,N4,N5 PIC to RS232 N6 Communication Board I4 LED-X Circuit N10 GND GND 5V 1K (ohm) PIC Board Master reset (Push Button) N9 MRC (N1,N2, N3, N4)

59 Test Procedures: Low level Speed Control (H-bridge) Testing - Test for the desired PWM output with DC power supplies and function generator without the integration with the PIC. - Test the same output via integration with the PIC. Power Circuit Testing - Test for the desired output voltage by varying the resistance in a output resistor. Switching Circuit Testing - Test via simulation in PSpice. Sensor Circuit Testing - Test by checking the output voltage in the oscilloscope. - Test by integrating with the PIC.

60 Requirements Analysis: Low-Level

61 Risk Analysis: Low Level Overall System Power Methodology Maturity Methodology Complexity Hardware Maturity Hardware Complexity Dependency of Schedule on External Functional Groups Dependency of Performance on External Functional Groups Degradation of Technical/Operational Performance at System Level Schedule Impact Cost Impact Risk Factor = (Medium Risk)

62 Risk Analysis: Low Level Rail Power Methodology Maturity Methodology Complexity Hardware Maturity Hardware Complexity Dependency of Schedule on External Functional Groups Dependency of Performance on External Functional Groups Degradation of Technical/Operational Performance at System Level Schedule Impact Cost Impact Risk Factor = (Medium Risk)

63 Risk Analysis: Low Level Rail Switching Methodology Maturity Methodology Complexity Hardware Maturity Hardware Complexity Dependency of Schedule on External Functional Groups Dependency of Performance on External Functional Groups Degradation of Technical/Operational Performance at System Level Schedule Impact Cost Impact Risk Factor = (Medium Risk)

64 Risk Analysis: Low Level Sensors Methodology Maturity Methodology Complexity Hardware Maturity Hardware Complexity Dependency of Schedule on External Functional Groups Dependency of Performance on External Functional Groups Degradation of Technical/Operational Performance at System Level Schedule Impact Cost Impact Risk Factor = (Medium Risk)

65 Cost Analysis: Low Level Direct Costs: PCBs (5), Power elements, Other components Total direct costs: $1, Indirect Costs: Labor, computers, prototyping boards and software for testing Total indirect costs: $9, Total Costs for project: $7,669.00