Generic optimization for SMPS design with Smart Scan and Genetic Algorithm
|
|
- Garey McCormick
- 5 years ago
- Views:
Transcription
1 Generic optimization for SMPS design with Smart Scan and Genetic Algorithm H. Yeung *, N. K. Poon * and Stephen L. Lai * * PowerELab Limited, Hong Kong, HKSAR Abstract the paper presents a new approach for generating optimized solutions of a Switched-Mode Power Supply with the higher efficiency. At the very beginning, we initialize a preliminary power supply design with a known topology (e.g. Fly-back). Then, we choose a set of alternative parts for some critical components such as the MOSFET and transformer. It is quite a complicated and time consuming task to obtain a design with the highest efficiency and lowest cost from numerous combinations. Multi-objective Genetic Algorithm is one generic solution to solve such optimization problems. In order to encode the electrical parts as the basic units of GA, the chromosomes, and evaluate them with a numerical function, we have to model an entire power supply circuits into a Component-based System and simulate the electrical reactions by the numerical characteristics of components. This approach not only reduces the time in the design stage but provide a more convincing design before the production. The experiment results are presented to show the robustness and the effectiveness of this approach. Keywords- Genetic Algorithm; Power supply optimization; Component based system; I. INTRODUCTION In the design stage of Switched-Mode Power Supply (SMPS), the engineers use their expert knowledge and experience to draft the power supply prototype, fabricate a sample and examine its efficiency on different aspects such as power dissipation. To refine the performance and adjust the cost, they usually change the parts at some critical nodes. These steps are reiterated until the product meets certain criteria and it may consume weeks or even months. It is no doubt that these steps are unavoidable to ensure the higher quality and the lower cost of the power supply. Indeed, the procedures themselves may not be definitely completed by manipulation. We generally classify this kind of problem searching for the best one from a set of combinations as a Discrete Optimization Problem. A. Techniques for solving Discrete Optimization Problem The following is a typical Discrete Optimization a Infineon provides the Evaluation Design circuit in our experiment Problem (DOP). Some boxes are put in the fixed size container. The size of boxes is varying and there is a set of positioning and placement combinations for those boxes. There must be at least one solution that most boxes fit in the containers. There are some well-known techniques to solve the DOP. Full Search, or try-an-error, is the most reliable method to obtain the solution. All combinations are evaluated with a fitness function and the one with the highest score is the best solution. Most industrial processes will apply this technique if the optimization task is too complicated to be analyzed. However, this method is very expensive and time-consuming if the number of combinations is too large. There are some other methods to tackle DOP likes Binary Search and Nearest Neighbor Search. Despite the exponential reduction in the number of evaluation for combinations by these methods, it is still difficult to appraise the resource for optimization. With limited resource, some evolutionary computing techniques such as Genetic Algorithm (GA) [4] and Particle Swarm Optimization (PSO) [6] are proposed. They are based on the evolutional algorithm to find the solution approximating to the best one at assigned resources. Even though the solution is not always the best as Full Search does, it is not far away from that. Most important thing is that we can control the resources (e.g. the size of pool and the number of generations) to achieve different effectiveness of optimization. There are some previous works applying GA for solving optimization problems in SMPS. Reference [1] employs GA for synthesizing low power circuits. GA is applied to search the optimal commitment of thermal units in power generation in [3]. A research conducted in [5] generates the pattern of high power supply noise to estimate the maximum power supply noise of chip. Moreover, there are some works on finding the best circuit configuration in power supply controller evaluated with transfer function, as in [7]. B. Outlines In this paper, we propose using a Component-based System (CBS) accompanied with Genetic Algorithm (GA) to optimize a power supply from different combinations of the real components for higher efficiency. In the section II, the idea of GA solving Discrete Optimization Problem is overviewed. Then, the CBS of power supply in online power supply design software, PowerESim, is
2 introduced for preparing candidates in the optimization in the section III. In section IV, the fitness function to evaluate the efficiency of the modeled power supply is presented. Finally, the successful rate to obtain the efficient power supply is demonstrated in the experiment results in section V. II. GENETIC ALGORITHM A. Operations of GA Assume an optimization problem contains at least one solution and the searching space is finite. Then, Genetic Algorithm (GA) [4] is able to locate the optimal solutions within the searching space. The basic unit of GA is chromosome or candidate. They are parameterized as a list of numbers which are the features representing the chromosome. In the optimization problems, there are some parameters to be optimized and a set of parameters forms one candidate. A few candidates are generated randomly and put in a pool. They are evaluated with the fitness function, or cost function. The fittest group of candidates always survives in the pool and they are mated as the parents for next generation. These parents form some pairs and born the offspring by the crossover and mutation operation [4]. The better candidates, supposedly, are evolved from the competitions among the candidates in last generation. After several generations, the combinations remained are the elites and the final solution is the best inside the pool. B. Multi-objective GA For multi-objective optimization problems, we need multi-objective GA to solve it. For instance, we have to evaluate the efficiency, the unit price of product and the stress at extreme conditions while designing a SMPS. These evaluations are conflict to each other and no solution with the highest scores at all criteria can be achieved. In order to fit all the criteria, we can record the more than one high score candidates for each evaluations and the one with the highest average score for those criteria. User can select one of them to be the final solution. In this paper, we are going to evaluate the efficiency of SMPS ONLY such that it does not complicate the idea we proposed. III. COMPONENT BASED SYSTEM OF SMPS A. Definition of Component-based system Component-based system (CBS) [2] is a widely used approach for computerizing the industrial processes into the software. In general, any process with the descriptive participants, the procedural actions and the measurable values can be implemented as a CBS. SMPS is obvious a CBS. The components are the physical parts like resistors, capacitors and transformers. Their connections lead the electrical response from the input source and each component participates in its position. The current and voltage across the components are measurable by the meters. In our experiment, a well-developed software, called PowerESim, which is a power supply simulator built as a CBS is applied as the testing platform. Initially, user selects a converter topology and provides the specification (e.g. the range of input voltage, expected output voltage and current output current) from the interface. Then, the software provides the basic design which just fulfilled the specification and simulates the entire power dissipation at one operational cycle 1/fs where fs is the switching frequency of power supply in several milliseconds. B. Modeling component from real parts To model a real part to be a component in the software, the essential characteristics of a particular component should be defined. Use MOSFET as an example. The characteristics of the MOSFET are modeled in the software according to the specifications are shown as following. Thousands of modeled components are stored as table entries in the database. User can modify the components inside the converter, T1 controller Rrcd1 and feedback circuits. INPUT TABLE I. MODELING CHARACTERISTICS OF MOSFET Rrc_M1 Characteristics Max. Drain to Source Voltage V DSS Max. Gate to Source Voltage V GS 20V Max. Continuous Figure Drain 3. Current Circuit I diagram of the Fly-back topology D 7.3A Figure 2. Typical Capacitance Vs. Drain to Source Voltage caption is centered in the column With a known converter topology, the power dissipation of every individual part can be estimated according to their modeled characteristics. Power dissipation of the main primary MOSFET in the Fly-back converter is defined as the integration of voltage current within duration of 1/fs (1) in the software. The software provides a multiple selection interface of components whereas M1 Values 730V Max. Pulsed Drain Current I DM 21.9A Max. Pulsed Avalanche Rating E AS Max. Power Dissipation P D Max. Operating Temperature T J Typical Gate to Source Threshold Voltage V GS Max. Total Gate Charge Q g(tot) Max. Body Diode Reverse Recovery Timet rr 230mJ 83W 150 o C 3V 21nC 400ns Do1 O/P
3 users can select the alternatives as the parameters for optimization. LossM 1 1/ fs V Idt (1) 0 = C. Modeling the transformer Transformer takes a very important role in a SMPS. The main difference between transformer and other parts is that transformer constituted by the sub-parts such as magnetic core, the magnetic wires, the bobbin etc. Different arrangements (e.g. number of turns and number of parallel wires) of those sub-parts directly affect its behavior and performance. Formerly, it is not easy to model and simulate such complicated structure in component-based system. The proposed software has developed a subtle tool called Magnetic Builder providing a construction interface and simulator of the magnetic characteristics and power dissipation in a well-formed transformer. To find the best construction of transformer, we need to select multiple cores, wires and number of turns at particular winding. The number of turns in winding is quantized as a set of step values. For optimization, there are several combinations of transformer are generated by the crossover of all those alternative parameters. D. The effective index of power supply Efficiency is always the most important measurement for a power supply. In the software, the efficiency simulated is the Effective index defined as (2) where Po total is the total output power and Pd total is the total power dissipation. This becomes the fitness function for the optimization where the higher value induces higher efficiency and the maximum value is 1. Pototal Effective _ index = Pd + Po IV. total EXPERIMENT RESULTS A. Using concurrent converter topology We choose an Evaluation Design of a power supply using Fly-back topology in the software. The input voltage range is V. The expected one output voltage is 16 V and current output current is 3.75 A. The circuit diagram is shown as Figure 3. The initial Effective Index of the design is There are some critical nodes in the converter have been selected as the parameters for optimization in Table II. total (2) B. Prepare the first pool by Smart Scan Algorithm Any parts containing only one alternative will not be considered as the parameters for optimization so to reduce the complexity. The chromosome is designed as Figure 4. The chromosomes in the first pool are generally selecting from the combination of alternatives randomly. If the maximum number of executed evaluation function, Iteration allowed, is small, some alternatives might be eliminated and never participate in the optimizing space. Hence, the best combination is not guaranteed in the pool. In the power supply design, some dominating alternatives lead to high efficiency no matter what other parameters are. With this feature, an election method is proposed called Smart Scan to form the first pool intellectually as the procedures below. Index (i) TABLE II. THE COMPONENTS FOR OPTIMIZATION Part no. Description 0 Rrcd1 RCD Clamper resistor 1 M1 Primary Main MOSFET 2 Rrc_M1 Slobber resistor 3 Do2 Output Diode Number of alternatives (ksel i ) 4 T1 Main 12 (4 cores and 3 Rrcd1 0 M1 0 Rrc_M1 Transformer 0 Do2 number 0 of T1 turns 0 at Figure 4. The first chromosome selecting the primary first alternative windings) of each parameter i. One of the parameters is randomly selected for the dominating scan, e.g. Rrcd1. Other parameters are restricted to be the one randomly selected from their list of alternatives. One chromosome is formed certainly by the first alterative of Rrcd1 and the fixed alternatives of other parameters. ii. The chromosome is evaluated by the fitness function and both the score and the chromosome are pushed into the empty and fixed size pool. iii. Another alternative for Rrcd1 is chosen to form the second chromosome. It is evaluated again and pushed into the pool. When all alternatives of Rrcd1 are examined, one round of scan is finished
4 iv. The alternative of Rrcd1 in the chromosome with highest score is the dominated alternative. The second round of scan starts for other parameter, e.g. M1. The alternative of Rrcd1 in the chromosome is always set to the dominating one and others remain unchanged. v. If the pool is getting full, the chromosome with lowest score is popped up to reserve space for the better one. Finally, a pool is filled by the strong chromosomes. vi. Repeat the scan until the dominating alternatives of all the parameters are found. This election method ensures the chromosomes are strong enough to generate better offspring. However, it requires some of evaluating iterations during the election. The number of fitness function executed is calculated by (3) where N is number of parameters. If the Iteration scan is more or equal to the upper limit of iterations Iteration allowed set by user, some of alternatives may be eliminated until it is within the limitation. N 1 Iterationscan = ksel N N i= 0 C. Genetic Algorithm i ( 1) (3) After electing the pool, the chromosomes are automatically copied to the pool for next generation. The pairs of chromosomes are randomly selected from the first pool for Crossover and Mutation to generate the children. Crossover operation of the chromosomes exchanges the combination of alternatives from one to another and Mutation modifies one alternative of one parameter in the chromosome randomly. The probability of the mutation occurs for each crossover operation is 0.2. If the child is better than one in the second pool, the worst one is popped up and the new one is pushed to the pool. Otherwise, it is eliminated. This method guarantees the best throughout the generation must survive in the pool. Then the third pool is duplicated from the second pool. The optimization is terminated when the maximum number of generation is finished. N generation ( Iteration Iteration ) allowed scan = trunc 2 N pair (4) Iteration = Iteration + 2 N N (5) total Scan generation pair The number of generations in GA allowed is estimated by (4) given that Iteration allowed is set by user. The pool size (N pool ) is 50 and the number of parent pairs (no duplication) selected from the pool (N pair ) is 50. Then, the total number of iterations actually is Iteration total found by (5). In the case N generation is 0, this means the limited iterations does not allow the GA operations and the best in the first pool becomes the final solution. Figure 5 depicts the flowchart of the proposed optimization process. Get all alternatives Rrcd1 M1 Rrc_M1 Do2 T1 Smart Scan Form the Pool A Rrcd10 M1 2 Rrc_M10 Do23 T10 Rrcd10 M1 3 Rrc_M10 Do24 T15 Npoo l Rrcd13 M1 9 Rrc_M11 Do28 T110 Copy Pool A to Pool B Choose Npair pairs from Pool B and undergo Crossover and Mutation Evaluate the fitness of generated children Yes Start End Rank the Pool A and get the one with the highest score Rrcd10 M13 Rrc_M10 Do24 T15 No No. of generation < Ngeneration insert them into Pool A if their scores are higher than anyone in Pool A. Pop-up the worst to remain the Pool size Figure 5. The flowchart of GA optimization D. Summaries The experimental result of Full search is the baseline of the optimization performance. It finds the highest and the lowest Effective Index from all combinations shown as Table III. Indeed, the total number of evaluations required in Full search is the total combination of all parameters calculated by (6) where ksel i is number of alternatives at i th parameter defined in Table II. Ncomp 1 Total combination = ksel (6) i = 0 We have repeated the Smart Scan and GA optimization with different Iteration allowed from 100 to 400 and each test is repeated for 20 times. The results are summarized at the Table IV. The tests with 300 and 400 Iteration allowed complete at least one GA round. Both of them find the best combination perfectly in all tests. When Iteration allowed is 200, it is resulted from Smart Scan only. The successful rate to get the best solution is 95% and the average highest 6 effective index is 6 10 less that the highest Effective index. It induces that one of test cannot achieve the highest score but it is very close to the best one. TABLE III. THE EXPERIMENT RESULT FROM FULL SEARCH The no. of iterations run Highest Effective Index Lowest Effective Index i
5 TABLE IV. THE EXPERIMENT RESULT FROM GA OPTIMIZATION AND SMART SCAN Iteration allowed The no. of iterations run Average Highest Effective index N generation Number of alternatives are eliminated Successful rate to find the best combination % % % % % After reducing Iteration allowed to 150 and 100, some of alternatives are eliminated in the pool. 4 of alternatives are removed randomly for 150 iterations and 14 of that are removed for 100 iterations. Only 85% and 70% of tests can found the best combination in these two cases respectively. Nonetheless, the average best score results are still approximate to the highest score of all combination. To conclude, the number of the iterations of Full search is about 26 times more than that of the guarantee optimization with GA and Smart Scan proposed. V. CONCLUSIONS Achieving the high efficient converter is considered in every SMPS design. Engineers conventionally choose the alternatives and put it in a real power supply. Its efficiency is estimated by the thermal analysis in an enclosed environment. These steps are repeated until the expected efficiency is obtained. However, these procedures are expensive and time-consuming. With using the proposed method, the simulated power supply optimization is optimized by the Smart Scan of the real components modeled in the software, which parameterizes the entire power supply into a CBS and estimates the efficiency in seconds, and Genetic Algorithm. There are several extensions to this work. First, the power losses, thermal effects and stress are evaluated at the same time by a multi-objective Smart Scan and GA optimizer. Second, this approach is also applicable in design the controller and feedback compensator like [7]. The differences are the real components are selected to form the circuit and it is estimated by the expected cut-off frequency and expected phase margin behaved in the power supply. ACKNOWLEDGMENT This project has been implemented as the Smart optimizer in PowerESim developed by PowerELab Limited. REFERENCES [1] T. Arslan, E. Ozdemir, M. S. Bridge, and D. H. Horrocks, Generic Synthesis Techniques for Low-Power Digital Signal Processing Circuits, Proc. Of the IEE Colloquium On Digital Synthesis, pp 7/1 7/5, February [2] I. Crnkovic, J. A. Stafford, and H. W. Schmidt, Component-based Software Engineering, Springer-Verlag Berlin Heidelberg, [3] D. Dasgupta, and D. R. McGregor, Short Term Unit Commitment Using Genetic Algorithms, Technical Report, IKBS-16-93, August [4] D. E. Goldberg, Genetic Algorithms, Addison Wesley, [5] Y. M. Jiang, and K. T. Cheng, Vector Generation for Power Supply Noise Estimation and Verification of Deep Submicron Designs, IEEE Trans. VLSI Syst., 9(2), pp , April [6] J. Kennedy, and R. C. Eberhart, Particle swarm optimization, Proceedings of the 1995 IEEE International Conference on Neural Networks (Perth, Australia), pp , [7] A. Maiden, A. Purvis, and M. Kinghorn, The Development of a Digital Switched-Mode Power Supply Controller and Controller Design Tool, Proc. International Signal Processing Conference, Dallas, Texas, March [8] D. Whitley, A genetic algorithm tutorial, Statistics and Computing, vol. 4, pp , 1994.
Intrinsic Evolution of Analog Circuits on a Programmable Analog Multiplexer Array
Intrinsic Evolution of Analog Circuits on a Programmable Analog Multiplexer Array José Franco M. Amaral 1, Jorge Luís M. Amaral 1, Cristina C. Santini 2, Marco A.C. Pacheco 2, Ricardo Tanscheit 2, and
More informationHARMONIC REDUCTION IN CASCADED MULTILEVEL INVERTER WITH REDUCED NUMBER OF SWITCHES USING GENETIC ALGORITHMS
HARMONIC REDUCTION IN CASCADED MULTILEVEL INVERTER WITH REDUCED NUMBER OF SWITCHES USING GENETIC ALGORITHMS C. Udhaya Shankar 1, J.Thamizharasi 1, Rani Thottungal 1, N. Nithyadevi 2 1 Department of EEE,
More informationWire Layer Geometry Optimization using Stochastic Wire Sampling
Wire Layer Geometry Optimization using Stochastic Wire Sampling Raymond A. Wildman*, Joshua I. Kramer, Daniel S. Weile, and Philip Christie Department University of Delaware Introduction Is it possible
More informationEvolution of Sensor Suites for Complex Environments
Evolution of Sensor Suites for Complex Environments Annie S. Wu, Ayse S. Yilmaz, and John C. Sciortino, Jr. Abstract We present a genetic algorithm (GA) based decision tool for the design and configuration
More informationReduction of crosstalk on printed circuit board using genetic algorithm in switching power supply
Title Reduction of crosstalk on printed circuit board using genetic algorithm in switching power supply Author(s) Pong, MH; Wu, X; Lee, CM; Qian, Z Citation Ieee Transactions On Industrial Electronics,
More informationSmart Grid Reconfiguration Using Genetic Algorithm and NSGA-II
Smart Grid Reconfiguration Using Genetic Algorithm and NSGA-II 1 * Sangeeta Jagdish Gurjar, 2 Urvish Mewada, 3 * Parita Vinodbhai Desai 1 Department of Electrical Engineering, AIT, Gujarat Technical University,
More informationThe Genetic Algorithm
The Genetic Algorithm The Genetic Algorithm, (GA) is finding increasing applications in electromagnetics including antenna design. In this lesson we will learn about some of these techniques so you are
More informationSMK0460IS Advanced N-Ch Power MOSFET
Advanced N-Ch Power MOSFET SWITCHING REGULATOR APPLICATION Features Drain-Source breakdown voltage: BV DSS =600V (Min.) Low gate charge: Q g =12nC (Typ.) Low drain-source On resistance: R DS(on) =2.1Ω
More informationN-Channel 0 V (D-S) MOSFET
N-Channel V (D-S) MOSFET 66SJ PRODUCT SUMMARY V DS (V) R DS(on) () I D (A) a, e Q g (Typ.).6 at V GS = V 53 4 nc.9 at V GS = 4.5 V 4 FEATURES TrenchFET II Power MOSFET % R g and UIS Tested APPLICATIONS
More informationSLD8N6 65S / SLU8N65 5S
SLD8N65S / SLU8N65S 650V N-Channel MOSFET General Description This Power MOSFET is produced using Maple semi s advanced planar stripe DMOS technology. This advanced technology has been especially tailored
More informationSMN630LD Logic Level N-Ch Power MOSFET
Logic Level N-Ch Power MOSFET 200V LOGIC N-Channel MOSFET Features Drain-Source breakdown voltage: BV DSS =200V (Min.) Low gate charge: Q g =12nC (Typ.) Low drain-source On-Resistance: R DS(on) =0.34Ω
More informationSMK1360FD Advanced N-Ch Power MOSFET
Advanced N-Ch Power MOSFET SWITCHING REGULATOR APPLICATION Features BV DDS =600V (Min.) Low gate charge: Q g =41nC (Typ.) Low drain-source On resistance: R DS(on) =0.65Ω (Max.) 100% avalanche tested RoHS
More informationN-Channel 100 V (D-S) MOSFET
N-Channel V (D-S) MOSFET PRODUCT SUMMARY V DS (V) R DS(on) () I D (A) a, e Q g (Typ.).88 at V GS = V 3 nc.95 at V GS =7.5 V DFN 3x3 EP Top View Bottom View Pin Top View FEATURES TrenchFET Power MOSFET
More informationDepartment of Mechanical Engineering, Khon Kaen University, THAILAND, 40002
366 KKU Res. J. 2012; 17(3) KKU Res. J. 2012; 17(3):366-374 http : //resjournal.kku.ac.th Multi Objective Evolutionary Algorithms for Pipe Network Design and Rehabilitation: Comparative Study on Large
More informationSMN01L20Q Logic Level N-Ch Power MOSFET
Logic Level N-Ch Power MOSFET 200V LOGIC N-Channel MOSFET Features 0.85A, 200V, R DS(on) =1.35Ω @ V GS =10V Low gate charge: Q g =4nC (Typ.) Fast switching 100% avalanche tested RoHS compliant device D
More informationFEATURES. Parameter Symbol Limit Unit Gate-Source Voltage V GS ± 20 V. 85 a Pulsed Drain Current I DM 600
DTU5N6 N-Channel 6 V (D-S) MOSFET PRODUCT SUMMARY V DS (V) R DS(on) ( ) I D (A) a.25 at V GS = V 5 6.5 at V GS = 4.5 V 75 FEATURES TrenchFET II Power MOSFET TO-252 D G D S Top View S N-Channel MOSFET ABSOLUTE
More informationFeatures. Information I-PAK G D S. Marking. Part Number. Package. I-PAK (Short Lead) SMK0160. Unit. V Gate-source voltage T c =25 C I D I DM
Features SWITCHING REGULATO OR APPLICATION Drain-Source breakdown voltage: BV DSS =600V (Min.) Low gate charge: Q g = 3.9nC (Typ.) Low drain-source On resistance: R DS(on) =11.5Ω (Max.) 100% avalanche
More informationSMK0990FD Advanced N-Ch Power MOSFET
z SMK0990FD Advanced N-Ch Power MOSFET SWITCHING REGULATOR APPLICATION Features Drain-Source breakdown voltage: BV DSS =900V Low gate charge: Q g =52nC (Typ.) Low drain-source On resistance: R DS(on) =1.4Ω
More informationSMPS MOSFET. V DSS Rds(on) max I D
Applications Switch Mode Power Supply ( SMPS ) Uninterruptable Power Supply High speed power switching Lead-Free Benefits Low Gate Charge Qg results in Simple Drive Requirement Improved Gate, Avalanche
More informationThe Behavior Evolving Model and Application of Virtual Robots
The Behavior Evolving Model and Application of Virtual Robots Suchul Hwang Kyungdal Cho V. Scott Gordon Inha Tech. College Inha Tech College CSUS, Sacramento 253 Yonghyundong Namku 253 Yonghyundong Namku
More informationI2-PAK G D S. T C = 25 C unless otherwise noted. Drain-Source Voltage 650 V. Symbol Parameter SLB10N65S SLI10N65S Units R θjc
SLB10N65S/ SLI10N65S 650V N-Channel MOSFET General Description This Power MOSFET is produced using Maple semi s advanced planar stripe DMOS technology. This advanced technology has been especially tailored
More informationImplementation of FPGA based Decision Making Engine and Genetic Algorithm (GA) for Control of Wireless Parameters
Advances in Computational Sciences and Technology ISSN 0973-6107 Volume 11, Number 1 (2018) pp. 15-21 Research India Publications http://www.ripublication.com Implementation of FPGA based Decision Making
More informationHFI50N06A / HFW50N06A 60V N-Channel MOSFET
HFI50N06A / HFW50N06A 60V N-Channel MOSFET Features Superior Avalanche Rugged Technology Robust Gate Oxide Technology Very Low Intrinsic Capacitances Excellent Switching Characteristics 100% Avalanche
More informationAn Optimized Performance Amplifier
Electrical and Electronic Engineering 217, 7(3): 85-89 DOI: 1.5923/j.eee.21773.3 An Optimized Performance Amplifier Amir Ashtari Gargari *, Neginsadat Tabatabaei, Ghazal Mirzaei School of Electrical and
More informationIRFP460 N-CHANNEL 500V Ω A TO-247 PowerMesh II MOSFET
N-CHANNEL 500V - 0.22Ω - 18.4A TO-247 PowerMesh II MOSFET TYPE V DSS R DS(on) I D IRFP460 500V < 0.27Ω 18.4A TYPICAL R DS (on) = 0.22Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE
More informationSPECIFICATIONS (T J = 25 C, unless otherwise noted)
N-Channel V (D-S) MOSFET PRODUCT SUMMARY V DS (V) R DS(on) ( ) I D (A) a, e Q g (Typ.). at V GS = V at V GS = 4.5 V nc DFN 3x3 EP Top View Bottom View Pin Top View FEATURES APPLICATIONS D 3 4 8 7 5 G Pin
More informationDWINDLING OF HARMONICS IN CML INVERTER USING GENETIC ALGORITHM OPTIMIZATION
Volume 117 No. 16 2017, 757-76 ISSN: 1311-8080 (printed version); ISSN: 131-3395 (on-line version) url: http://www.ijpam.eu ijpam.eu DWINDLING OF HARMONICS IN CML INVERTER USING GENETIC ALGORITHM OPTIMIZATION
More informationEvolutionary Image Enhancement for Impulsive Noise Reduction
Evolutionary Image Enhancement for Impulsive Noise Reduction Ung-Keun Cho, Jin-Hyuk Hong, and Sung-Bae Cho Dept. of Computer Science, Yonsei University Biometrics Engineering Research Center 134 Sinchon-dong,
More informationA Genetic Algorithm for Solving Beehive Hidato Puzzles
A Genetic Algorithm for Solving Beehive Hidato Puzzles Matheus Müller Pereira da Silva and Camila Silva de Magalhães Universidade Federal do Rio de Janeiro - UFRJ, Campus Xerém, Duque de Caxias, RJ 25245-390,
More informationFeatures. Information SOT-223. Part Number. Marking. Package SOT-223 SNN01Z60. Unit. V Gate-source voltage A A I DM T c =25 C I D.
Logic Level Gate Drive Application SNN01Z60Q Logic Level N-Ch Power MOSFET Features Logic levell gate drive Max. R DS(ON N) = 135mΩ at V GS = 10V, I D = 0.5A Low R DS(on) provides higher efficiency ESD
More informationA Novel approach for Optimizing Cross Layer among Physical Layer and MAC Layer of Infrastructure Based Wireless Network using Genetic Algorithm
A Novel approach for Optimizing Cross Layer among Physical Layer and MAC Layer of Infrastructure Based Wireless Network using Genetic Algorithm Vinay Verma, Savita Shiwani Abstract Cross-layer awareness
More informationIRF130, IRF131, IRF132, IRF133
October 1997 SEMICONDUCTOR IRF13, IRF131, IRF132, IRF133 12A and 14A, 8V and 1V,.16 and.23 Ohm, N-Channel Power MOSFETs Features Description 12A and 14A, 8V and 1V r DS(ON) =.16Ω and.23ω Single Pulse Avalanche
More informationObsolete Product(s) - Obsolete Product(s)
N-CHANNEL 100V - 0.009 Ω - 140A MAX247 MESH OVERLAY POWER MOSFET STY140NS10 100V
More informationLow Power High Performance 10T Full Adder for Low Voltage CMOS Technology Using Dual Threshold Voltage
Low Power High Performance 10T Full Adder for Low Voltage CMOS Technology Using Dual Threshold Voltage Surbhi Kushwah 1, Shipra Mishra 2 1 M.Tech. VLSI Design, NITM College Gwalior M.P. India 474001 2
More informationUNISONIC TECHNOLOGIES CO., LTD UTT150N03 Preliminary Power MOSFET
UNISONIC TECHNOLOGIES CO., LTD UTT150N03 Preliminary Power MOSFET N-CHANNEL ENHANCEMENT MODE POWER MOSFET DESCRIPTION The UTC UTT150N03 is a N-channel power MOSFET, using UTC s advanced trench technology
More informationThe Application of Multi-Level Genetic Algorithms in Assembly Planning
Volume 17, Number 4 - August 2001 to October 2001 The Application of Multi-Level Genetic Algorithms in Assembly Planning By Dr. Shana Shiang-Fong Smith (Shiang-Fong Chen) and Mr. Yong-Jin Liu KEYWORD SEARCH
More informationDevice Marking Device Device Package Reel Size Tape width Quantity 6075K FNK6075K TO-252-2L Parameter Symbol Limit Unit
FNK N-Channel Enhancement Mode Power MOSFET Description The FNK6075K uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. It can be used in a wide variety of applications.
More informationElectrical Characteristics (T A =25 unless otherwise noted) Off Characteristics Parameter Symbol Condition Min Typ Max Unit Drain-Source Breakdown Vol
N-Channel Enhancement Mode Power MOSFET Description The HM uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. It can be used in a wide variety of applications.
More informationSECTOR SYNTHESIS OF ANTENNA ARRAY USING GENETIC ALGORITHM
2005-2008 JATIT. All rights reserved. SECTOR SYNTHESIS OF ANTENNA ARRAY USING GENETIC ALGORITHM 1 Abdelaziz A. Abdelaziz and 2 Hanan A. Kamal 1 Assoc. Prof., Department of Electrical Engineering, Faculty
More informationAvailable online at ScienceDirect. Procedia Computer Science 24 (2013 )
Available online at www.sciencedirect.com ScienceDirect Procedia Computer Science 24 (2013 ) 158 166 17th Asia Pacific Symposium on Intelligent and Evolutionary Systems, IES2013 The Automated Fault-Recovery
More informationAUTOMOTIVE GRADE. A I DM Pulsed Drain Current -44 P A = 25 C Maximum Power Dissipation 3.8 P C = 25 C Maximum Power Dissipation 110
Features Advanced Planar Technology Low On-Resistance P-Channel MOSFET Dynamic dv/dt Rating 175 C Operating Temperature Fast Switching Fully Avalanche Rated Repetitive Avalanche Allowed up to Tjmax Lead-Free,
More information3 Hints for application
i RG i G i M1 v E M1 v GE R 1 R Sense Figure 3.59 Short-circuit current limitation by reduction of gate-emitter voltage This protection technique limits the stationary short-circuit current to about three
More informationMDF11N60 N-Channel MOSFET 600V, 11 A, 0.55Ω
General Description MDF11N6 is suitable device for SMPS, high Speed switching and general purpose applications. MDF11N6 N-Channel MOSFET 6V, 11 A,.55Ω Features = 6V = 11A @ V GS = V R DS(ON).55Ω @ V GS
More informationSSF6014D 60V N-Channel MOSFET
Main Product Characteristics V DSS 60V R DS(on) 12mΩ(typ.) I D 60A Features and Benefits TO-252 (DPAK) Marki ng and P i n Assignment S c h e m a ti c Dia g r a m Advanced trench MOSFET process technology
More informationIRL5NJ V, P-CHANNEL LOGIC LEVEL POWER MOSFET SURFACE MOUNT (SMD-0.5) PD-94052C. Product Summary
PD-9452C IRL5NJ744 LOGIC LEVEL POWER MOSFET SURFACE MOUNT (SMD-.5) 2V, P-CHANNEL Product Summary Part Number BV DSS R DS(on) I D IRL5NJ744-2V.4 -A SMD-.5 Description IRL5NJ744 is part of the International
More informationIRFF230 JANTX2N6798 JANTXV2N6798
PD-90431E JANTX2N6798 JANTXV2N6798 REPETITIVE AVALANCHE AND dv/dt RATED HEXFET TRANSISTORS THRU-HOLE TO-205AF (TO-39) 200V, N-CHANNEL REF: MIL-PRF-19500/557 Product Summary Part Number BVDSS RDS(on) I
More informationPower MOSFET. PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 600 V Gate-Source Voltage V GS ± 30 T C = 25 C. V GS at 10 V
Power MOSFET PRODUCT SUMMARY V DS (V) 600 R DS(on) ( ) V GS = V 0.75 Q g (Max.) (nc) 49 Q gs (nc) 3 Q gd (nc) 20 Configuration Single G D 2 PAK (TO-263) D S Note a. See device orientation. G N-Channel
More informationMDF9N50 N-Channel MOSFET 500V, 9.0 A, 0.85Ω
General Description The MDF9N5 uses advanced MagnaChip s MOSFET Technology, which provides low on-state resistance, high switching performance and excellent quality. MDF9N5 is suitable device for SMPS,
More informationCOMPARATIVE ANALYSIS OF SELECTIVE HARMONIC ELIMINATION OF MULTILEVEL INVERTER USING GENETIC ALGORITHM
COMPARATIVE ANALYSIS OF SELECTIVE HARMONIC ELIMINATION OF MULTILEVEL INVERTER USING GENETIC ALGORITHM S.Saha 1, C.Sarkar 2, P.K. Saha 3 & G.K. Panda 4 1&2 PG Scholar, Department of Electrical Engineering,
More informationTaiwan Goodark Technology Co.,Ltd
TGD N-Channel Enhancement Mode Power MOSFET Description The uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. This device is suitable for use in PWM, load switching
More informationN-Channel 100-V (D-S) 175 C MOSFET
N-Channel -V (D-S) 75 C MOSFET SUD4N-25 PRODUCT SUMMARY V DS (V) R DS(on) (Ω) I D (A).25 at V GS = V 4.28 at V GS = 4.5 V 38 FEATURES TrenchFET Power MOSFET 75 C Maximum Junction Temperature % R g Tested
More informationHGI290N10SL. Value T C =25 31 Continuous Drain Current (Silicon Limited) I D T C = Drain to Source Voltage. Symbol V DS
, HGI29NSL P- Feature High Speed Power Switching, Logic Level Enhanced Body diode dv/dt capability Enhanced Avalanche Ruggedness % UIS Tested, % Rg Tested Lead Free, Halogen Free V N-Ch Power MOSFET V
More informationN-Channel Power MOSFET 600V, 11A, 0.38Ω
N-Channel Power MOSFET 600V, 11A, 0.38Ω FEATURES Super-Junction technology High performance due to small figure-of-merit High ruggedness performance High commutation performance Pb-free plating Compliant
More informationEvolutionary Optimization for the Channel Assignment Problem in Wireless Mobile Network
(649 -- 917) Evolutionary Optimization for the Channel Assignment Problem in Wireless Mobile Network Y.S. Chia, Z.W. Siew, S.S. Yang, H.T. Yew, K.T.K. Teo Modelling, Simulation and Computing Laboratory
More informationP- and N-Channel 4 V (D-S) MOSFET
P- and N-Channel 4 V (D-S) MOSFET PRODUCT SUMMARY V DS (V) R DS(on) ( ) I D (A) a Q g (Typ.) N-Channel 4. 6 at V GS = V 6.7.24 at V GS = 4.5 V 5.8 5. P-Channel -4. 2 at V GS = - V - 6..52 at V GS = - 4.5
More informationN-Channel 100-V (D-S) MOSFET
N-Channel -V (D-S) MOSFET 3 PRODUCT SUMMARY V (BR)DSS (V) r DS(on) ( ) I D (A). at V GS = V. at V GS = V 7.5 FEATURES TrenchFET Power MOSFETS 75 C Junction Temperature Low Thermal Resistance Package Available
More informationMDF7N60 N-Channel MOSFET 600V, 7 A, 1.1Ω
General Description MDF7N is suitable device for SMPS, high Speed switching and general purpose applications. MDF7N N-Channel MOSFET V, 7 A,.Ω Features = V = 7.A @ = V R DS(ON).Ω @ = V Applications Power
More informationFeatures. Applications. Table 1: Device summary Order code Marking Package Packing STWA70N60DM2 70N60DM2 TO-247 long leads Tube
N- Power MOSFET in a TO-247 long leads package Datasheet - production data Features Order code V DS R DS(on) max. I D P TOT STWA70N60DM2 600 V 66 A 446 W 3 2 1 TO-247 long leads Figure 1: Internal schematic
More informationComplementary N- and P-Channel 40-V (D-S) MOSFET
Complementary N- and P-Channel -V (D-S) MOSFET PRODUCT SUMMARY V DS (V) r DS(on) (Ω) I D (A) a Q g (Typ.) N-Channel.7 at V GS = V 8. at V GS =.5 V 8 2 P-Channel -. at V GS = - V - 8.5 at V GS = -.5 V -
More informationSMPS MOSFET. V DSS R DS(on) max I D
SMPS MOSFET PD - 9506A IRFR8N5DPbF IRFU8N5DPbF HEXFET Power MOSFET Applications High frequency DC-DC converters Lead-Free l l V DSS R DS(on) max I D 50V 0.25Ω 8A Benefits l Low Gate to Drain Charge to
More informationSTS7PF30L P-CHANNEL 30V Ω - 7ASO-8 STripFET II POWER MOSFET
TYPE V DSS R DS(on) I D STS7PF30L P-CHANNEL 30V - 0.016Ω - 7ASO-8 STripFET II POWER MOSFET PRELIMINARY DATA STS7PF30L 30 V < 0.021 Ω 7A TYPICAL R DS (on) = 0.016Ω STANDARD OUTLINE FOR EASY AUTOMATED SURFACE
More informationTSF18N60MR TSF18N60MR. 600V N-Channel MOSFET. Features. Absolute Maximum Ratings. Thermal Resistance Characteristics
600V N-Channel MOSFET General Description This Power MOSFET is produced using Truesemi s advanced planar stripe DMOS technology. This advanced technology has been especially tailored to minimize on-state
More informationTO-220 G. T C = 25 C unless otherwise noted. Drain-Source Voltage 80 V. Symbol Parameter MSP120N08G Units R θjc
MSP120N08G 80V N-Channel MOSFET General Description Features This Power MOSFET is produced using Maple semi s advanced technology. which provides high performance in on-state resistance, fast switching
More informationFNK N-Channel Enhancement Mode Power MOSFET
FNK N-Channel Enhancement Mode Power MOSFET Description The FNK 80H11 uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. It can be used in a wide variety of
More informationSMPS MOSFET. V DSS R DS(on) max I D
SMPS MOSFET PD 93917A IRFP3703 Applications Synchronous Rectification Active ORing l l HEXFET Power MOSFET V DSS R DS(on) max I D 30V 0.0028Ω 2A Benefits l Ultra Low OnResistance l Low Gate Impedance to
More informationUNISONIC TECHNOLOGIES CO., LTD 9N50 Preliminary Power MOSFET
UNISONIC TECHNOLOGIES CO., LTD 9N50 Preliminary Power MOSFET 9A, 500V N-CHANNEL POWER MOSFET DESCRIPTION The UTC 9N50 is an N-channel mode power MOSFET using UTC s advanced technology to provide customers
More informationLNTR4003NLT1G. Small Signal MOSFET. 30 V, 0.56 A, Single, N Channel, Gate ESD Protection, SOT-23 LESHAN RADIO COMPANY, LTD. 1/5. and halogen free.
Small Signal MOSFET V,.56 A, Single, N Channel, Gate ESD Protection, SOT- Features Low Gate Voltage Threshold(Vgs(th))to Facilitate Drive Circuit Design Low Gate Charge for Fast Switching ESD Protected
More informationUsing Genetic Algorithm in the Evolutionary Design of Sequential Logic Circuits
IJCSI International Journal of Computer Science Issues, Vol. 8, Issue, May 0 ISSN (Online): 694-084 www.ijcsi.org Using Genetic Algorithm in the Evolutionary Design of Sequential Logic Circuits Parisa
More informationN-Channel Power MOSFET 100V, 81A, 10mΩ
N-Channel Power MOSFET 100V, 81A, 10mΩ FEATURES Advanced Trench Technology 100% avalanche tested APPLICATION Synchronous Rectification in SMPS High Speed Power Switching KEY PERFORMANCE PARAMETERS PARAMETER
More informationAchieving Desirable Gameplay Objectives by Niched Evolution of Game Parameters
Achieving Desirable Gameplay Objectives by Niched Evolution of Game Parameters Scott Watson, Andrew Vardy, Wolfgang Banzhaf Department of Computer Science Memorial University of Newfoundland St John s.
More informationHCA60R080FT (Fast Recovery Diode Type) 600V N-Channel Super Junction MOSFET
HCA60R080FT (Fast Recovery Diode Type) 600V N-Channel Super Junction MOSFET Features Very Low FOM (R DS(on) X Q g ) Extremely low switching loss Excellent stability and uniformity 00% Avalanche Tested
More informationNTMS5838NL. Power MOSFET 40 V, 7.5 A, 20 m
Power MOSFET V, 7.5 A, 2 m Features Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise stated)
More informationMinimization of Power Loss and Improvement of Voltage Profile in a Distribution System Using Harmony Search Algorithm
Minimization of Power Loss and Improvement of Voltage Profile in a Distribution System Using Harmony Search Algorithm M. Madhavi 1, Sh. A. S. R Sekhar 2 1 PG Scholar, Department of Electrical and Electronics
More informationGENETICALLY DERIVED FILTER CIRCUITS USING PREFERRED VALUE COMPONENTS
GENETICALLY DERIVED FILTER CIRCUITS USING PREFERRED VALUE COMPONENTS D.H. Horrocks and Y.M.A. Khalifa Introduction In the realisation of discrete-component analogue electronic circuits it is common practice,
More informationOperating Junction and 55 to +175 C Storage Temperature Range
Feathers: dvanced trench process technology avalanche energy, 100% test Fully characterized avalanche voltage and current ID =60 BV=60V Rdson=14mΩ(max.) Description: The is a new generation of middle voltage
More informationDevice Marking Device Device Package Reel Size Tape width Quantity TO-252-2L. Parameter Symbol Limit Unit
HM80N05K N-Channel Enhancement Mode Power MOSFET Description The uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. It can be used in a wide variety of applications.
More informationUNISONIC TECHNOLOGIES CO., LTD UTT36N05 Preliminary Power MOSFET
UNISONIC TECHNOLOGIES CO., LTD UTT36N05 Preliminary Power MOSFET 36A, 50V N-CHANNEL ENHANCEMENT MODE POWER MOSFET TRANSISTOR DESCRIPTION The UTC UTT36N05 is an N-channel enhancement power MOSFET using
More informationPower MOSFET FEATURES. IRFIB6N60APbF SiHFIB6N60A-E3 IRFIB6N60A SiHFIB6N60A
Power MOSFET IRFIB6N60A, SiHFIB6N60A PRODUCT SUMMARY V DS (V) 600 R DS(on) (Ω) V GS = V 0.75 Q g (Max.) (nc) 49 Q gs (nc) 3 Q gd (nc) 20 Configuration Single TO-220 FULLPAK D G FEATURES Low Gate Charge
More informationUNISONIC TECHNOLOGIES CO., LTD
UNISONIC TECHNOLOGIES CO., LTD 6.5 Amps, 00 Volts N-CHANNEL POWER MOSFET DESCRIPTION The UTC 6N0 is an N-Channel enhancement mode power FET providing customers with excellent switching performance and
More informationUNISONIC TECHNOLOGIES CO., LTD 10N50 Preliminary Power MOSFET
UNISONIC TECHNOLOGIES CO., LTD 10N50 Preliminary Power MOSFET 10A, 500V N-CHANNEL POWER MOSFET DESCRIPTION 1 TO-220 The UTC 10N50 is an N-channel mode power MOSFET using UTC s advanced technology to provide
More information1 Electrical ratings Electrical characteristics Electrical characteristics (curves)... 6
N-channel 600 V, 0.094 Ω typ., 28 A MDmesh DM2 Power MOSFET in a TO-220 package Datasheet - production data Features Order code V DS R DS(on) max. I D P TOT STP35N60DM2 600 V 0.110 Ω 28 A 210 W Figure
More informationFault Location Using Sparse Wide Area Measurements
319 Study Committee B5 Colloquium October 19-24, 2009 Jeju Island, Korea Fault Location Using Sparse Wide Area Measurements KEZUNOVIC, M., DUTTA, P. (Texas A & M University, USA) Summary Transmission line
More informationSMPS MOSFET. V DSS R DS(on) max I D
Applications l l l l Switch Mode Power Supply (SMPS) Uninterruptible Power Supply High Speed Power Switching Lead-Free SMPS MOSFET PD - 9546 HEXFET Power MOSFET V DSS R DS(on) max I D 650V 0.93Ω 8.5A Benefits
More informationAUTOMOTIVE GRADE. Thermal Resistance Symbol Parameter Typ. Max. Units R JC Junction-to-Case 1.9 R JA Junction-to-Ambient ( PCB Mount) 50 C/W
Features Advanced Planar Technology P-Channel MOSFET Low On-Resistance Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Fully Avalanche Rated Repetitive Avalanche Allowed up to Tjmax Lead-Free,
More informationDevice Marking Device Device Package Reel Size Tape width Quantity NCE60P12K NCE60P12K TO-252-2L - - -
http://www.ncepower.com NCE P-Channel Enhancement Mode Power MOSFET Description The uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge.this device is well suited
More informationSMPS MOSFET. V DSS R DS(on) max (mω) I D
SMPS MOSFET PD- 94048 IRFR220N IRFU220N HEXFET Power MOSFET Applications l High frequency DC-DC converters V DSS R DS(on) max (mω) I D 200V 600 5.0A Benefits l Low Gate to Drain Charge to Reduce Switching
More informationFEATURES G D S. Parameter Symbol Limit Unit Gate-Source Voltage V GS ± 20 V I D T C = 100 C
N-Channel 6 V (D-S) Super Junction Power MOSFET DTP63SJ PRODUCT SUMMARY V DS (V) R DS(on) ( ) I D (A) a.35 at V GS = V 3 6.4 at V GS = 4.5 V FEATURES 75 C Junction Temperature TrenchFET II Power MOSFET
More informationT C =25 unless otherwise specified. Symbol Parameter Value Units V DSS Drain-Source Voltage 200 V V GS Gate-Source Voltage ± 30 V
200V N-Channel MOSFET General Description This Power MOSFET is produced using Truesemi s advanced planar stripe DMOS technology. This advanced technology has been especially tailored to minimize on-state
More informationObsolete Product(s) - Obsolete Product(s)
N-CHANNEL 550V @ Tjmax - 0.20Ω - 20ATO-247 MDmesh MOSFET TYPE STW20NM50 550V < 0.25Ω 20 A TYPICAL R DS (on) = 0.20Ω HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED LOW INPUT CAPACITANCE AND
More informationDesign Of PID Controller In Automatic Voltage Regulator (AVR) System Using PSO Technique
Design Of PID Controller In Automatic Voltage Regulator (AVR) System Using PSO Technique Vivek Kumar Bhatt 1, Dr. Sandeep Bhongade 2 1,2 Department of Electrical Engineering, S. G. S. Institute of Technology
More informationTSP13N 50M / TSF13N N50M
TSP13N50M / TSF13N50M 600V N-Channel MOSFET General Description This Power MOSFET is produced using True semi s advanced planar stripe DMOS technology. This advanced technology has been especially tailored
More informationN-Channel Power MOSFET 30V, 185A, 1.8mΩ
TSM8NA3CR N-Channel Power MOSFET 3V, 85A,.8mΩ FEATURES Low R DS(ON) to minimize conductive losses Low gate charge for fast power switching % UIS and R g tested Compliant to RoHS directive 2/65/EU and in
More informationNTTFS5116PLTWG. Power MOSFET 60 V, 20 A, 52 m. Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant
Power MOSFET 6 V, 2 A, 52 m Features Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant Applications Load Switches DC Motor Control DC DC Conversion MAXIMUM RATINGS ( unless otherwise
More informationEvolutions of communication
Evolutions of communication Alex Bell, Andrew Pace, and Raul Santos May 12, 2009 Abstract In this paper a experiment is presented in which two simulated robots evolved a form of communication to allow
More informationObsolete Product(s) - Obsolete Product(s)
N-CHANNEL 200V - 0.062 Ω - 34A TO-247 PowerMESH MOSFET Table 1. General Features Figure 1. Package Type V DSS R DS(on) I D STW34NB20 200 V < 0.075 Ω 34 A FEATURES SUMMARY TYPICAL R DS(on) = 0.062 Ω EXTREMELY
More informationAUTOMOTIVE GRADE. Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) 300
Features Advanced Process Technology Ultra Low On-Resistance 175 C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free, RoHS Compliant Automotive Qualified * AUTOMOTIVE
More informationN-Channel 150-V (D-S) MOSFET
N-Channel 5-V (D-S) MOSFET PRODUCT SUMMARY V (BR)DSS (V) R DS(on) (Ω) I D (A) Q g (Typ.) 5.8 at V GS = V 75 d 64 FEATURES TrenchFET Power MOSFET % R g and UIS Tested APPLICATIONS Primary Side Switch Power
More informationI2-PAK G D S. T C = 25 C unless otherwise noted. Drain-Source Voltage 260 V. Symbol Parameter SLB40N26C/SLI40N26C Units R θjc
SLB40N26C / SLI40N26C 260V N-Channel MOSFET General Description This Power MOSFET is produced using Maple semi s advanced planar stripe DMOS technology. This advanced technology has been especially tailored
More informationLoad Frequency Controller Design for Interconnected Electric Power System
Load Frequency Controller Design for Interconnected Electric Power System M. A. Tammam** M. A. S. Aboelela* M. A. Moustafa* A. E. A. Seif* * Department of Electrical Power and Machines, Faculty of Engineering,
More informationDevice Marking Device Device Package Reel Size Tape width Quantity SIP3210 SIP3210 SOP-8 330mm
SIAI N-Channel Enhancement Mode Power MOSFET DESCRIPTION The SIP3210 uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. It can be used in a wide variety of applications.
More information