Performance Efficient Parallel Self Timed Adder Design

Transcription

1 Performance Efficient Parallel Self Timed Adder Design Swathi v.s. 1, Sheelu Susan Mathews 2 1 MTech Student (VLSI& ES), Department of Electronics and Communication, FISAT, MG University, Kerala 2 Assistant Professor, Department of Electronics and Communication, FISAT, MG University, Kerala 1 swathivs.999@gmail.com, 2 sheelususan87@gmail.com Abstract- A performance efficient asynchronous parallel Self Timed Adder(PASTA) is presented in this paper. This adder achieves better performance even without any speedup circuitry/lookahed schem/carry skip unit. Skew problem are solved by Self-timing. The operation is done parallely for the bits that donot require carry chain propagation, this decreases the total delay. Recursive formula is used to perform multibit addition. The halfadders in the design makes it area efficient with minimal interconnection. The absence of clock generation and distribution units also results in less power dissipation. Clockless chips offer power efficiency, robustness and reliability. Digital simulation was done in Xilinx ISE 14.7 and implemented in Sparten 3E FPGA. Analog simulation was done in Tanner tool. An ALU was designed and synthesized using existing adder and proposed adder to show the superiority of the proposed approach. Index Terms - Binary adders, Self timed circuits, Asynchronous circuits. I.INTRODUCTION Power dissipation has become an important factor for a circuits performance and area. Binary addition is the single most important operation that a processor performs.the speed of the adders affects the performance of a processor significantly. Over all performance of an adder depend on its speed, area and power. Most of the adders are designed as synchronous circuits even though there is a big interest in clockless/ asynchronous processors/circuits [2]. Asynchronous circuits do not consider any quantization of time. A request-acknowledgment handshaking protocol is used to establish a logic flow in asynchronous circuits for pipelining in the absence of clocks. The absence of clock generation and distribution circuitry brings down the power dissipation. A single-rail wave-pipelined approach which is different from conventional pipelined adders with dual-rail encoding of carry signals is used. Self-timed adders[3] is able to run faster as early completion sensing can avoid the need for the worst case delay mechanism of synchronous circuits. The design of PASTA is regular.it uses half-adders (HAs) and multiplexers requiring minimal interconnections. Pipelined inputs can be applied before the outputs are stabilized. For independent carry chain blocks, design works in a parallel manner. The Half- Adders (HA) are simplest single. bit adders. The fulladders are single bit adders with the provision of carry input and output. The full-adders are typically composed of two HAs and hence are expensive than half-adders in terms of area, time and interconnection complexity.the use of the half adders in the design reduces area. The parallel computation of the result decreases the over all delay. The content of this paper is arranged as follows. Section II provides a review of self-timed adders. Section III presents the theory and architecture behind the proposed adder. Sections IV provide the digital implementation details. Sections V shows CMOS implementation for the proposed adder. Section VI provides the ALU implementation using proposed adder and kogge stone adder and its comparison results. Section VII presents digital and analog implementation results. Section VIII draws the conclusion. II. REVIEW OF SELF TIMED ADDERS ST implementation of combinational logic continues to be a field of important research. A ST realisation typically satisfies the acknowledgement property and the unique-successor-set property. This ensures hazard-free implementation. There are a many designs of binary adders and we focus here on asynchronous self-timed adders. Self-timed are the logic circuits that depend on engineer timing assumptions for its correct operation. Seitz's approach to self-timed design [12], in its basic form, is an AND-OR two-level implementation of logic functions. Singh's approach [13] targets ST implementation of the desired functionality by first partitioning the entire input space, constructing smaller modules for all the different partitions and then combining all those smaller modules appropriately in order to realise the required logic. DRCL is suitable for translation of synchronous circuits into asynchronous circuits based on the DI dual-rail data encoding protocol. A.Delay Insensitive Adders Using Dual-Rail Encoding Delay-insensitive (DI) circuits [6] are a subclass of asyn-chronous circuits. The defining property of pure DI circuits is that their correctness is insensitive to delays in both gate elements and connection wires. Owing to the qqq.ijrcct.org 277

2 practical limitations associated with physical implementation of such circuits, a weakest compromise is made leading to the class of quasi-delay-insensitive (QDI) circuits. QDI circuits are essentially DI circuits but with the extra assumption of isochronic forks. Delay insensitive (DI) adders are asynchronous adders that assert bundling constraints or DI operations. Therefore, they can properly operate in presence of bounded but unknown gate and wire delays [4]. There are many types of DI adders, such as DI ripple carry adder (DIRCA) and DI carry look-ahead adder (DICLA). DI adders use dual-rail encoding, this increase complexity. Dual-rail can be used to produce circuits nearly as efficient as that of the single-rail variants using dynamic logic or nmos only designs though it doubles the wire complexity. An example of 40 transistors per bit DIRCA adder is shown in [9] while the conventional CMOS RCA uses 28 transistors. Similar to CLA, the DICLA defines carry propagate, generate, and kill equations in terms of dual-rail encoding [9]. They do not connect the carry signals in a chain but rather organize them in a hierarchical tree. Thus, they can potentially operate faster when there is long carry chain. The logic complexity of DIRCA is a linear function of n,o(n), and the aver-age computation time is proportional to the logarithm of n,o( log n). The perception of dualrail encoding rationale can profit by settling of either the 0 or 1 way give further improvement. Double rail rationale need not sit tight for both ways to be assessed. It is conceivable to accelerate the convey look-ahead hardware to send convey create/convey murder signs to any level in the tree. This is unmistakably given in [9] and alluded as DICLA with speedup hardware (DICLASP). The theory and architecture behind PASTA is presented in this section. Half additions is performed by adder first accepting the two input operands. Then iteration is done using earlier generated carry and sums to perform half-additions repeatedly until all carry bits are consumed and settled at zero level. Once the addition completion indication signal is generated, then the output can be taken out of the PASTA module. A.Architecture of proposed design Fig. 1 shows the general architecture. The selection input for two-input multiplexers corresponds to the Req handshake signal. The actual operands are selected during SEL = 0 and will change to feedback/carry paths for subsequent iterations when SEL = 1. The feedback path from the HAs enables the multiple the generated carry and sum, iterative phase will be executed. Operation will be terminated when the carry sum of signals settles to 0. Fig 1. General block diagram of PASTA B.State Diagrams B.Pipelined Adders Using Single-Rail Data Encoding To empower the snake piece and build up the stream of convey signs the offbeat Req/Ack handshake can be utilized. For bitwise stream of convey yields inside, a double - rail convey tradition is utilized. More than two rationale values (invalid, 0, 1) can speak to these double - rail signs and thusly can be utilized to produce bit - level affirmation when a bit operation is finished. A last fruition is detected, when all piece Ack signs are gotten (high). The viper in [9] is a case of a pipelined snake,which utilizes full viper (FA) utilitarian pieces adjusted for double - rail convey and the snake in [9] utilizes a prematurely end rationale and early culmination to choose the best possible consummation reaction from various altered postponement lines. The downside is the costly execution of the prematurely end rationale because of high fan - in necessities. III. HIGH SPEED PASTA DESIGN Fig 2. State diagram of PASTA (a) : initial phase (b) : iterative phase The state diagrams of of the proposed architecture is composed of two phases, the initial phase and the iterative phase. Each state is represented by (C i+1, S i ) pair where C i+1, S i represent carry out and sum values, qqq.ijrcct.org 278

3 respectively, from the ith bit adder block. The circuit works as a combinational HA operating in fundamental mode during the initial phase. The tranition from one state to other is done depending on the value of inputs. It is clear that due to the use of HAs instead of FAs, state (11) cannot appear. From this the absence of full adder is clear. Initial sum and carry bits are generated in this phase. During the iterative phase (SEL = 1), the feedback path through multiplexer block is activated.the carry transitions are allowed as many times as needed to complete the recursion. The tranition from one state to other inthis phase is done depending on the Ci value. From the definition of fundamental mode circuits, the present design cannot be considered as a fundamental mode circuit as the input outputs will go through several transitions before producing the final output. It is not a Muller circuit working outside the fundamental mode is analogous to cyclic sequential circuits where gate delays are used to separate individual states [4]. C.Recursive Formula for Binary Addition Let S j i and C j i+1 denote the sum and carry, respectively, for ith bit at the j th iteration. The initial condition(j= 0) for addition is formulated as follows: S 0 i= ai bi C 0 i+1= ai (1) The jth iteration for the recursive addition is formulated by S j i = S j 1 i C j 1 i, 0 i < n. (2) C j i+1= S j 1 i. C j 1 i, 0 i n...(3) that it will be successfully transmitted to next higher bit in the (k + 1) th iteration. As shown in the state diagram, the kth iteration of lth bit state (C k l+1, S k l ) and (l + 1)th bit state (C k l+2, S k l+1) could be in any of (0, 0), (0, 1), or (1, 0) states. As C k l+1= 1, it implies that S k l= 0. Hence, from (3), C k+1 l+1= 0 for any input condition between0 to l bits. We now consider the (l + 1) th bit state (C k l+2, S k l+1) for k th iteration. It could also be in any of (0, 0), (0, 1), or (1, 0) states. In (k+1) th iteration, the (0, 0) and (1, 0) states from the k th iteration will correctly produce output of (0, 1) following (2) and (3). For (0, 1) state, the carry successfully propagates through this bit level following (3). Thus, all the single -bit adders will successfully kill or propagate the carries until all carries are zero fulfilling the terminating condition. IV DIGITAL IMPLEMENTATION The digital implementation of the proposed design was done in verilog HDL. The code for 32 bit PASTA module along with completion detection unit was developed. The developed code was simulated in xilinx ISE 14.7 and synthesized to obtain the device utilization summary and timing details. The coding was done initially in behavioral modeling then converted to structural modeling in order to obtain the gate level circuit. V. ANALOG IMPLEMENTATION The CMOS implementation of the proposed design was done in Tanner tool. CMOS circuit diagram was drawn and simulated using Tspice. The recursion is terminated at kth iteration when the following condition is met: C k n + C k n 1+ +C k 1= 0, 0 k n.(4) Fast adder will now be designed using the formulae presented in equations(1)-(4) Theorem 1: The recursive formulation of given equations will produce correct sum for any number of bits and will terminate within a finite time. Proof: We can prove the correctness of the algorithm by induction on the required number of iterations for completing the addition. Basis: Consider the operand choices for which no carry propagation is required, i.e., C 0 i= 0 for i, i [0..n]. The proposed formulation will produce the correct result by a single-bit computation time and terminate instantly as (4) is met. Fig 3. Single-bit sum module. Induction: Assume that C k i+1_= 0 for some ith bit at kth iteration. Let l be such a bit for which C k l+1= 1. We show qqq.ijrcct.org 279

4 K A B Addition by Kogge stone Subtraction Mux OP Fig 7. ALU implementation Fig MUX for the 1 bit adder Fig 5. Single-bit carry module Fig 6. Completion signal detection circuit. A B VI. ALU IMPLEMENTATION K Addition by PASTA Subtraction Mux OP The performance of two ALU was evaluated. One ALU performs its addition operation uing PASTA and the other using another high speed adder called Kogge stone adder(ksa). KSA is a parallel prefix form of carry look ahead adder. Carry is generated in O (logn) time and is widely considered as the fastest adder and is widely used in the industry for high performance arithmetic circuits. In KSA, carry is computed fast by computing them in parallel way at the cost of increased area. PASTA can effectively perform binary addition for different temperatures and process corners to validate the robustness. The best-case corresponding to minimum length carry chain does not involve any carry propagation, and hence has only a single-bit adder delay before producing the TERM signal. The worst-case has maximum carry propagation cascaded delay due to the carry chain length of full 32 bit. Performance enhancement that can be achieved using these adders as the basic unit and employing some kind of completion sensing technique. PASTA performs best among the self-timed adders. PASTA completes the first iteration of the recursive formulation when SEL = 0. Therefore, the best case delay represents the delay required to generate the TERM signal only and of the order of picoseconds. All adders show decreasing average power consumption as the process length is decreased and PASTA consumes least power among the self-timed adders. VII. DIGITAL AND ANALOG IMPLEMENTATION RESULTS A. Digital implementation result Two 32 bits A and B inputs were given into the PASTA adder block, initially the SEL signal is made 0 to intake the inputs. Then recursive addition operation is performed when SEL is made 1. A= B= C in =0 qqq.ijrcct.org 280

5 S out is initially at x state when SEL=0, output is obtained only when SEL is made 1.The addition operation is completed when the term signal is generated from the completion detection circuitry. The result obtained in S out is passed to s_output when TERM becomes 1. Final output s_output is obtained as with C out = 0 Simulation and synthesis tool used is Xinlix ISE Language used is Verilog HDL.The design was coded in behavioural and structural level. Fig 11. Inner structure of mux module TABLE 1. DEVICE UTILIZATION SUMMARY OF 32 BIT PASTA Logic utilization Used Available Utilization No.of 4 input LUT 113 9,312 1% No.of occupied slices 57 4,656 1% Fig 8. Digital simulation result. No.of containing logic slices related % No.of slices containing unrelated logic % Fig 9. RTL schematic of PASTA Total no.of 4input 113 9,312 1% LUTs No.of IOBs % Total equivalent gate count for the design Additional JTAG gate count for IOBs 726 4,752 Fig 10. Inner structure of PASTA block From the synthesis report it is clear that, due to the usage of half adders instead of full adder, the new design requires lesser number of gate count. Less area is occupied, which is evident from the number of slices occupied. The design of PASTA is regular and uses halfadders (HAs) along with multiplexers requiring minimal interconnections. Thus, it is suitable for VLSI implementation. qqq.ijrcct.org 281

6 TABLE 2. TIMING DETAILS OBTAINED AFTER IMPLEMENTATION OF DESIGN. Delay Source Destination Data path Levels of logic 71 Total Delay 97.73nS Sel Sout Sel to Sout 97.73nS[51.936% logic,45.978% route ] B. Analog implementation results The analog design of newly proposed adder design was done in Tanner tool using 180nm technology. Simulation was done using spice tool to obtain the result of addition of two 32 bit numbers A and B where A is and B is 32 b Output S out obtained must be Figure 13. Single PASTA block with C out as 1. Figure 14. 2x1 mux circuitry Figure 12. Implementation of block diagram of PASTA Fig 15. Single bit carry module qqq.ijrcct.org 282

7 Fig 16. Completion signal detection circuit timed asynchronous designing method provide all the advantages of the design to be used in any clockless chip. C. ALU implementation result An ALU was designed with a subtraction module and addition module using the proposed adder. Another ALU was designed with a subtraction module and addition module using koggestone adder. The simulation and synthesize of both the ALU designs were done in xilinx ISE 14.7 to compare their performance. When K = 0 addition is performed. When K=1, subtraction is performed. Fig 17. S1,S0 value obtained. Similarly S2 to S32 and cout values were obtained correctly. This verifies the proper working of designed CMOS implementation of the given adder design. Analog implementation shows that no clock generation and clock distribution circuitry has been used. This reduces the area and power consumption. Clockless chips offer power efficiency, robustness, and reliability. Single rail circuitry is been used. Transister feature size of 180nm is chosen for circuit design. The given adder was designed and simulated using spice tool. A single PASTA module is first designed and then a 32 bit adder is created to perform addition and correct result is obtained. Self timed asynchronous designing method provide all the advantages of the design to be used in any clockless chip. In clockless chips, data doesn t all move at the same time, which spreads out current flow, thereby minimizing the strength and frequency of spikes and emitting less. Less EMI reduces both noise related errors within circuits and interference with nearby devices. The design of the completion detection circuitry used here is simple, which makes the design easier. Analog implementation shows that no clock generation and clock distribution circuitry has been used. This reduces the area and power consumption. Clockless chips offer power efficiency, robustness, and reliability. Single rail circuitry is been used. Transister feature size of 180nm is used for circuit design. The adder was designed and simulated using spice tool. A single PASTA module is first designed and then a 32 bit adder is created to perform addition and correct result is obtained. Self Fig 18. ALU output. Figure 19. Device utilization summary of ALU with 4 bit PASTA adder Fig 20. Device utilization summary of ALU with 4 bit koggestone adder qqq.ijrcct.org 283

8 TABLE 3. PERFORMANCE OF ALU PASTA Source Sel A Destination O O Levels of logic 6 12 VIII.CONCLUSION This work presents a performance efficient implementation of PASTA. The design achieves a very simple n-bit adder that is area and interconnection-wise simple. The circuit works in a parallel manner for independent carry chains, and thus achieves logarithmic average time performance over random input values. The completion detection unit for the proposed adder is also practical and efficient. Simulation and synthesis results are used to verify the advantages of the proposed approach. The analog and digital implementation proves that the design of PASTA is robust and reliable. Clock skew problem are solved by Self-timing.The operation is parallel for those bits that do not need any carry chain propagation, makes it faster. The comparison result of performance of both the ALU shows the faster operation of proposed adder. Since no clock is used in the design, it can be utilized as part of asynchronous chip which run cooler, have fewer and lower voltage spikes. In this design no clock generation and clock distribution circuitry is been used. This reduces the area and power consumption. IX.REFERENCES Koggestone Total delay ns nS Logic 7.306nS 11.53nS Route 2.771nS 7.209nS [1] Mohammed Ziaur Rahman, Lindsay Kleeman, and Mohammad Ashfak Habib,Recursive, Approach to the Design of a Parallel Self-Timed Adder IEEE transactions on very large scale integration (vlsi) systems, vol. 23, no. 1, january 2015 [2] D. Geer, Is it time for clockless chips? [Asynchronous processor chips], IEEE Comput., vol. 38, no. 3, pp , Mar [4] P. Choudhury, S. Sahoo, and M. Chakraborty, Implementation of basic arithmetic operations using cellular automaton, in Proc. ICIT, 2008, pp [5] M. Z. Rahman and L. Kleeman, A delay matched approach for the design of asynchronous sequential circuits, Dept. Comput. Syst Technol., Univ. Malaya, Kuala Lumpur, Malaysia, Tech. Rep , [6] M. D. Riedel, Cyclic combinational circuits, Ph.D. dissertation, Dept. Comput. Sci., California Inst. Technol., Pasadena, CA, USA, May [7] R. F. Tinder, Asynchronous Sequential Machine Design and Analysis,A Comprehensive Development of the Design and Analysis of Clock-Independent State Machines and Systems. San Mateo, CA, USA: Morgan, [8] W. Liu, C. T. Gray, D. Fan, and W. J. Farlow, A 250-MHz wave pipelined adder in 2-μm CMOS, IEEE J. Solid-State Circuits, vol. 29, no. 9, pp , Sep [9] F.-C. Cheng, S. H. Unger, and M. Theobald, Selftimed carrylookahead adders, IEEE Trans. Comput., vol. 49, no. 7, pp , Jul [10] S. Nowick, Design of a low-latency asynchronous adder using speculative completion, IEEE Proc. Comput. Digital Tech., vol. 143, no. 5, pp , Sep [11] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. Reading, MA, USA: Addison-Wesley, [12] C.L Seitz, System Timing, in Introduction to VLSI Systems, C. Mead and L. Conway(Eds.), pp , Addison-Wesley, Reading, MA, [13] N.P. Singh, A design methodology for self-timed systems, M.Sc. Thesis, MIT Laboratory for Computer Science Technical Report TR-258, February [14] A. J. Martin. Asynchronous datapaths and the design of an asynchronous adder. Formal Methods in System Design 1(1): , July 1992 [3]J. Sparsø and S. Furber, Principles of Asynchronous Circuit Design. Boston, MA, USA: Kluwer Academic, qqq.ijrcct.org 284

9 About Authors Swathi V.S. received bachelor degree in electronics and communication from FISAT, MG university, kerala. Currently pursuing master degree in VLSI and embedded system from FISAT, MG university, kerala. Sheelu Susan Mathews received bachelor degree in Electronics and Communication Engineering from Mar Baselios College of Engineering, Kerala and master s degree in VLSI and Embedded Systems from ER and DCI-IT(CDAC, Trivandrum),Kerala. She has been working as an Assistant Proffessor in FISAT,Angamaly,Kerala for the past 4 years. qqq.ijrcct.org 285