IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, APRIL

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1 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, APRIL A Stimulator ASIC Featuring Versatile Management for Vestibular Prostheses Dai Jiang, Member, IEEE, Andreas Demosthenous, Senior Member, IEEE, Timothy A. Perkins, Xiao Liu, Member, IEEE, and Nick Donaldson Abstract This paper presents a multichannel stimulator ASIC for an implantable vestibular prosthesis. The system features versatile stimulation management which allows fine setting of the parameters for biphasic stimulation pulses. To address the problem of charge imbalance due to rounding errors, the digital processor can calculate and provide accurate charge correction. A technique to reduce the data rate to the stimulator is described. The stimulator ASIC was implemented in 0.6- m high-voltage CMOS technology occupying an area of 2.27 mm 2. The measured performance of the ASIC has been verified using vestibular electrodes in saline. Index Terms Charge balance, data compression, implanted device, neural stimulation, stimulation management, vestibular prosthesis. I. INTRODUCTION T HE vestibular organ, located in the inner ear, provides input to the nervous system for head motion and orientation in order to maintain body balance and steady vision. The system consists of three orthogonal fluid-filled semicircular canals for sensing angular head motion, and two otolithic organs (the Saccule and the Utricle) for linear acceleration. Dysfunction of the vestibular system causes postural instability, blurred vision during head motion, and chronic disequilibrium. Research into the response to pulsatile stimulation has shown the possibility for neural prostheses to treat severe vestibular disorders [1] [5]. These studies suggest that by applying precise pulsatile stimulation to the vestibular nerve, mimicking the natural frequency-modulated neural response to head motion and bypassing the defective vestibular organ, balance sensation could be restored. Based on these findings, a variety of prototype vestibular prostheses has been developed. In 2000, Gong and Merfeld [5] reported a single-channel prosthesis which stimulated the nerve branch innervating the anterior semicircular canal with electrical pulses, rate modulated by angular velocity. Della Santina et al. [6] later reported a device with a similar Manuscript received October 14, 2010; revised February 27, 2011; accepted March 24, Date of current version May 18, This work was supported by the European Commission under project CLONS (grant agreement no ). This paper was recommended by Associate Editor V. Owall. D. Jiang, A. Demosthenous, and X. Liu are with the Department of Electronic and Electrical Engineering, University College London, London WC1E 7JE, U.K. ( a.demosthenous@ee.ucl.ac.uk). T. A. Perkins and N. Donaldson are with the Department of Medical Physics and Bioengineering, University College London, London WC1E 6BT, U.K. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TBCAS concept but capable of stimulating the nerve branches innervating three semicircular canals, via a stimulation queue to avoid clashes between stimuli on different channels. Shkel et al. [7] developed a vestibular prosthesis with a custom-designed microelectromechanical-system (MEMS) gyroscope as a motion sensor, showing the potential for a single-chip implanted device. Recently, a design of a vestibular prosthesis towards a fully integrated implantable device has been published by Constandinou et al. [8] [10]. This design uses custom-made MEMS sensors, signal-processing units, and current drivers as separate integrated circuits (ICs), which could be enclosed in a system in package (SiP). Stimulus pulses were amplitude modulated according to the continuous interleaved sampling (CIS) scheme, similar to that used for cochlear implants [11] [13]. The work presented in this paper is part of an activity aimed at further refining the performance of vestibular neural prostheses [14] [17]. This paper describes a prototype multichannel complementart metal oxide semiconductor (CMOS) stimulator application-specific integrated circuit (ASIC) designed as a part of a three-dimensional (3-D) closed-loop implantable vestibular prosthesis [14]. The system aims at providing independent stimulation to the nerve branch innervating each of the three semicircular canals to restore loss of vestibular function. Stimulus currents will be delivered to the nerve branches via multisite implantable vestibular electrodes [17]. Furthermore, the electrical stimulation parameters will be dynamically adjusted via a feedback parameter using vestibular-evoked potentials (i.e., activity of the vestibular nerve in response to electrical stimulation [18]). Human rotation detection thresholds are around 0.5 /s [3], [19], [20]. Primate vestibular nerve pulse-rate modulation sensitivities of around 1 pulse/s (pps) per /s have been found [3]. Therefore, to match normal performance, at least 0.5-pps resolution is required. With a stimulus pulse rate requirement of 1 to 500 pps, wide dynamic range and fine resolution are needed. This implies long command frames to update stimulus patterns, unless some data compression is used. In addition, to accurately detect the facial and vestibular thresholds [3], a maximum current amplitude of 1 ma with 8-b resolution is required. The new stimulator ASIC is accordingly designed to meet these specifications. In addition, it provides great flexibility and precision for all stimulus parameters, while allowing rapid update of these parameters, as may be required to track fast head movement. This is achieved by the versatile on-chip digital stimulation management. The remainder of this paper is organized as follows. Section II gives an overview of the stimulator design. Section III describes details of the hardware implementation and operation /$ IEEE

2 148 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, APRIL 2011 Fig. 1. System block diagram of the vestibular prosthesis. of the stimulation management. Section IV describes the output stage design. Section V presents measured results from testing the ASIC with vestibular electrodes in isotonic saline, followed by concluding remarks in Section VI. II. SYSTEM OVERVIEW The architecture of the vestibular prosthesis under development is shown in Fig. 1. The system is unilateral (vestibular stimulation in one ear), although bilateral stimulation can be implemented by using two of these systems (one in each ear). The prosthesis comprises external and implanted parts which are wirelessly connected via an inductive link similar to a cochlear implant [11]. The final implanted part, including packaging and receiver coil, is expected to be of comparable size to a commercial cochlear implant. 1 The external part includes signal processing to convert head motion into settings for stimulation pulses. The settings, organized in command frames, are transmitted via the inductive link to the implanted part to generate biphasic current pulses to the stimulation electrodes. The telemetry unit receives power from the transmitter to supply the entire implanted device, and extracts data modulated as a serial stream on the carrier. The implanted device consists of three 1 MED-EL, Austria. [Online]. Available: identical stimulators functioning in parallel (Fig. 1). The stimulators are assigned, respectively, to the three semicircular canals and work independently to deliver stimulation to the ampullary nerve of each canal. Each stimulator has a management unit and an output stage consisting of an 8-b current digital-to-analog converter (DAC) and a switching circuit. The command frames from the telemetry are sent to all three stimulators. Each frame contains settings for only one canal, identified by the Canal ID section. The management unit in each stimulator receives the frames. Once the Canal ID in a frame matches the settings of the stimulator, the management unit loads and decodes the settings from the command frame to control the stimulation. The management unit controls the DAC to set the stimulation current amplitude and drives the switching circuit to generate current pulses with specified pulsewidth and interval. The stimulators are designed to generate biphasic current pulses [21] because of the relatively high stimulation pulse-rate requirement. A cathodic pulse delivers enough charge for neural excitation, followed by an anodic pulse of equal but opposite polarity charge. The profile of a biphasic pulse (Fig. 2) is specified by five parameters: the cathodic pulse amplitude and width, the interphase delay, the anodic-to-cathodic ratio which defines the ratio between the amplitudes of the two phases (the ratio of their pulse widths is the inverse value), and

3 JIANG et al.: A STIMULATOR ASIC FEATURING VERSATILE MANAGEMENT FOR VESTIBULAR PROSTHESES 149 Fig. 2. Biphasic current stimulus waveform. the pulse interval (inverse of pulse repetition rate). The five parameters of specifying the pulse profile give high flexibility for programming the stimulation pattern. In this prosthesis, the anodic amplitude can be equal to, or 1/2, 1/4, and 1/8 of the cathodic amplitude whose width changes accordingly to maintain the charge balance. Each stimulator drives an electrode array (containing up to 8 electrodes) for multisite stimulation. Only one pair of electrodes in a given electrode array can be selected at a time. This is performed by the channel ID section in the command frame. To minimize the amount of information transmitted, in this system, frames are only sent when changes of stimulation are required. As three stimulators share the communication link, the conventional approach of using the external signal processor to initiate each biphasic pulse [5], [6] is not suitable. First, it would saturate the communication channel quickly during fast head motion. Second, it cannot deal with situations where pulses on different canals may overlap since the three stimulators operate independently. Autonomous stimulation management is therefore necessary to retrieve and store the control information at the arrival of a new frame and continuously generate current pulses as specified. Details of the management unit and output stage are given in the following sections. III. STIMULATION MANAGEMENT A. Hardware Implementation The stimulation-management unit has two major functions: 1) to derive data settings from command frames sent from the external device to the specific canal, and 2) to manage the current DAC. The hardware for the management unit comprises the data loading unit (DLU) and the stimulation control unit (SCU) which operate at different clock frequencies. The DLU uses a 100-kHz clock to receive command frames at 100 kb/s, while the SCU works with a 1-MHz clock to achieve 1- s resolution for the pulsewidth. This 1-MHz clock frequency must be accurate and consistent, because any frequency variation on the clock may result in mismatch in total charge delivered between the cathodic and anodic phases. This imbalance could charge up the blocking capacitor and saturate the output stage. For this reason, an independent clock source is used rather than the conventional method of deriving the clock from the carrier, which prevents the clock frequency being affected by any interruption on the inductive link. Since the clocks for the DLU and SCU are not synchronized, a flag indicator is employed. To avoid conflict, the SCU only retrieves data settings when the flag signals that there is no ongoing data-loading process. 1) DLU: Fig. 3 shows the block diagram of the DLU and the structure of the command frame. A command frame, sent serially in the data stream, consists of four sections: 1) a synchronization word, followed by 2) a Canal ID; 3) a data settings section with 7 binary words; and 4) a correction word at the end. The data stream is shifted into a shift register one bit per cycle at the 100-kHz clock DCLK. Once a synchronization word is detected, the DLU recognizes that a command frame has been fully received and, hence, checks the Canal ID. If the Canal ID matches, the data settings section is read in parallel to a verification block. In implementation, the two bits of the Canal ID for each stimulator are fixed to logic 1 or 0. The verification block is designed to ensure that the loaded pulse profile settings do not contain errors which may cause appreciable charge imbalance at the electrode-tissue interface. The settings of the pulsewidth and amplitude are verified to ensure that the total charge injected is below the limit for safe stimulation for the electrodes used, and the biphasic pulse is charge-balanced. To control the amount of charge injected, either the current amplitude or pulse duration or both can be controlled. Once the settings are confirmed, a Load signal is generated. This signal is a one-clock-cycle pulse to load the relevant binary words from the command frame to eight registers. The settings for the channel ID, cathodic amplitude and width, interphase delay, pulse rate, and passive discharge indicator are saved directly, while the settings for the anodic amplitude and width are calculated from the settings of the cathodic phase and anodic-to-cathodic ratio. One clock period of 10 s is allowed for the eight registers to process and store the settings. During this period, the flag indicator signals that data are not ready, until all settings are stably stored. The settings remain in the registers until another command frame is loaded and verified. The SCU loads data settings from these registers. 2) SCU: The stimulation control operation is based on a state-machine with five counters chained together. The schematic of the state machine is shown in Fig. 4. It loads the stored data settings from the DLU at the beginning of each stimulation pulse and then activates the counters in a sequence to control the biphasic pulse parameters. This process repeatedly starts itself after the specified pulse interval. Two different types of counters are employed to construct the state machine. Both types are downcounters which load a value on the command LoadCnt and, if enabled by the EN input, count down from the loaded value to zero and stop. However, the outputs from the two types are different. Type- generates a one-clock-cycle-long pulse when it reaches zero, while Typegives logic HIGH when the counting starts and stays at HIGH until it reaches zero. The pulse-rate counter in Fig. 4 is a Type- counter. It is configured in a self-repetitive fashion. The pulse-rate setting is loaded into the counter at the LoadCnt pulse. The counter starts countdown to zero and then generates a LoadCnt pulse that also triggers itself to load a new setting and counts down again. The duration of this count-down process is equal to the pulse interval

4 150 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, APRIL 2011 Fig. 3. Block diagram of the data loading unit. defined in Fig. 2. The value loaded into the counter is the number of clock cycles during a pulse interval. The remaining four counters, namely, the cathodic width counter, interphase delay counter, anodic width counter and compensation phase counter, are all Type- counters. These four counters are chained in a fashion where counting in one counter is controlled by the output signal from previous counters. Each counter controls one of the four phases of the stimulation pulse (see Fig. 2). The value loaded to these counters is the number of clock cycles during each phase. The compensation phase counter is for the multiphase charge balancing, described in Section III-D. The process of generating a biphasic current pulse starts from a LoadCnt pulse from the pulse-rate counter. At this time instant, the channel ID is sent to a decoder to activate the chosen pair of stimulation electrodes. At the same time, the four Typecounters load data settings from the respective registers. The chain of these counters provides a switching sequence to generate biphasic currents featuring cathodic, interphase, anodic and compensation phases as detailed in Section IV. The cathodic and anodic signals (see Fig. 4) also control a multiplexer to set the input to the current DAC. B. Stimulation Mode There are two modes for stimulation: the operating mode and the sleep mode. During the sleep mode, the 1-MHz operation clock, called SCLK in Fig. 4, is disabled to stop the state machine. The device enters the sleep mode when a command frame arrives with a cathodic amplitude setting word of zero. In this mode, only the DLU is active and stimulation is paused. Stimulation can be reactivated simply by sending another frame with a nonzero cathodic amplitude setting word. C. Optimization for Faster Data Transmission During fast head motion, the stimulation parameters change quickly. Therefore, the command frame must be short enough to allow fast downlink transmission to provide sufficient information about the motion. Besides this requirement, future improvement of the vestibular prosthesis will have the ability to record vestibular-evoked potentials [18] and send the digitized data to the external device for processing and closed-loop control. Since the uplink and downlink transmission share the telemetry, shortening the command frames in the downlink allow allocation of more communication capacity to the uplink so that faster sampling or longer recording windows are possible. The largest section in a command frame is the pulse interval word for setting the pulse rate. According to the stimulation control operation described in Section III-B, the value of the setting word is the number of clock cycles in a pulse interval. The length of this clock cycle is decided by the desired resolution on pulse rate, which must be comparable to the natural sensitivity to angular velocity. For a maximum pulse rate of 500 pps, an increase of 1 s in pulse interval results in a 0.25-pps change. This defines the counting speed of the pulse-rate counter at 1 MHz. To provide a full pps range of pulse rate with a 1- s step size, 20 b are required for the setting word. However, the inverse relation between the pulse interval and rate, shown in Fig. 5(a), means that the pulse-rate resolution becomes much finer with the decrease of the pulse rate when

5 JIANG et al.: A STIMULATOR ASIC FEATURING VERSATILE MANAGEMENT FOR VESTIBULAR PROSTHESES 151 Fig. 4. State machine for the stimulation control. the step size of the pulse interval remains at 1 s, as shown in Fig. 5(d). These fine resolutions in the low pulse-rate range are redundant. This suggests the possibility of using a small pulse interval increment in the high pulse-rate range and a large increment in the low-rate range without compromising the pulse-rate resolution. Thus, a short word can be sent in the frame and later converted into a 20-b word for the pulse-rate counter. The conversion method should allow the increment on the conversion output to change with the input value which increases with a constant increment. Exponential conversion is one of these methods. A two-stage data conversion method is employed in this stimulator design. It combines an exponential conversion stage with a variable sampling rate stage, reducing the size of the pulse-rate setting word from 20 to 12 b. 1) Exponential Conversion: Similar to the technique used in [22], the input value to the exponential conversion consists of an exponential increment and a linear increment. As illustrated in Fig. 6, the higher bits in the input word are the exponent and the lower bits are the mantissa. In the conversion process, the value of the exponent is used to set the exponential intervals in the conversion output from to ; and the value of the mantissa is used to linearly divide each interval into divisions. The conversion process can be expressed as (1) where is the input setting word, and man is the number of bits in the mantissa. is a function to get the integer value from a fractional number, and is to obtain the fractional value. Hence (2a) (2a) For this stimulator design, a 14-b setting word is chosen with a 4-b exponent and a 10-b mantissa. With an increment of 1, after the conversion, input values between 900 and generate an output range between 1925 and , which sufficiently covers the required range of the pulse interval. The pulse rate is plotted against the input setting word in Fig. 5(b), and the pulse-rate resolution is plotted against the pulse rate in Fig. 5(e). A 900 offset is added during the conversion so the input word starts from 0. Fig. 5(e) shows that a large portion of the pulse-rate resolution stays below 0.3 pps except in the range where pulse rates are between 387 and 488 pps, but still remains in a tolerable range below 0.5 pps. With this conversion approach, the number of values required to have pulse rates in the 1 to 500 pps range with fine resolution, is reduced from to Hence, the size of the setting word is shortened by 40% from 20 to 14 b.

6 152 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, APRIL 2011 Fig. 5. Change of the pulse rate and pulse-rate resolution with setting values. (a) Pulse rate versus setting value with the linear setting method. (b) Pulse rate versus setting value after exponential conversion. (c) Pulse rate versus setting value after exponential conversion and variable-rate sampling. (d) Pulse-rate resolution versus setting value with the linear setting method. (e) Pulse-rate resolution versus setting value after exponential conversion. (f) Pulse-rate resolution versus setting value after exponential conversion and variable-rate sampling. lower 11 b increasing from 1 to 2048 and the highest bit indicating the zone. In the two-stage conversion process, the 12-b setting word is first extended to a 14-b value using while Fig. 6. Illustration of exponential conversion. while The hardware implementation of this conversion is quite straightforward. The conversion can be achieved by adding a 1 in front of the mantissa and then left-shifting by bits, as illustrated in Fig. 6. 2) Variable-Rate Sampling: Examining Fig. 5(b) and (e), it is found that the length of the pulse interval word can be further shortened by choosing a variable increment for the input value, in effect, sampling the original 14-b setting word at a variable rate. Dividing Fig. 5(b) into three zones by the value of the setting word, with an increment of 1 on the input value, the pulse rate changes significantly in zone 1 with the first 2048 input values, but becomes slow in zone 2 with the next 2048 input values, and slower in zone 3 where the input value is beyond Correspondingly, the resolution is largely beyond 0.1 pps in zone 1 but almost entirely below 0.1 pps in zone 2 and zone 3, shown in Fig. 5(e). If the increment on the input value, instead of 1, is 2 for zone 2 and 8 for zone 3, the number of values to set the pulse rate is further reduced to 3339 without compromising the resolution to an unacceptable level, as shown in Fig. 5(c) and (f). Thus, the pulse interval word needs only 12 b, with the while (3) then the 14-b value is converted into a 20-b pulse interval setting by using (1). The two-stage conversion shortens the total length of a command frame by 21.6%, but the pulse-rate resolution is still finer than 0.5 pps. The hardware implementation of mapping a 12-b setting word to a 14-b value using (3) involves only shifting and adding operations. By reading the highest two bits of the 12-b setting word, it can be decided which of the three possibilities in (3) to apply. For 2048, 900 is added to the 12-b word. For , the lowest ten bits of are taken out to construct a new 12-b word with a 1 inserted to the left (MSB) and a 0 to the right (LSB), then 900 is added to the new word. For 3072, a 14-b word is constructed from the lowest ten bits of with a 1 inserted to the left and three 0 to the right, and then 900 is added to the new word. D. Multiphase Charge Balancing Charge balancing is a major design issue in biphasic current stimulators [23] [25]. Due to practical limitations, the cathodic

7 JIANG et al.: A STIMULATOR ASIC FEATURING VERSATILE MANAGEMENT FOR VESTIBULAR PROSTHESES 153 Fig. 7. Biphasic current pulse with multiphase change balance. and anodic phases may not generate the same amount of charge. Charge imbalance may result in direct current, causing harmful electrochemical reactions, particularly electrolysis which causes damage to the electrodes and tissue. A digital approach to balance charge mismatch due to the rounding error in generating asymmetrical pulses is implemented in this design. This approach requires a small physical area and low power consumption. Charge imbalance between the cathodic and anodic phases may occur in an asymmetrical pulse due to the step nature of the DAC output (i.e., limited resolution). In an asymmetrical biphasic pulse, the amplitude of the anodic phase is derived by dividing the cathodic phase amplitude with the anodic-to-cathodic ratio. This is achieved by dividing the 8-b DAC input by the ratio. However, if the input for the cathodic amplitude is not an integer multiple of the ratio, a rounding error will introduce charge mismatch between the two phases. With reference to Fig. 7, expressing the amplitude of the cathodic pulse as, its width as, and the anodic-to-catholic ratio as, the width of the anodic pulse is therefore and its amplitude is. In case is not an integer multiple of, it can be written as, where is the closest integer multiple of smaller than. The binary-weighted DAC cannot generate an output of because it is not an integer multiple of the LSB current, so the DAC output for the anodic amplitude is reduced to, and a charge mismatch of occurs between the two phases. The mismatch is illustrated as the shaded area on top of the anodic phase in Fig. 7. The problem of the small remaining charge can be minimized by several methods but they have limitations as follows. 1) Conventional passive discharge [23] can be added by shorting the electrodes after the pulse. However, the fast stimulation rate may not allow enough time to fully cancel the mismatch. 2) A current DAC with finer resolution can also be a solution, but this approach increases the difficulty of layout to achieve good linearity. 3) The cathodic amplitude can also be limited to an integer multiple of the ratio, but the flexibility of the stimulation control is compromised by this approach. An alternative method using an extra phase for charge balancing is employed in this design. The extra compensation phase is introduced in the current pulse after the anodic phase. This phase is designed to cancel the mismatch due to the rounding error. Once the current DAC input for anodic amplitude is set to, the mismatch is on the anodic side. The amount of charge imbalance is. Additional current is injected in the compensation phase to reduce this mismatch. Since is also a binary integer value and is the cathodic width, the compensation phase can be easily implemented. As the maximum anodic-to-cathodic ratio is 8 and the maximum cathodic pulsewidth is 500 s, the maximum possible current amplitude of the compensation phase is 28 A (the maximum rounding error at the 8-b current DAC input is 7, so A) and the maximum charge is 14 nc. An 8- s interval separates the anodic and compensation phases to allow sufficient time for the DAC to settle at the new output. Since, in practice, a DAC may not be perfectly linear, a small amount of mismatch may still remain after the compensation phase. To suppress the residual mismatch, a passive discharge phase can be activated before the next biphasic pulse starts. The passive discharge is optional, decided by one extra bit in the command frame. Fig. 7 illustrates a biphasic pulse with multiphase charge balancing. Hardware implementation of multiphase charge balancing is simple. In the data-loading process, deriving the anodic amplitude and width is merely a shifting operation since the options for the anodic-to-cathodic ratio are 1, 2, 4, and 8. The residue bits resulting from the shifting, with a value, are saved as the DAC input during the compensation phase. If, the cathodic width is loaded into the compensation phase counter at the LoadCnt pulse (see Fig. 4) during the stimulation control to later activate a compensation phase; otherwise, the counter stays at zero and no compensation phase is activated. IV. OUTPUT STAGE Since the voltage swing on the electrodes during stimulation can be in the region of 10 V, a cascode current source with active feedback is employed to provide high output impedance and large voltage compliance [26]. The circuit schematic of the output stage is shown in Fig. 8(a). Current generated from an 8-b DAC is multiplied by 16 using an active feedback current mirror constructed with high-voltage transistors and an opamp (folded cascode with dc gain of 90 db), supplied at 18 V. The circuit provides current

8 154 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, APRIL 2011 Fig. 8. (a) Output stage. (b) The 8-b current DAC. to a switching circuit which alters the current direction to deliver biphasic current pulses to the electrode-tissue interface. The 8-b current DAC shown in Fig. 8(b) consists of two identical 4-b binary-weighted cascode current sources [27] with each source controlled by 4 b of the DAC input. The input bias current of the current source controlled by the lower 4 b is 250 na while that of the current source controlled by the upper 4 b is 4 A. Hence, the 8-b DAC output current is between 0 and A and the amplitude of is between 0 and 1.02 ma (with a step size of 4 A). The 8-b DAC input is controlled by the values in the cathodic and anodic amplitude registers. The current DAC works at a 5-V supply voltage. The switches, and in the switching circuit in Fig. 8(a) are organized as an -bridge [8], [28], [29], with an additional switch to provide isolation from the negative power rail. Electrodes to are connected to and through a multiplexer consisting of channel switches to and an off-chip blocking capacitor. The indifferent electrode is connected to and via another off-chip blocking capacitor. Only one of the electrodes to can be selected at a time, and together with, the electrode pair allows bipolar stimulation. Current is shaped into biphasic pulses by turning the switches on and off in sequence. During stimulation, current flows either through the path to form the cathodic pulse, colored in blue in Fig. 8(a), or through the path to form the anodic pulse colored in red. The on-resistance of each switch is 500 and the charge injection is about 4 pc. The capacitance of and is 200 nf, so that the voltage drop across each blocking capacitor at the maximum stimulation current of 1 ma and pulsewidth of 500 s is 0.5 V. Since the vestibular prosthesis is designed for chronic use, the implanted device must be fail-safe. In the event of a single fault occurring inside the stimulator ASIC, the resulting direct current through the electrodes must be close to zero ( 10 na) to avoid electrode damage and tissue destruction. Multifault situations are not included in the fail-safe design considerations as more than one failure occurring in the ASIC at the same time is considered highly unlikely [30]. The dual-blocking capacitor arrangement shown in Fig. 8(a) is used to protect the stimulator from damaging consequences in the event of a single fault. In such an event, if one switch in the switching circuit is unexpectedly shorted to the power rails or becomes open/short circuit during stimulation or one of the capacitors goes short circuit, any possible direct current path through the electrodes to the power rails must have leakage currents well below the accepted limit. To verify the resulting direct current leakage in case of such an ASIC fault, a copy of the output stage arrangement was built with discrete components. The fail-safe feature was tested with the output stage circuit connected to electrodes in saline and driven by control signals to deliver biphasic pulses. Various scenarios were tested with every single switch tied to the power rails, made open or short circuit. In all scenarios, the direct current flow through the electrodes was measured over a period of 10 s. Results from all of the scenarios suggest that the direct current is always smaller than 5 na. V. MEASURED RESULTS The prototype stimulator circuitry was designed with the XFAB 0.6- m high-voltage CMOS technology [31] and Cadence Verilog design flow for the digital-management unit. Since the three stimulators are identical to reduce prototyping costs, a single silicon chip contains only one stimulator. This is sufficient to verify the functionality of the stimulator ASIC. The chip microphotograph is shown in Fig. 9. The size of the core area is 2.27 mm with the digital part occupying about 55% of the area. The digital circuits and the low-voltage analog part operate at 5 V while the high-voltage output stage can accommodate voltages up to 18 V. Table I summarizes the key features and performance characteristics of the ASIC. A. Current Source Performance Fig. 10 shows the measured full-scale output of the current source [see Fig. 8(a)]. Results from four fabricated chips are

9 JIANG et al.: A STIMULATOR ASIC FEATURING VERSATILE MANAGEMENT FOR VESTIBULAR PROSTHESES 155 Fig. 9. Chip microphotograph. (a) Management unit. (b) Current source. (c) Switching circuit. TABLE I ASIC FEATURES AND PERFORMANCE Fig. 10. Measured full-scale current source output versus DAC input code from four ASICs. plotted alongside the expected current output. The results from all four chips demonstrate reasonable linearity, though a gain variation exists among the chips. At the maximum current output of 1020 A, the largest deviation from the expected value is 48 A, suggesting a 4.7% error. The output characteristic of the current source was measured with the output current set to 60 A, 252 A, 508 A, 764 A, and 1020 A, respectively. Fig. 11 shows the measured output current against the voltage across the current source. The results show that the current source requires a minimum 0.3 V to maintain a constant current output at 60 A, and 1.4 V for the highest current output of 1.02 ma. The output impedance of the current source indicated in Fig. 11 is above 10 M, but an accurate value is not obtainable given the accuracy level of the equipment used in the tests. B. Test Setup for Stimulation with Electrodes in Saline Tests were conducted with the stimulator ASIC connected to a thin-film electrode array in isotonic saline. The electrodes are specially designed for vestibular stimulation [14], [17]. For a maximum current pulse of 1 ma, the voltage swing required on the electrodes is about 10 V. Hence, an 18-V supply is sufficient to account for the added voltage drops in the driving circuit from switches, etc. A Xilinx FPGA XC3S700AN was programmed Fig. 11. Measured output characteristic curves of the current source. to construct the command frames and generate a 100-kb/s data stream to transmit the frames to the stimulator. The 2-b Canal ID of the stimulator ASIC was set externally. All of the control signals to drive the output stage were put on pads and monitored on a logic analyzer (Agilent 16801A). Two 200-nF ceramic off-chip blocking capacitors were used. A number of stimulation electrodes were connected to the multiplexer output at the stimulator ASIC. A 2-k resistor was connected in series with the selected electrode. The stimulation pulses were displayed on an oscilloscope by monitoring the voltage across this resistor with a differential probe (Picotech TA044). A low-pass filter was connected to the 2-k resistor in parallel to measure the direct current through the electrodes due to charge imbalance. The dc voltage after filtering was measured with a multimeter (Agilent 34401A). This arrangement is similar to the circuit in [30] and [32] in concept but with two-pole filtering. The test setup is illustrated in Fig. 12. Note that the low-pass filter and

10 156 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, APRIL 2011 TABLE II STIMULATION PROFILES OF THE WAVEFORMS SHOWN IN FIG. 13 Fig. 14. Measured process of changing the stimulation current pulse from profile 1 to profile 2. Profile 1: symmetrical pulse with pulse amplitude 500 A, pulsewidth 200 s and pulse interval 3800 s. Profile 2: asymmetrical pulse with cathodic phase amplitude 1 ma, cathodic phase width 100 s, anodic-tocathodic ratio 4 and pulse interval 1935 s. Fig. 12. Test setup for direct current measurement with electrodes in saline. Fig. 13. Measured stimulation current pulses with different profiles. The profiles of the four waveforms are listed in Table II. voltage meter were only used for the direct current measurement (enabled by the two switches shown in Fig. 12). C. Stimulation Pulses and Multichannel Stimulation Fig. 13 shows four measured stimulation current waveforms with different profiles. The profile of each waveform is listed in Table II. For the pulse-rate setting, both the setting values and the actual pulse intervals derived from the two-stage exponential conversion are shown. Among them, waveform-(b) and -(c) are symmetrical pulses, while -(a) and -(d) are asymmetrical. The anodic width in waveform-(a) is four times the cathodic width, and twice in waveform-(d). All four waveforms are generated correctly against the settings. The rise time for a 1-mA current pulse is about 1 s. The stimulation management enables rapid update of the stimulation parameters as may be required to track fast head motion. An example measurement is shown in Fig. 14. In this test, two command frames were sent in sequence to the data input terminal (Data In). The first frame sets the current pulse to be symmetrical (500- A amplitude and 200- s width for cathodic and anodic phases), while the second frame changes the anodic-to-cathodic ratio to 4 and doubles the pulse rate. Simultaneous stimulation on two channels in two separate electrode arrays (corresponding to stimulation on two canals) was also tested. The electrode arrays were placed at 3-mm separation in isotonic saline. Each channel was driven by its own stimulator ASIC. The two stimulators and their power supplies were electrically isolated from one another by using the switched-capacitor method described in [33]. The approach reduces crosstalk between simultaneously activated channels in a multichannel stimulator implant. Fig. 15 shows the measured current pulses from the two channels. The two stimulators

11 JIANG et al.: A STIMULATOR ASIC FEATURING VERSATILE MANAGEMENT FOR VESTIBULAR PROSTHESES 157 Fig. 15. Measured stimulation current pulses from two channels, operated simultaneously and using the crosstalk reduction method in [33]. Upper waveform (channel 1): pulse amplitude 220 A, pulsewidth 250 s, interphase delay 100 s, pulse interval 2.5 ms (400 pps); Lower waveform (channel 2): pulse amplitude 160 A, pulsewidth 200 s, interphase delay 50 s, pulse interval 2 ms (500 pps). Fig. 16. Measured output current pulse with multiphase charge balance. generate biphasic current pulses with different pulse amplitude, width, and repetition rate. D. Multiphase Charge Balancing The performance of multiphase charge balancing was measured with asymmetrical pulses. The pulse interval was set to 1935 s, giving a pulse rate of pps, slightly higher than the maximum required 500 pps. The cathodic amplitude was set to the maximum required current of 1 ma. The anodic-to-cathodic ratio was 4. Charge mismatch is most likely to occur in this arrangement. Fig. 16 shows the stimulation pulse waveform with the appearance of a compensation phase. In the cathodic phase, the input value to the current DAC is 250. In the anodic phase, the input changes to 62, derived from 248/4, where 248 is the closest integer multiple of 4 below 250. This changes the anodic current amplitude to 248 A. Eight microseconds after the anodic phase, a compensation phase starts. The current DAC input is 2 in this phase to generate a current amplitude of 8 A. The direct current through the electrodes was also measured. After the compensation phase, the maximum direct current is 4.5 na, which is negligible. With passive discharge activated, this value is further brought down to 1 na. VI. CONCLUSION This paper has described the design of a stimulator ASIC as part of an implantable 3-D vestibular neural prosthesis. The key design factor is the versatility of generating variable stimulation patterns. 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12 158 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, APRIL 2011 [17] K.-P. Hoffmann, W. Poppendieck, T. Doerge, M. Hanauer, W. Gong, C. Haburcakova, D. M. Merfeld, and S. Micera, Design of microelectrodes for a vestibular prosthesis, presented at the BMT 2010, Rostock, Germany, Oct [18] V. Kögler, Acquisition and analysis of vestibular evoked potentials in the horizontal semicircular canal of an animal model, M.Sc. dissertation, ETH Zurich, Zurich, Switzerland, [19] L. Grabherr, L. K. Nicoucar, F. W. Mast, and D. M. Merfeld, Vestibular thresholds for yaw rotation about an earth-vertical axis as a function of frequency, Exp. Brain Res., vol. 186, no. 4, pp , Apr [20] A. J. Benson, E. C. Hutt, and S. F. Brown, Thresholds for the perception of whole body angular movement about a vertical axis, Aviat. Space Environ. Med., vol. 60, no. 3, pp , Mar [21] N. N. de Donaldson and P. E. K. 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Workshop on FES, Vienna, Austria, Sep. 2010, pp Dai Jiang (S 07 M 09) was born in Lanzhou, China, in He received the B.Sc. and M.Sc. degrees from Beijing University of Aeronautics and Astronautics, Beijing, China, in 1998 and 2001, respectively, and the Ph.D. degree from University College London (UCL), London, U.K., in He was with Datang Telecom Group, China, from 2001 to 2002, working on developing field-programmable gate-array functions for wideband code-division multiple-access signal processing. From 2006 to 2008, he was a Research Assistant, and since 2009, he has been a Postdoctoral Research Associate, both with the Analog and Biomedical Electronics Research Group at UCL. His research interests include complementary metal oxide semiconductor analog and mixed-signal integrated-circuit design for biomedical applications and frequency synthesis for wireless communications. Dr. Jiang received an Overseas Research Students (ORS) Award during his Ph.D. study. Andreas Demosthenous (S 94 M 99 SM 05) was born in Nicosia, Cyprus, in He received the B.Eng. degree in electrical and electronic engineering from the University of Leicester, Leicester, U.K., in 1992, the M.Sc. degree in telecommunications technology from Aston University, Birmingham, U.K., in 1994, and the Ph.D. degree in electronic and electrical engineering from University College London (UCL), London, U.K., in From 1998 to 2000, he held a Postdoctoral Research Fellow position with the Department of Electronic and Electrical Engineering, UCL. In 2000, he was appointed to the academic faculty of the same department, where he is currently a Professor and leads the Analog and Biomedical Electronics Research Group. He has numerous collaborations for interdisciplinary research and has published more than 150 articles in journals and international conference proceedings. He is an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS and an Associate Editor for the IEEE Circuits and Systems Newsletter. He is on the International Advisory Board for Physiological Measurement, Institute of Physics. In 2006 and 2007, he was an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS. His main areas of research are analog and mixed-signal integrated circuits for biomedical, communication, sensor, and signal-processing applications. Dr. Demosthenous is a member of the Analog Signal Processing Technical Committee (ASPTC) and the Biomedical Circuits and Systems (BioCAS) Technical Committee of the IEEE Circuits and Systems Society (CASS). He is also a member of the U.K. Engineering and Physical Sciences Research Council (EPSRC) Peer Review College. He is a member of the Technical Programme Committee of various IEEE conferences, including ESSCIRC, BioCAS, and ECCTD. Timothy A. Perkins received the B.Sc. degree in physics from Bristol University, Bristol, U.K., in 1971 and the M.Sc. degree in electrical engineering from London University, London, U.K., in Since 1972, he has designed stimulation controllers at the British Medical Research Council s Neurological Prostheses Unit under Prof. G. S. Brindley. His research interests continue to be in the design and practical use of stimulation controllers to rehabilitate the neurologically disabled. Mr. Perkins and Prof. Giles Brindley jointly won the Institute of Electrical Engineers prize for helping disabled people in 1985, for their bladder control work. He joined Nick Donaldson s Implanted Devices Group at University College London in Xiao Liu (S 05 M 09) was born in Chengdu, China, in He received the B.Eng. degree in information engineering from Xi an Jiaotong University, China, in 2003, the M.Sc. degree in microelectronics systems design from the University of Southampton, Southampton, U.K. in 2004, and the Ph.D. degree from University College London (UCL), London, U.K., in From 2006 to 2008, he was a Research Assistant in the Department of Electronic and Electrical Engineering, UCL, where he has been a Research Associate in the Analog and Biomedical Electronics Research Group since His main research interests include analog and mixed-signal integrated-circuit design for biomedical applications, neuroprostheses, and microelectronic sensor design.

13 JIANG et al.: A STIMULATOR ASIC FEATURING VERSATILE MANAGEMENT FOR VESTIBULAR PROSTHESES 159 Nick Donaldson received the M.A. degree in engineering and electrical sciences from Cambridge University, Cambridge, U.K. From 1977 to 1992, he was with the Medical Research Council, Neurological Prostheses Unit, London, U.K., under the direction of Prof. G. S. Brindley. In that period, his main field of research was the technology and the use of implanted devices for the restoration of useful leg function to paraplegics. Since 1992, he has been Head of the Implanted Devices Group at University College London (UCL), London, U.K. He has been a Principal Investigator for many projects related to implanted devices and functional electrical stimulation. He is a Professor with UCL. His research interests include the development of implanted devices that use natural nerve signals as inputs, especially for preventing incontinence, stimulators of nerve roots, the use of electrical stimulation for recreational exercise of paralyzed legs, and methods to encourage functional neurological recovery after injury.