MIPI I3C Interface Advanced Features

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1 Radu Pitigoi-Aron Principal Engineer, Systems Architect QUALCOMM Technologies, Inc MIPI I3C Interface Advanced Features

2 Outline MIPI I3C intelligent multifeatured interface List of main bus management procedures Timing Control Problems solved, Challenges, Practical implementation aspects Elements of flow control Problems solved, Challenges, Practical implementation aspects 2

3 MIPI I3C Bus Clients 3

4 MIPI I3C Intelligent Multifeatured Interface MIPI I3C supports several communication formats, all sharing a two-wire interface. The two wires are designated and : (Serial Data) is a bidirectional data pin (Serial Clock) can be either a clock pin or a data pin while in certain HDR Modes An MIPI I3C Bus supports the mixing of various Message types: I 2 C-like SDR Messages, with clock speeds up to 12.5MHz Broadcast and Direct Common Command Code (CCC) Messages that allow the Master to communicate to all or one of the Slaves on the I3C Bus, respectively HDR Mode Messages, which achieve higher data rates per equivalent clock cycle I 2 C Messages to Legacy I 2 C Slaves Slave-initiated requests to the Master, for example for In-Band Interrupt or to request the Master role 4

5 MIPI I3C BUS Management Features Dynamic Address Assignment Hot-Join In-Band Interrupt Secondary Master In-Band Hard RESET Timing Control Common Command Codes Error detection and Recovery Elements of Flow Control 5

6 Timing Control Complex applications require several Sensors on a common timeline Synchronous Systems and Events Controlling the sampling moments has the potential of drastically reducing the system energy expenditure Asynchronous Systems and Events The accuracy of the timestamps of events matters The Synchronous and Asynchronous modes can be used independently and concurrently on the same bus and devices 6

7 Synchronous Systems and Events S_RED S_GREEN S_BLUE SENSORS READ NOT IN SYNC ST+DT SYNC Tick [ST] and Delay Time [DT] in-band, via I3C bus ST+DT ALL READ IN SYNC DT SENSORS DATA NOT IN SYNC T_Ph start T_Ph start ALL DATA IN SYNC Sensors sample Sensors sample Sensors sample Sensors sample Sensors sample Sensors sample Sequence Repetition Period Adjustable [0.2 ; 5 sec], 1 sec nominal Sequence repeats 7

8 Synchronous Multiple Transactions I3C START I3C START I3C START I3C START ST&DT Polling Polling or something else Polling or something else I3C messages, on the bus Some I3C transactions START condition is used by the Slaves (sensors) for adjusting their (sensors ) internal timers ST&DT Polling Sensors Sample unsynchronized Sensors Sample unsynchronized Sensors Sample unsynchronized Sensors Sample unsynchronized Sync Tick [ST] & Delay Time [DT] ST if validated by DT Sensors Sample in sync Sync Tick [ST] & Delay Time [DT] ST if validated by DT T_Ph start, calculated from ST and DT Refresh/Adjust Sensor s Timer Sensors Sample in sync Sensors Sample in sync T_Ph start, calculated from ST and DT Sensors Sample in sync DT between ST and T_Ph Start Sequence Repetition Period Adjustable [0.2 ; 5 sec], 1 sec nominal ST&DT to next ST&DT delay Adjustable [0.2 ; 5 sec], 1 sec nominal Each ST&DT instantiation includes Timer Error Correction data Sequence repeats 8

9 Synchronous Common Command Codes SETXTIME CCC Configuration messages ODR (Output Data Rate) TPH (Procedure Repetition Time) TU (Time Unit) Run Time messages SYNC Tick [ST] Delay Time [DT] 9

10 Asynchronous Systems and Events Four Async Modes Basic Async Mode 0 Enhanced Async Mode 1, 2 and 3 SETXTIME is the CCC The defining byte selects the running mode 10

11 Async 0 Time Diagram Timeline SENSOR SAMPLE 1 ST HW EVENT 2 ND HW EVENT MTS Master Timestamp, expressed in MASTER s time units SENSOR Sensor s SCNT1 Start Sensor Initiates IRQ Sensor s clock for timer/counter Sensor s CNT2 Start S captured Master s MCNT2 Start Sensor s clock for timer/counter SC2 captured MREF Master Reference, i.e. Start of Master s secondary counter, MCNT2 M, MC2 Master s counters values, captured at the corresponding HWSE events. MASTER Master s Timestamp MTS Master s clock / virtual clock for timer/counter Virtual M MREF captured Master s clock for timer/counter MC2 captured S, SC2 Slave s counters values, captured at the corresponding HWSE events. MTS = MREF MC2 S/SC2 11

12 Async 0 on SDR SENSOR SAMPLE 1 ST HW EVENT 2 ND HW EVENT SENSOR Sensor s SCNT1 Start Sensor Initiates IRQ Sensor s Clock for Timer/Counter Sensor s SCNT2 Start S Captured Sensor s Clock for Timer/Counter SC2 Captured MASTER Master s Timestamp MTS Master s MCNT2 Start MREF Captured MC2 Captured Virtual M First Rising Edge After ACK or T Bit LEGEND Bus Management I3C SDR ISR Read S Byte1 Master to Slave R ACK T Slave to Master T Bit - Transition I3C BUS S S_ADD R IBI R ACK ISR Read T S Byte1 T S Byte2 T SC2 Byte1 T 12

13 Elements of Flow Control The Transmitter drives actively the data lines on HDR-DDR and on HDR-TSx The Receiver might need to end the transaction The bus needs to provide the opportunity for the Receiver to change the state of a line, in a pre-established way 13

14 HDR-DDR Transactions HDR-DDR Preamble Values Preamble Value and Interpretation Context 2 b00 2 b01 2 b10 2 b11 After EnterHDR Command Word follows - - After Read CMD - Slave ACK, Data follows Slave NACK, Aborted After Read DATA Reserved for Future Use CRC Word follows Master Aborts, Slave yields. Master drives second 0. Data follows. Master does not drive second bit. After Write CMD After Write DATA - Data follows - CRC Word follows - Data follows 14

15 HDR-DDR Slave controls DDR READ command Beginning of new DATA Word Beginning of HDR Restart or HDR EXIT Pattern CCC DATA [15:0] PAR1 PAR0 PRE1 PRE0 D0.7 D0.6 CCC DATA [15:0] PAR1 PAR0 PRE1 PRE M_ M_ CCC DATA [15:0] PAR1 PAR0 PRE1 PRE0 D0.7 D0.6 0 C2 CCC DATA [15:0] PAR1 0 PAR0 PRE1 PRE0 tsco tsco

16 HDR-DDR Master Controls DDR READ Transaction [1] Beginning of new DATA Word Beginning of HDR Restart or HDR EXIT Pattern DATA [15:0] PAR1 PAR0 PRE1 PRE0 D0.7 D Early ending with no CRC M_ M_ D0.7 D0.6 0 C2 0 tsco tsco

17 HDR-DDR Master Controls DDR READ Transaction [2] Beginning of new DATA Word Beginning of CRC 1'b1 1'b1 1'b0 1'b0 DATA [15:0] PAR1 PAR0 PRE1 PRE0 D0.7 D0.6 Early ending with CRC M_ M_ D0.7 D0.6 0 C2 tsco 0 CLK_CR CLK_CRC2 CLK_CRC3 tsco

18 HDR-DDR Slave Requests DDR WRITE Termination [1] Beginning of new DATA Word Beginning of HDR Restart or HDR EXIT Pattern D0.7 D Early ending with no CRC M_ M_ D0.7 D0.6 0 C2 0 tsco tsco

19 HDR-DDR Slave Requests DDR WRITE Termination [2] Beginning of new DATA Word Beginning of CRC 1'b1 1'b1 1'b0 1'b0 D0.7 D0.6 Early ending with 0.7 X CRC VDD M_ M_ D0.7 D0.6 0 C2 tsco 0 CLK_CR CLK_CRC2 CLK_CRC3 tsco

20 HDR-TSx Master Controls S2M Data Transfer Beginning of new DATA Word Beginning of HDR Restart or HDR EXIT Pattern T1 T0 T1 T0 T11 T10 T M_ M_ T1 T0 T11 T10 T9 T1 T0 C2 C

21 HDR-TSx Slave Controls the M2S Data Transfer Beginning of new DATA Word Beginning of HDR Restart or HDR EXIT Pattern T1 T0 T1 T0 T11 T10 T M_ M_ T1 T0 T11 T10 T9 T1 T0 C2 C

22 ENDXFER CCC Early Termination Setup and Invocation Defining Bytes 0x7F SET/GET Repetition Interval for HDR-TSx 0x55 Initiates the HDR-TSx with Ending Data Transfer Procedure Enabled 0xF7 SET/GET CRC Index for HDR-DDR 0xAA Initiates the HDR-DDR with Ending Data Transfer Procedure Enabled S Sr 7 h7e / W / ACK ENDXFER CCC / T Defining Byte / T (Optional) Data / T Sr P Describes Slave ENDXFER has ended Next CCC S Sr 7 h7e / W / ACK ENDXFER CCC / T Defining Byte / T Sr Slave Addr / RnW / ACK Data / T Sr 7 h7e / W / ACK Sr P Slave Addr / RnW / ACK P Repeat for additional Slaves on ENDXFER 22

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