Evaluation of FPGA Design and Implementation of Improved Systolic Architectures for Variable Length Median Filters

Transcription

1 Evaluation of FPGA Design and Implementation of Improved Systolic Architectures for Variable Length Median Filters Asmaa Hameed Rasheed Lecturer College of Engineering, Baghdad University Baghdad, Iraq. Abstract FPGAs are efficiently used for real-time systems implementation according to their ability of parallel processing. This paper evaluate the performance of an efficient FPGA based hardware design of improved systolic architectures for median filtering algorithms with different window size to check hardware complexity optimized with filter performance and output quality. Several techniques can be used to implement the sorting process which is the core of median filter architecture to pipeline filter performance that leads to reduce execution time for filtering process. These different architectures are developed to simplest filter structure and minimize hardware complexity. A windowing technique is used to mask specified number of pixels of an image, according to the median filter length. The present work is tested for 3 different window sizes 3*3, 5*5 and 7*7. The 9*9 is also tested for time constraints. Filtering processing was applied for gray image of size 250*400, but this approach can be used for any size of gray images without any reprogramming or reconfiguring the FPGA kit. The implementation created with cooperative of MATLAB package and FPGA platform with aid of System Generator Technique. Xilinx software ISE 14.7 with Spartan3-700A and its matched version of MATLAB R2013a are dependant in the present work. Keywords: Median filter, FPGA, System Generator, Noise cancellation, Data processing. INTRODUCTION The Gaussian and impulse noise are the most common noise types that affect digital images [1], [2]. The impulse noise occurred due to different image system processing such as scanning, digitizing, and transmission through channels. Salt & pepper noise, is a special type of impulse noise, when corrupt an image, the affected pixel will take the minimum or maximum gray level which are 0 and 255 respectively. Salt & pepper noise cancellation can be achieved using the median filter. This filter behaves well at lower percentages of noise densities, but an advanced version of median filter, such as adaptive median and weighted median will be needed with large noise densities [3], [4], [5]. The main obstacle for these advanced versions of median filters is that their designs cannot normally meet real time processing requirements. Sliding window always used which moves systematically over the entire noisy image depending on the stationary feature of this image [6]. FPGA s are used in a very wide applications of digital image processing including image filtering [7]. This is due to FPGA s features that make it the most candidate choice for many real time processing, these features are: flexibility, reconfigurablity, and parallelism. The implementation of image filtering on PC takes more time because the execution of all operations is in sequential order. FPGAs supports parallelism [8], that accelerates real time processing and then lead to high speed response compared to the personal computer. The internal structure of FPGA's consists of a grid of programmable logic cells supported by a programmable interconnection lines and switches that provide communication media for these logic cells. I/O cells that arranged around them, provides an interface between external pins and interconnection lines of the used chip [9], [10]. In fact, programming an FPGA is specifying logic function to each cell and to each interconnection lines [11], [12]. IMAGE FILTERING TECHNIQUES Image denoising is one of the most applicable areas in digital image processing. Salt & pepper noise is one of the most noise type that is produced with image processing systems, such as image storage, or transmission. A suitable denoising method, depending on filtering process must be used to eliminate noise effects and must not affect the other original details of the image. Here image filtering system is used for noise cancellation while retaining edges and image characterizing feature. Median Filter The median filter is a nonlinear digital filter, effectively used for impulse noise cancellation. Figure 1 shows the probability density function of impulse noise. The affectivity of median filtering referred to its ability to preserve edges of the images and many useful details while removing or at least eliminating noise under certain conditions. This filter is a local filter that produces the middle element of a sorted values of a number of pixels taken from a specified window. The filtered pixel depends on its nearby neighbors to decide if it is a good representative of its surroundings [13], so the filter replaces the value of the pixel with the median of a specified window. The median filter processing can be summarized by following steps: firstly select specified window, then it sorts the pixels in ascending or descending order. The second processing step 1908

2 of this filter, it gives the median value of the sorted elements. It is preferable that the number of pixels is odd to select the middle value as median. But when the number of pixels is even it takes the average of two middle pixels as median. The last step of filter processing is to place the median at the centre of the selected window. These processes are done for all image pixels by moving the pixel pointer horizontally and vertically. H/W IMPLEMENTATION OF MEDIAN FILTER Median filter implementation include several processing stages. one of these stages is the image preprocessing in which the image must be converted into 1-dimensional form, a k*k processing window is required to scan the images, so a k*k window generator is used which imitates a processing window, generating (k*k) pixels at a time as it scans the entire image, this (k*k) pixels are fed in a parallel manner. k is determined according to the used median filter length. The second and the most important stage consist of hardware implementation of median filter. The design and hardware implementation of this filter need cooperative method between MATLAB simulink and XILLINX system generator. The final stage in H/W implementation of median filter is the post image processing. Since the output of the system will be floating point, it needs to be converted to unsigned integer of 8-bit, because data type of image pixels are unsigned integer taking up 8 bits of data, the output pixel will be an individual pixel, which must be converted back to 2D data using the reshape block. The image is now ready for display. These processing can be summarized as follows: 1. Read the input gray scale image. 2. Compute the size of an input image, and then pad the image with zeros on all sides of the image. 3. Initialize the pixel pointer to points to the first pixel. 4. One additional iteration is applied to eliminate any unnecessary noise at edges. 5. Exclude the padded zeroes on all image sides. When the simulation complete, the system generator block are use with select type of FPGA kit to generate a block represent all Xilinx blocks in the last simulation that represent the real kit. Figure 2 shows the H/W design flow using system generator. The median filter is implemented with different window size: 3x3, 5x5, and 7x7 to compare median filter performance with these different sizes, and to ensure the effect of increasing or decreasing the window size on the complexity of filter hardware design and on filtered image quality. METHODS OF MEDIAN FILTER DESIGN Median filter can be implemented in different methods including optimized structure using simulink tools. Traditional Simulink Design of Median Filter The classical structure using one simulink block as shown in Figure. In this structure the VHDL code do all the design steps required for median filter implementation. The Median of (k*k) pixels can be calculated using the traditional sorting method, which is done by arranging the pixels in ascending or descending order and picking the middle value as the median, see Figure 3. Or it can be done by calculating the distance between the pixels using the distance norms. The pixel with the minimum distance to all the pixels is the median [11]. An FPGA system of 3*3 median filter design using traditional method is shown in figure 4. The VHDL S/W inside the block box do all the sorting process to produce the median value as a filter output. Optimized Simulink Design of Median Filter FPGAs are used for efficient median filter design based on different noval algorithms [14], [15], [16], [17]. Median filter can be implemented in different optimized structure using simulink tools [18]. In the proposed method, the median is calculated in a different fashion using systolic algorithm [19], [20]. The systolic architecture is done by sub-dividing the nine pixels into three parts and with each parts containing three pixels. The minimum, median and maximum is calculated for each part as shown in figure 9. And again, a maximum from the minimums, a minimum from the maximums and a median from the medians is chosen. And from these three sub-medians, the median is calculated which will be the final median of the nine pixels. This optimized structure shown in Figure 9 consists of seven simulink blocks and most of the processing job done by these blocks using VHDL S/W. Several other optimized structure are developed based on the parallelism of systolic array [21]. The principle structure of three 2-inputs comparators is used as a basic block for large systolic filtering system, which illustrated in figure 10. Each comparator will be considered as a single node for further designs. THE RESULTS The median filter is implemented in different methods and techniques which can be classified mainly as: traditional method systolic architecture techniques. Several systolic architecture are implemented and tested in the present work. The optimized systolic architecture for 3*3 median filter with 41 nodes is shown in figure 11. Developed systolic architecture of 27,21, and 19 nodes are shown in figures 13, figure 15 and figure 17 respectively. The execution time for each selected window is obtained with other performance factors of median filter is illustrated in table

3 Design summary of 41 nodes, 27 nodes, 21 nodes, and 19 nodes designs are shown in table 4, table 5, table 6, and table 7. The required time for 3*3 median filter in which each selected window contain 9 pixels for the traditional and optimized systolic techniques are summarized in table 8. Number of used LUTs for each design of 3*3 median filter is also shown in Table 8 besides to peak usage memory for each design. For 3*3 median filter, its clear that the execution time is reduced effectively from ns for the single window with traditional method to ns with the proposed systolic architecture technique. And if the execution time for the hole image is obtained then the efficiency of the proposed technique will be very clear. The design summary for 5*5 median filter is shown in Table 9 while a comparison between traditional design method and systolic array architecture, for performance factors of 5*5 median filters, is well illustrated in Table 10. The implemented system is tested with the image of Scientist Albert Einstein of size 250x400 which has total execution time of 91 ms with traditional method while it takes 68.6 ms with improved systolic architecture that illustrates the highly benefits of the proposed technique. The tested image is a flower image of size 250x400 with salt and pepper noise of noise density d= Figure 21 shows the original clean image and the noisy image is shown in Figure 22. The implemented median filter of window size 3x3 and 5x5 is applied to the chosen tested image with different values of noise density. Filtered images of 3x3 and 5x5 median filters are shown in Figure 23 and Figure 24 respectively. CONCLUSION To meet real time processing requirements the execution time must be reduced as minimum as possible. Since the median filter represent the most important part in any image denoising system, a special attention must be given to its design and implementation. As its clear from the results, the execution time for median filter is considerably high with traditional design method. But with systolic array architecture the processing speed is highly improved and the execution time becomes 75 % from the execution time of traditional design. The main weakness of the systolic array architectures design that it needs more hardware compared with traditional design method as its clear from the 41 nodes systolic array design of median filter. traditional method needs 36 comparators while the systolic design needs 41 comparators. As well as traditional method needs 656 LUTs while the 41 nodes systolic design needs 715 LUTs. This hardware cost problem appeared at the first attempt of median filter systolic design only which includes 41 nodes for 3*3 median filter design, but this problem resolved later by optimizing the systolic array design to 27 nodes, 21 nodes and 19 nodes. In fact the number of nodes, that reduce effectively the used hardware, can be reduced further to reach to 9 nodes for 3*3 of median filters. While reducing the hardware complexity of systolic array architecture, the execution time is improved also to give excellent overall filter design performance parameters. The peak memory used take its chance of improvement also to become less and less with the optimized systolic array for median filter design. From the execution time charts its obvious that the processing time increased exponentially with increasing window size of the median filter. The execution time is increased too much with increasing window size as well as the used hardware to over the FPGA available components limit, but for high noise density the large window length become essential demands. Table 1: Hardware Design Summary of 3*3 median filter of traditional method. Device Utilization Summary Logic Utilization Used Available Utilization Note(s) Number of 4 input LUTs ,776 5% Number of occupied Slices 344 5,888 5% Number of Slices containing only related logic % Number of Slices containing unrelated logic % Total Number of 4 input LUTs ,776 5% Number of bonded IOBs % IOB Flip Flops 8 Number of BUFGMUXs % Average Fanout of Non-Clock Nets

4 Table 2: Hardware Design Summary of 5*5 median filter of traditional methods. Device Utilization Summary [-] Logic Utilization Used Available Utilization Note(s) Number of 4 input LUTs 5,424 11,776 46% Number of occupied Slices 2,854 5,888 48% Number of Slices containing only related logic 2,854 2, % Number of Slices containing unrelated logic 0 2,854 0% Total Number of 4 input LUTs 5,424 11,776 46% Number of bonded IOBs % IOB Flip Flops 8 Number of BUFGMUXs % Average Fanout of Non-Clock Nets 4.35 Table 3: Design criteria of different window sizes of median filter (Traditional method). Performance Window size Used LUT Max memory usage MB Max Clk Time µs 3* * * Table 4: Hardware Design Summary of 3*3 median filter structure of 41 nodes Device Utilization Summary Logic Utilization Used Available Utilization Note(s) Number of Slice Flip Flops 80 11,776 1% Number of 4 input LUTs ,776 6% Number of occupied Slices 395 5,888 6% Number of Slices containing only related logic % Number of Slices containing unrelated logic % Total Number of 4 input LUTs ,776 6% Number used as logic 715 Number used as a route-thru 5 Number of bonded IOBs % Number of BUFGMUXs % Average Fanout of Non-Clock Nets

5 Device Utilization Summary Table 5: Hardware Design Summary of 3*3 median filter structure of 27 nodes Logic Utilization Used Available Utilization Note(s) Number of Slice Flip Flops 64 11,776 1% Number of 4 input LUTs ,776 4% Number of occupied Slices 269 5,888 4% Number of Slices containing only related logic % Number of Slices containing unrelated logic % Total Number of 4 input LUTs ,776 4% Number used as logic 485 Number used as a route-thru 3 Number of bonded IOBs % IOB Flip Flops 8 Number of BUFGMUXs % Average Fanout of Non-Clock Nets 3.65 Table 6: Hardware Design Summary of 3*3 median filter structure of 21 nodes Device Utilization Summary Logic Utilization Used Available Utilization Note(s) Number of Slice Flip Flops 48 11,776 1% Number of 4 input LUTs ,776 3% Number of occupied Slices 227 5,888 3% Number of Slices containing only related logic % Number of Slices containing unrelated logic % Total Number of 4 input LUTs ,776 3% Number of bonded IOBs % IOB Flip Flops 24 Number of BUFGMUXs % Average Fanout of Non-Clock Nets

6 Device Utilization Summary Table 7: Hardware Design Summary of 3*3 median filter structure of 19 nodes Logic Utilization Used Available Utilization Note(s) Number of Slice Flip Flops 48 11,776 1% Number of 4 input LUTs ,776 3% Number of occupied Slices 224 5,888 3% Number of Slices containing only related logic % Number of Slices containing unrelated logic % Total Number of 4 input LUTs ,776 3% Number used as logic 390 Number used as a route-thru 2 Number of bonded IOBs % IOB Flip Flops 24 Number of BUFGMUXs % Average Fanout of Non-Clock Nets 3.62 Table 8: Design criteria of median filter using systolic array architecture. Used LUT Peak Memory Usage MB Max clk Time (ns) Traditional nodes nodes nodes nodes Table 9: Hardware Design Summary of 5*5 median filter with systolic array. Device Utilization Summary Logic Utilization Used Available Utilization Note(s) Number of Slice Flip Flops ,776 1% Number of 4 input LUTs 7,080 11,776 60% Number of occupied Slices 3,713 5,888 63% Number of Slices containing only related logic 3,713 3, % Number of Slices containing unrelated logic 0 3,713 0% Total Number of 4 input LUTs 7,088 11,776 60% Number used as logic 7,080 Number used as a route-thru 8 Number of bonded IOBs % Number of BUFGMUXs % Average Fanout of Non-Clock Nets

7 Table 10: Performance factors of 5*5 median filter with different design methods. Traditional Systolic Used LUT Max memory usage Max Clk Time Simulink Algorithm System Generator Block sets VHDL Code Figure 1: Probability density function for impulse noise. Figure 2: Design flow using XSG Sorting order Figure 3: Sorting method for traditional median filter design. Figure 4: Simulink of 3x3 median filter design using traditional method. 1914

8 128 clk o/p=112 Figure 5: Timing diagram for 3*3 median filter using traditional method with sample of 9 pixels. 250 Figure 6: Timing diagram for 5*5 median filter using traditional method Used LUT Max Memory Usage Max Clk Time *3 5*5 7*7 Figure 7: Comparison of performance factors for median filter with different window size. 1915

9 *3 5*5 7*7 9*9 Figure 8: Execution time for median filter with different window size (A) (B) Figure 9: Simulink design of 3*3 median filter using optimized method, (A) : simulink design for median value of nine pixels, (B) : The same model in (A), including Clk to all stages to activate systolic process. 1916

10 Figure 10: Simulink structure of the core of systolic design of median filter. Figure 11: Simulink design of 3*3 median filter using systolic array with 41 nodes. Figure 12: Timing diagram for 3*3 median filter using systolic array of 41 nodes. 1917

11 Figure 13: Simulink design of 3*3 median filter using systolic array with 27 nodes. Figure 14: Timing diagram for 3*3 median filter using systolic array of 27 nodes. Figure 15: Simulink design of 3*3 median filter using systolic array with 21 nodes. 1918

12 Figure 16: Timing diagram for 3*3 median filter using systolic array of 21 nodes. Figure 17: Simulink design of 3*3 median filter using systolic array with 19 nodes. Figure 18: Timing diagram for *3 median filter using systolic array with 19 nodes. 1919

13 Used LUT Max memory usage Max Clk Time Traditional 41 nodes 27 nodes 21 nodes 19 nodes Figure 19: Comparison of 3*3 median filter performance factors for different design techniques. Figure 20: Simulink design of 5*5 median filter using systolic array. Figure 21: Original image. Figure 22: Noisy image, d=

14 Figure 23: Filtered image of 3*3 filter length. Figure 24: Filtered image of 5*5 filter length. REFERENCES [1] A. K. Jain, Fundamentals of Digital Image Processing,Prentice Hall of India, First Edition,1989. [2] R. Gonzalez and R.E. Woods, Digital Image Processing. Reading, MA: Prentice Hall,3rd edition, [3] H. Hwang, R. Haddad, Adaptive Median Filters: New Algorithms and Results, IEEE Trans. Image Processing, Vol. 4, No. 4, 1995, pp [4] S. Singh and N. R. Prakash, Modified Adaptive Median Filter for Salt & Pepper Noise, International Journal of Advanced Research in Computer and Communication Engineering, vol. 3, no. 1, (2014) January. [5] S.S.Tavse, P.M. Jadhav, M.R. Ingle Optimized Median Filter Implementation on FPGA Including Soft Processor IJEATE Volume 2, Issue 8, August 2012). [6] V. Katkovnik, K. Egiazarian and J. Astola, Adaptive Window Size Image De-noising Based on Intersection of Confidence Intervals (ICI) Rule, Journal of Mathematical Imaging and Vision vol. 16, 223±235, (2002). [7] B. Draper, R. Beveridge, W. Böhm, C.Ross and M. Chawathe. "Implementing Image Applications on FPGAs," Internationa lconference on Pattern Recognition, Quebec City, Aug , [8] Linde, A., T. Nordstr-om and M. Taveniku, Using FPGAs to implement a reconfigurable highly parallel computer, FPGA: Architectures and Tools for Rapid Prototyping; Selected papers from: Second International Workshop on Field-Programmable Logic and Applications (FPL 92), Vienna, Austria, Gr-un bacher and Hartenstein Eds. New York: Springer-Verlag, pp , [9] Introduction to Field Programmable Gate Arrays: cas.web.cern.ch/cas/sweden- 2007/Lectures/Web-versions/Serrano-1.pdf [10] Xilinx Inc., FPGA vs. ASIC: sasic.htm#pcs [11] J. Villasenor and B. Hutchings, The Flexibility of Configurable Computing, IEEE Signal Processing Magazine, Sept. 1998, pp [12] S. Hauck, The Role of FPGAs in Reprogrammable Systems, in Proceedings of the IEEE, vol. 86, no. 4, April 1998, [13] T. Huang, G. Yang, and G. Tang, "A fast twodimensional median filtering algorithm", IEEE Trans. Acoust., Speech, Signal Processing, vol. 27, no. 1, pp , [14] Hyeong-Soek Yu, Joon-Yeop Lee and Jun-Dong Cho, A Fast VLSI Implementation of Sorting Algorithm for Standard Median Filters, 12th Annual IEEE International ASIC/SOC Conference Proceedings, [15] K. Benkrid, D.Crookes, A. Benkrid, Design and Implementation of a Novel Algorithm for General Purpose Median Filtering on FPGAs, IEEE International Symposium on Circuits and Systems, Vol. 4, pp. IV-425-IV-428, [16] Gavin L.Bates and Saeid Nooshabadi, FPGA Implementation of a Median Filter, Proceedings of IEEE Speech and Image Technologies for Computing and Tele-communications, Vol. 2, pp vol.2, 1997 [17] Miguel A. Vega-Rodriguez, An FPGA Based Implementation for Median Filtering Meeting the Real-time Requirements of Automated Visual Inspection Systems, Proceedings of the 10th Mediterranean Conference on Control and Automation, July [18] Lu Gang1, Liang Yitao, "The Implementation and Analysis of Fast Median Filter Based on FPGA" Luoyang Institute of Science and Technology, Luoyang, China [19] A. N. Pimpale and Porf. Anoop Khambra, "Optimized Systolic Array Design for Median Filter in Image Filtration", International Journal of Electrical, Electron and Computer Engineering: 46-53(2016). [20] Yueli Hu, Huijie Ji. Research on Image Median Filtering Algorithm and Its FPGA Implementation. IEEE Global Congress on Intelligent Systems, [21] Elmoncef Benrhouma, Meddeb Souad "Study and Design of Median Filter", 2 nd Workshop on signal processing, March 23-24, 2012-Hammamet-Tunisia. 1921