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1 Is Now Part of To learn more about ON Semiconductor, please visit our website at ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

2 AN-6084 Surface Mount Assembly Guideline for WLCSP 1.0x1.5 Introduction The Wafer-Level Chip-Scale Package (WLCSP) is one of the smallest discrete MOSFET devices available in the market. Fairchild s offering comes in two ultra-low profile packages. The first has a profile height of <0.65mm and the other at <0.40mm after board assembly. This lowprofile height makes these two thin packages well suited for use in handheld portable products. WLCSP features a small package termination pitch combined with a low gate charge, low R DS(ON), and excellent thermal performance. This board assembly application notes is written to guide users on how to use this product in their assembly. Package Structure The Fairchild Semiconductor WLCSP comes into the two package sizes shown below. Figure 1. WLCSP 1.0x1.5x0.65mm (Standard WLCSP) and WLCSP 1.0x1.5x0.4mm (Thin-WLCSP) The first package (standard WLCSP) has a total package height of <0.65mm. This package has six solder balls with nominal height and diameter of 0.25mm and 0.31mm, respectively. The ball pitch is 0.50mm. The package body is about 0.3mm thick and 1 x 1.5mm in size. The other WLCSP, the thin WLCSP, has a total package height of <0.40mm. This thin-wlcsp has solder balls with nominal height and diameter of 0.21mm and 0.26mm, respectively, and the package body thickness is only 0.15mm nominal. This is similar ball pitch, package size, pin configuration, and performance to the standard WLCSP, which makes it a direct replacement with the standard WLCSP. Should the thin WLCSP replace the standard WLCSP, adjustments in the component pickand-place machine should be performed to cater to its thin profile. The standard WLCSP uses a SAC381 solder balls, while the thin WLCSP uses SAC105 solder terminations. SAC381 and SAC105 liquefy at temperatures 217 C and 227 C, respectively. These two solder alloys are collapsible at a normal lead-free assembly reflow environment, making the package coplanarity (<0.05mm) and component board placement on the board less critical. These two WLCSP packages are classified MSL1 in IPC/JEDEC J-STD-020 [1] standard, making this package less sensitive to moisture, even to reflow temperatures of up to 260 C. Rev /10/08

3 Board Attributes and Design Guide Land Pattern Design Figure 2 shows the recommended land pattern design for the 1.0x1.5mm WLCSP. In SMD, the Cu pad is larger than the desired land pad size and the land pads are defined by the solder mask opening on the pad [4]. The overlapping solder mask on the copper pads gives the package a higher stand-off height; this is because the solder mask prevents solder from flowing around the pad edges [3]. Although there are some advantages of SMD lands, the major disadvantage is that this is less reliable than when using NSMD lands. An area of high stress is created at the solder mask opening [3]. The notch formed between the solder and solder mask creates a stress concentration point that can be a reliability risk in the field [4]. Another disadvantage is that the photo-imageable process for SMD pads makes the registration for SMD pads less accurate [4]. Solder Mask Opening Figure 2. Recommended Land Pattern for 1.0x1.5 WLCSP For area array packages like the BGA and WLCSP, the typical land pad dimensions are between 80% and 100% of the bump diameter [2]. However, ideally this should be equal to the size of the component ball pad. IPC standards recommend reducing the land diameter by 20% for nominal bump sizes of less than 0.60mm and 25% for nominal bump sizes of greater than 0.60mm [2] [3]. For the thin-wlcsp, the land-pad recommendation is unified with the standard WLCSP. This is to provide the flexibility with the package size to be used without changing their board design. Board-level evaluations of the two package sizes showed excellent performance using this board land-pad design. NSMD SMD Copper Pad Figure 3. NSMD versus SMD Copper Pads SMD Solder Masking, Trace Routing, and Clearance The solder mask opening can be designed as either NSMD (non-solder-mask-defined) or SMD (solder-maskdefined). In NSMD, the copper pad is etched to define the land pattern. The pattern registration is accurate because it is dependent on the copper artwork. NSMD is preferable for this package. The fine-pitch configuration of the package requires a more accurate pattern registration [4]. The absence of solder mask around the solder land allows the solder to flow around the edges of the land, eliminating areas of stress concentrations [3]. This makes the solder joint much wider, potentially giving it longer fatigue life [3]. Figure 4. Sectional View of WLCSP Mounted on an SMD Copper Pads NSMD Figure 5. Sectional View of WLCSP Mounted on an NSMD Copper Pads Rev /10/08 2

4 Use of small trace routings in NSMD land pads is preferable; this prevent solder migration to the traces that can result in lower standoff height of the bumps. A balanced fan-out of traces from land pads in the X and Y direction helps avoid the impact of unintentional component movement as a result of unbalanced solder wetting forces during reflow. The traces are typically 2/3 of the board pad diameter [4]. It is preferred that only one trace should be joined to any NSMD solder land [3]. Typical clearance between the solder mask and the copper pads for a NSMD pad is about 0.075mm [4]. The solder mask thickness should be carefully selected, especially on fine pitch components. A thick solder mask can reduce the gasketing effect between the stencil and the board land pads during solder paste printing, allowing the solder paste to get through small openings between the stencil and the board. In some components, this can result in shorting the solder paste between pads. Typically solder mask thickness is around 20 to 25µm for a liquid solder mask process and around 80 to 100µm when using a dry film solder mask [2]. Micro vias or via-in-pad may also be used. Microvias are created either by a standard drill process or laser ablation. A standard microvia connects the two outermost layers of the board, either in top or bottom side of the board. The size of the hole can be about 0.10mm with land diameter of about 0.30mm [3]. This makes it possible to place via at the center of the solder land with the only noticeable effect being a small dimple [3]. By placing vias directly in the land, the spaces around and in between lands on the outer layers can be used for routing traces [3]. Figure 6. Via-in-Pad (Microvia): Resulting Large Voids Surface Finish The pad-surface finishes that are commonly used are NiAu (electroless nickel immersion gold), OSP (organic solderability preservative), and HASL (hot-air surface leveling). Another finish that is becoming popular is immersion Ag (silver). NiAu is preferable in some applications and fine-pitch packages because of its excellent surface solderability and flatness [14]. OSP is excellent for use with fine-pitch packages and ball grid array (BGA). It has a very low cost and excellent flatness. The thickness of OSP should depend on the resistance of the underlying Cu pad from tarnishing and retention of the solderability of the surface [14]. HASL is the most readily available surface finish. It has superior barrel fill and solderability characteristics [14]. Immersion Ag is a leadfree alternative and has an excellent flatness; however, special handling may be required. Fairchild has no preference on the suitable surface finish for this package. However, reliability tests have been performed on OSP and NiAu surface finishes and, in both finishes, the package passed the qualifying requirements. Board Via With the six solder balls at the periphery of the package, vias can easily be routed at any location around the component (dog-bone design). Clearance and solder masking should be provided to avoid solder migration during reflow. The solder migration may result in insufficient solder on the board land pads, resulting in low standoff of the solder joints. Figure 7. Microvia in Pad: Voiding in Solder Joint Figure 8. Voiding Due to Microvia in Pad Avoided by Solder Paste Printing Technique and Reflow Via-in-pad is known to cause large voids in the solder joints. Flux volatiles trapped in the via cause it to form voids in the solder ball. To prevent this, the vias should be plated until the dimple is completely shut or the via should be filled with a conductive epoxy prior to final plating of the board to cover the hole so the surface appears as a flat pad [4]. However, these methods are process adders in the board fabrication. Another option is to print the solder paste around the via; which prevents flux volatiles from being trapped in the via hole during reflow and allows the melted solder to flow though the via. Rev /10/08 3

5 Fiducials Depending on the accuracy of the component mounter, it may be necessary to provide local fiducials for this package to assist the automatic placement equipment in placing the fine-pitch component. Local fiducials are normally placed diagonally outside the component land pad. Other Board Design Considerations Since the solder joints of BGA and CSP packages are not easily seen by viewing it from the top, alignment legends can be used as a visual indicator for good component placement. Such alignment legends can be silkscreen or copper features on the board outer layer. Sufficient clearance should be provided around the package to facilitate rework [3]. This clearance provides room for the heating nozzle to blow hot air into the package, allowing the solder to remelt and facilitate removal of the package. Typical clearance or keepout area per IPC-9075 is about 2.5mm away from the outer edge of the oven nozzle. In presence of high-profile a component next to this package, the minimum distance needs to be adjusted [2] [3] recommends solder paste overprint from 50µm to 75µm larger than the land for fine-pitch BGA components [2]. Radiused corners of the aperture provide better paste release and facilitate cleaning the stencil after use [2]. IPC-7525 [6] recommends the square aperture for fine-pitch components. The recommended stencil foil thickness is 0.10mm. Calculation of the stencil aspect ratio and area ratio determine the good combination of aperture dimension and foil thickness for optimum paste release. The formulas for calculating these are shown below [6]: Aspect Ratio = Area Ratio = Width of Aperture (W) Thickness of Stencil Foil (T) Area of Pad (W x L) Area of Aperture Wall (T x 2[L+W]) Stencil Design The recommended stencil aperture design is as follows: Figure 9. Recommended Stencil Aperture Design The 0.28x0.28mm square aperture is larger than the recommended land pad. The overprint extends to about 0.05mm from the edge of the land pad. Using an overprint or an aperture larger than the land may be necessary to achieve a good aspect and area ratio. This is desirable to provide a larger print target for component placement and greater adhesion of the component to the board pad prior to reflow; preventing the component from being easily dislodged due to insufficient contact with the paste. IPC- Figure 10. Area Ratio > 0.66 and Aspect Ratio > 1.5 for Optimum Paste Release in Laser Cut Stencils [6] Generally, the aspect ratio should be >1.5 and the area ratio is >0.66 [6]. However, depending on stencil type, the aspect and area ratio may change. Recommended aspect and area ratios for different stencil types are provided in IPC-7525 [6]. Tapering or trapezoidal opening on stencil holes are commonly used to improve the solder paste released during screen-printing; however, this may be dependent on the fabrication process used and manufacturing capability of the stencil vendor [6]. For a chemically etched stencil, this can be specified; for laser cut and electroformed stencils, these are inherent parts of the process and the vendor should be contacted for the dimensions [6]. Tapering on the stencil aperture is usually between 2 to 5. This is achieved by making the PCB contact side larger than the squeegee side. The most common stencils are those fabricated by a laser-cutting method. A laser-cut stencil with a complementary step of electropolishing is recommended to improve solder paste release performance. Rev /10/08 4

6 Fairchild recommends that solder pastes with a no-clean flux be used in the board assembly of the WLCSP packages. The low standoff heights of the solder joints cause difficulty in cleaning the trapped flux residues under the package. Board Assembly Considerations Figure 11. Square Stencil Apertures with Radiused Corners for Good Solder Paste Release The assembly processes for attaching BGA and CSP packages with collapsible bumps are more forgiving than the fine pitch peripheral component types. This is because the package easily self-aligns with the board land pad [3]. On printing on land pads with via, the stencil aperture may need to be designed offset from the actual location of the board pad. The amount of offset recommended is about 50% from the center position. This is to prevent flux volatiles from being trapped in the via holes in the pad, which results in large voids. Offset print allows the liquid solder during reflow to flow to via, without entrapping the flux volatile materials. Solder Paste Solder pastes normally used in board assembly have particle sizes of either Type 3 or Type 4. This is the particle size normally used in printing or stenciling process. As a general rule in selecting the appropriate solder particle size in the solder paste, the particle size should not exceed the aperture width divided by 4.2 [3]. The maximum particle sizes for the different solder paste types are [7] For Type 2 paste, mesh <200 / +325, maximum particle size is 75µm For Type 3 paste, mesh <325 / +500, maximum particle size is 53µm For Type 4 paste, mesh <400 / +500, maximum particle size is 38µm The flux materials in solder pastes that are commonly used are classified as ROL0 (rosin based, low activity, and halide-free) or no-clean solder paste (typically a ROL0 or ROM0) [4]. These solder pastes normally contain about 88 to 90% metal by weight, which is approximately 50% solder by volume. The most common solder alloy for board assembly is the eutectic SnPb solder (63Sn37Pb). With the shift to Pb-free soldering to comply with RoHS requirements, SAC387 (95.5Sn3.8Ag0.7Cu) is gaining popularity [4]. Liquidus temperature of eutectic SnPb solder is 183 C and SAC387 is 217 C. Solder Paste Printing Solder paste printing can be accomplished by stenciling solder paste on to the board pads. Stencil aperture design is presented above. Alignment of the aperture to the pad has been found not to be very critical. Given the board design with solder mask clearance of 0.075mm from the pad edge, the solder paste would align itself with the board pad. Evaluation on a board with 1 ounce copper and solder mask to pad edge clearance of 75 micrometer showed that even with an print offset of 50% from the center, the paste still realigns with board pad, with no solder balling and bridging between pads. Figure 12. Aligned Solder Paste Print on Pad, an Overprint on the Land Pad Figure 13. Solder Paste is Printed Offset from the Land Pad by about 50% Rev /10/08 5

7 For pads with microvia at the center of the land, offsetting the stencil from the land pads by about 50% in either X or Y direction help reduce the voiding in the solder joint. Microvias in pad inhibits flux volatiles from outgasing out of the solder joint, resulting in voids. With solder paste printed away from microvia, the liquid solder can migrate through the contours of the via, allowing it to fill the microvia hole with solder. With mask around the board pad, the solder realign itself with the pads during reflow. Printing parameters should be characterized and optimized to get consistent and uniform printing results. Critical parameters in printing are basically the print, speed, force, stencil-to-board gap, and the separation speed. After paste printing, inspection of the paste is strongly recommended. Figure 14. Aligned Component Placement on Board with Printed Solder Paste Component Placement A 50% misalignment during placement of the WLCSP package on the board is tolerable; the package tends to self-align itself during reflow process. The surface tension of the molten solder pulls the package bumps towards the wettable surface of the board land pad. The placement machine nozzle z-height should have enough over-travel to allow the bumps to be submerged about 50µm (2 mils) or half of the solder paste height to the printed paste to allow the self-centering of the package to work. This also prevents the package from moving or being dislodged during transit from the pick-and-place equipment to the reflow oven [4]. The two most popular methods for package alignment are the package silhouette (look-down camera) and the ball recognition system (look-up camera). In the package silhouette system, the vision system locates the package outline only; while in the ball recognition, the vision system locates the ball array pattern. In ball recognition system, the machine can detect missing balls [4]. Another package silhouette system looks at the side of the package and measures the length and width of the package from a certain distance from its top surface. This determines the center point of the package and position the package in the predefined center point location on the board. This system is normally faster than the other two systems. With the tight tolerance in the dimensions between the package edge and solder ball location of the WLCSP, this system can hasten the placement process. Should the printed paste be offset intentionally from center of the pad, in the case of microvia in pad, it is recommended that component placement should be offset in the same direction as the printed paste. This allows the component adhere to the printed paste and prevents it from being dislodged during handling or transport from the component mounter to the next process (such as an offline placement inspection and reflow). Figure 15. Offset Component Placement on Board, Aligned with Solder Paste Location Because the CSP and BGA packages with collapsible solder balls realign themselves with the board pad during reflow, it is advisable not to correct an offset placement. This can only smear the paste underneath, which can lead to bridging and solder balling. Reflow After component placement on board, the assembly normally goes to reflow. The reflow temperature profile should be based on the recommended profile of the solder paste supplier. In setting up the reflow parameters, care must be taken not to expose the packages to temperatures above the rated temperature. The WLCSP package is tested and qualified to perform reliably up to three reflow passes at the maximum reflow peak temperature of 260 C. Locations of the thermocouple are critical in taking temperature profiles of a board assembly. This should be taken into consideration when creating the reflow profile for the board. Due to variation in the component sizes, the number of components on each area of the board, and board design; there are variations in the thermal masses on the board. This results in wide temperature gradient across the board. Thermocouples should be placed on areas where the temperature-sensitive components are placed to monitor the temperature to which the components are exposed and on areas where high thermal masses exists to guarantee that the components on these areas are exposed to the right reflow temperatures. With the small size of the WLCSP, this package can be heated up during reflow; along with other small components on the board, and their temperatures should be carefully monitored. Rev /10/08 6

8 Figure 16. Standard WLCSP After Reflow The WLCSP is a Pb-free product. The solder balls are collapsible at a temperature between 217 to 227 C. It is best that the reflow temperature profile be above 240 C to collapse the solder bumps during reflow. A sample reflow temperature profile used in the board assembly of the WLCSP is shown below. This has linear temperature ramp to the peak temperature of about 250 C. The reflow profile is based on the recommendation provided by the solder paste vendor. Fairchild s Application Note AN-7528 [8] provides guidelines for the different reflow methodologies for surface-mount devices. Critical conditions that affect the components on the board and the appropriate temperature profile for each reflow technology are presented. The WLCSP package is tested to meet moisture sensitivity level 1 at 260 C peak reflow temperature per IPC/JEDEC J-STD-020 [1]. With this classification, preheating or baking the component to remove absorbed moisture prior to assembly process is not necessary. Figure 17. Thin-WLCSP After Reflow Figure 18. Sample Reflow Temperature Profile Rev /10/08 7

9 Inspection Inspection for this package is relatively difficult in comparison with other leaded packages. With the terminals or solder balls hidden underneath the package, inspection may have to be done with a tilted board. The presence of high-profile components surrounding this package makes inspection more challenging. Inspection using an X-ray machine is the recourse in doing this assembly quality check. A good process assembly should show uniform ball sizes and that there is sufficient spacing between solder balls. Presence of an hour-glass shape solder joint is an indication of insufficient solder volume during assembly, which can cause reliability problems. This structure is not recommended [4]. Figure 19. Board Mounted WLCSP Showing Well-Reflowed Solder Joints A well-reflowed solder joint shows evidence of wetting and adherence wherein the solder merges to the soldered surface forming a contact angle of 90 [6] [7]. In the case of WLCSP, since the solder balls melts during reflow, the solder should merge with the solder ball, forming a continuous surface from the solder on the board pad to the pad on the component side. The solder joints should have a smooth appearance. Occasionally a matte, dull, or grainy solder joint may appear. This can be due to the solder alloy used, the component termination or board pad surface finish, or the soldering process used [9] [10]. Figure 22. Hourglass Shape Solder Joint Transmission X-ray equipment can be used to the detect the presence of voids and defects; like uneven solder ball size, solder bridging, and missing balls. IPC recommends that the voids be controlled to below 25% of the total area [3] [10]. Although large voids do not pose reliability concerns, excessive presence of voids is an indication of poor product design or poor process control [3]. Figure 23. Photo of Component with Solder Bridging Figure 20. X-Ray Photo Showing Uniform Ball Sizes and Spaces Between Solder Joints Figure 24. X-Ray Photo Showing Large Voids in the Solder Joint IPC-A-610 [10] provides the inspection methodology and acceptance criteria for surface mount area array packages like the WLCSP. Figure 21. Cross-Section of WLCSP Rev /10/08 8

10 General Rework Guideline WLCSP Table 1. Recommended Board Rework Methodology for this Package STEP TOOLS/EQUIPMENT GUIDELINE / PROCEDURE Baking Component Removal Land Preparation Component installation Inspection Oven Rework station Heat gun Solder wick Soldering iron Continuous vacuum desoldering system Desoldering tip Solder paste dispenser Low magnification microscope Pick and place machine Reflow oven X-ray machine Low magnification microscope Baking of the board assembly may be necessary, depending on the moisture sensitivity of the board and the other surrounding components. The purpose is to eliminate absorbed moisture on these parts and prevent the damaging effects when subjected to sudden ramp of temperature during removal of the component. Secure the board on the rework station. Preheat the whole board to minimize board warpage when high temperature is applied on the component to be removed. Apply heat into the component using a heat gun. When the solder joint has melted, remove the component immediately using a vacuum nozzle. It is important to note that applying too much heat on the board can also affect the surrounding components, thus it is important to do this process quickly. After the component is removed, remove excess solder from the lands using a continuous vacuum desoldering system and soldering tip. Soldering iron and solder wicking material can also be used. After preparing the lands, install a new component into the board. The old component should be discarded. Installation of the component follows these steps: Solder paste dispensing A solder paste dispensing system should be used to put paste on the lands. Inspection perform inspection to check if sufficient paste is printed on the board. Component placement place the component onto the board either manually or using the work station. Avoid moving the component after placement; this can smear the paste may cause bridging or solder balling. Reflow reflow the board using the standard reflow profile established for the whole board assembly. Inspect the component after reflow using an X-ray machine to check for solder joint anomalies, such as solder bridging, beading, and voids. Rev /10/08 9

11 Board-Level Test on WLCSP Packages The WLCSP packages are being tested to simulate possible field conditions. Tabulated below are the environmental and mechanical stress tests that were performed on these packages and the outcome of the tests [3]. Table 2. Environmental and Mechanical Stress Test Results Test Result / Test Condition / Reference Standard 1.0x1.5x0.65mm WLCSP 1.0x1.5x0.40mm WLCSP Temperature Cycle Test Passed -10 C to +100 C 15min dwell time per hot and cold zones 3-pass reflow (260 C peak temperature) temperature cycles Reference standard: Fairchild s FSC-QAR-0006 [11] Passed -10 C to +100 C 15min dwell time per hot and cold zones 3-pass reflow (260 C peak temperature) temperature cycles Reference standard: Fairchild s FSC-QAR-0006 [11] Drop Test Bending Cycle Test Compression Test Passed Half-sine pulse; 1500G for 0.5ms, simulates a drop height of 1.12 meters 105mm support span 1mm-thick, 4 and 8 layer boards 150 drops Reference standard: JEDEC JESD22-B111 [12] Passed 4 point bend test 110mm support span, 75mm load span 0.18mm deflection, sinusoidal 15 hertz frequency 7.48mm/sec crosshead speed 1mm-thick, 4-layer board 1,000,000 cycles Reference standard: Fairchild s internal standard Passed the package can withstand compressive stress up to >6000 gmf, way above the normal compressive forces any component would be subjected into in board assembly processes. 2.5mm diameter load 0.5mm/min tool speed Reference standard: Fairchild s internal standard Passed -40 C to +125 C 10min dwell time 20 C/min ramp rate 2.35mm-thick, 8-layer board 1000 cycles Reference standard: IPC9701 [5] TBD Half-sine pulse; 1500G for 0.5ms, simulates a drop height of 1.12 meters 105mm support span 1mm-thick, 8-layer board 30 drops Reference standard: JEDEC JESD22-B111 [12] Passed 4 points bend test 110mm support span, 75mm load span 2mm deflection, sinusoidal 1 hertz frequency 1mm/s crosshead speed 1mm-thick, 8-layer board 200,000 cycles Reference standard: JEDEC JESD22-B113 [13] TBD Except for the Temperature Cycle test per FSC-QAR-0006 and Compression test, all the tests performed above used daisy chained components and board. Rev /10/08 10

12 References [1] IPC / JEDEC J-STD-020, Moisture / Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [2] IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard [3] IPC-9075, Design and Assembly Process Implementation for BGAs [4] FSC-QAR-0024, Guideline on the Methodology of Board Level Characterization [5] IPC9701, IPC standard, Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments [6] IPC7525, IPC Standard, Stencil Design Guidelines [7] IPC J-STD-005, Requirements for Soldering Pastes [8] AN-7528, Fairchild Application Notes, Guidelines for Soldering Surface Mount Components to PC Boards [9] IPC/EIA J-STD-001, and EIA Joint Standard, Requirements for Soldered Electrical and Electronic Assemblies [10] IPC-A-610, IPC standard, Acceptability of Electronic Assemblies [11] FSC-QAR-0006, Fairchild Semiconductor General Reliability Requirements [12] JESD22-B111, JEDEC standard, Board Level Drop Test Method of Components for Handheld Electronic Devices [13] JESD22-B113, JEDEC standard, Board Level Cyclic Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Devices [14] IPC-2221, Generic Standard on Printed Board Design Applicable FSIDs: FDZ1905PZ, FDZ191P, FDZ192NZ, FDZ193P, FDZ197PZ, and FDZ391P. Rev /10/08 11

13 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Rev /10/08 12

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