Pushing Ultra-Low-Power Digital Circuits

Pushing Ultra-Low-Power Digital Circuits into the Nanometer Era David Bol Microelectronics Laboratory Ph.D public defense December 16, 2008

Why ultra-low power? Low-power circuits Performances: 1 GOp/s Power < 1 W High-performance circuits Performances: 10 GOp/s Power < 100 W 2

Hearing aids

ULP digital circuits Hearing aids and biomedical RFID tags Wearable electroncics Ultra-low-power circuits Performances: 10 k - 10 MOp/s Power < 1µW Smart Dust [Berkeley] Sensor networks 3

Pushing Ultra-Low-Power Digital Circuits into the Era David Bol Microelectronics Laboratory Ph.D public defense December 16, 2008

Moore s law (1965) Every 18 months : x 2 [Intel] 5

Moore s law today 6

Moore s law Moore s law without technology scaling Moore s law with technology scaling 7

Technology scaling Clock frequency 1 GHz 130n 2008 45nm 100 MHz 10 MHz 1 MHz 10 4 10 5 10 6 10 7 10 8 10 9 Transistor count 8

Technology scaling Clock frequency 2008 45nm 130n 1 GHz 100 MHz 10 MHz ULP circuits 1 MHz? 104 105 106 107 Transistor count 108 109 8

Trend in ULP digital circuits 400 Last chips [IEEE ISSCC 08]: 65nm Technology node [nm] 300 200 100 ITRS Ultra-low-power 0.3V µc for biomedical applications [Kwong] 0 1998 2000 2002 2004 2006 2008 Year 65nm Ultra-low-power 0.32V motion estimator [Kaul] 9

Outline Motivation Basics: energy consumption of ULP digital circuits Impact of technology scaling Reaching E min Reducing E min ULP logic style for high-temperature applications Roadmap for nanometer ULP circuits

Sources of power dissipation V dd 1/f clk IN 0 I on OUT 1 C L 10

Sources of power dissipation V dd 1/f clk IN 1 OUT I on 0 C L 10

Sources of power dissipation V dd 1/f clk IN 1 OUT I on 0 C L P dyn ~ f clk x C L x V dd 2 10

Sources of power dissipation V dd IN OUT 1 0 I on C L P dyn ~ f clk x C L x V dd 2 kg 11

Power consumption Minimum V dd [V] Power [W] 1.5 1 0.5 10-3 10-5 10-7 10-9 8-bit RCA multiplier in 130nm technology ULP applications = subthreshold logic Functional limit Speed limit 0 10 4 10 5 10 6 10 7 10 8 10 9 P dyn ~ f clk x C L x V dd 2 Frequency scaling Frequency/voltage scaling 10 4 10 5 10 6 10 7 10 8 10 9 Throughput [Op/s] 12

Sources of power dissipation V dd IN OUT 1 0 I off = I leak C L P stat ~ V dd x I leak 13

Minimum V dd [V] Power [W] 1.5 1 0.5 10-3 10-5 10-7 10-9 Power consumption 8-bit RCA multiplier in 130nm technology ULP applications = subthreshold logic Functional limit 0 10 4 10 5 10 6 10 7 10 8 10 9 P dyn ~ f clk x C L x V dd 2 ULP applications Speed limit Frequency/voltage scaling P stat = V dd x I leak 10 4 10 5 10 6 10 7 10 8 10 9 Throughput [Op/s] 14

Energy consumption Minimum V dd [V] Energy per operation [J] 1.5 1 0.5 10-12 10-13 10-14 8-bit RCA multiplier in 130nm technology ULP applications = subthreshold logic Functional limit 0 10 4 10 5 10 6 10 7 10 8 10 9 ULP applications E stat E min Speed limit E dyn ~ C L V dd 2 Frequency/voltage scaling 10 4 10 5 10 6 10 7 10 8 10 9 Throughput [Op/s] 15

Impact of technology scaling Gate Gate Source T ox L T ox, L, W ~ 1/S Drain Source W L Drain T ox Gate W Source L Drain L 16

Impact of technology scaling I on Speed Reduce V dd kg C L I leak E stat ~ I leak V dd 2 E dyn ~ C L V dd 2 Variability! T ox Gate W Source L Drain L 17

Variability 130nm technology Gate Gate Source Drain Source Drain Continuous doping 45nm technology Straight line edges Gate Source Drain Rough line edges Discrete dopants 17

Impact of technology scaling 1.5 8-bit RCA multiplier Minimum V dd [V] Energy per operation [J] 1 0.5 10-10 10-11 10-12 10-13 10-14 Functional limit 0 10 4 10 5 10 6 10 7 10 8 10 9 Variability 130nm 45nm Speed limit 130nm 45nm E dyn 10 4 10 5 10 6 10 7 10 8 10 9 Throughput [Op/s] 18

Impact of technology scaling 1.5 8-bit RCA multiplier Minimum V dd [V] Energy per operation [J] 1 0.5 10-10 10-11 10-12 10-13 10-14 Functional limit 0 10 4 10 5 10 6 10 7 10 8 10 9 ULP applications E stat 130nm 45nm Speed limit 130nm 45nm E dyn 10 4 10 5 10 6 10 7 10 8 10 9 Throughput [Op/s] 18

Impact of technology scaling Energy per operation x10! Energy per operation ULP applications E min 130nm 1 45nm 2 Throughput 19

What if you have to scale? Scale, scale, scale Famous Intel co-founder DIY

Outline Motivation Basics: energy consumption of ULP digital circuits Impact of technology scaling 1 Reaching E min Reducing E min 2 ULP logic style for high-temperature applications Roadmap for nanometer ULP circuits

1 Technology versatility High-Performance/ General-Purpose 45nm technology Short L g Thin T ox Low V t Mid V dd Low-Power High I on High I leak Mid L g Mid T ox High V t High V dd Low I on Low I leak 21

1 Technology selection 0.8 8-bit RCA multiplier in 45 nm technology Minimum V dd [V] Energy per operation [J] 0.6 0.4 0.2 10-12 10-13 10-14 0 10 4 10 5 10 6 10 7 10 8 LP high-v t GP ULP applications LP high-v t GP 10 4 10 5 10 6 10 7 10 8 Throughput [Op/s] General- Purpose Low- Power 22

Dual-V t assignement Std-V t Non-critical path Register Register Non-critical path clk clk 23

Dual-V t assignement Std-V t Register High-V t Non-critical path Register Non-critical path clk High-V t clk 23

Dual-V t assignement A Mult B Critical path IN High-V t OUT Std-V t OUT Inefficient Maximum N 40 30 20 10 Typical With variability 7 8 2 3 27 11 32 19 0 0.2 0.4 0.6 0.8 1 1.2 V dd [V] N 24

1 Circuit adaptation Energy per operation model actual Global process variations Temperature variations Modeling errors Device aging +40% +90% target throughput 25

1 Circuit adaptation target throughput 25 actual adapt. model Energy per operation

1 Circuit adaptation 0.5 8-bit benchmark multiplier in 45 nm LP technology 0.6 adapt actual target throughput V dd [V] 0.4 0.3 0.3 0-0.3 V BB [V] 0.2-0.6 0.1 1 10 V dd V dd -V BB V BB Norm. energy per op. 2 1.8 1.6 1.4 1.2 1 +70% ASV (V BB =0V) ABB (V dd =0.35V) 0.8 0.1 1 10 Norm. throughput 26

1 Circuit adaptation 0.5 8-bit benchmark multiplier in 45 nm LP technology 0.6 V dd actual adapt target throughput V dd -V BB V BB Minimum V dd [V] Norm. energy per op. 0.4 0.3 0.3 ASV (V BB =0V) -0.3 ABB (V dd =0.35V) 0.2 0.1 1-0.6 10 2 1.8 1.6 1.4 1.2 1 ABB better ASV better 0 Minimum V BB [V] 0.8 0.1 1 10 Norm. throughput 26

1 Circuit adaptation 0.5 8-bit benchmark multiplier in 45 nm LP technology 0.6 adapt actual target throughput Reverse body bias is fine in 45 nm LP technology Problem in 45 nm GP! What at 32 nm? Minimum V dd [V] Norm. energy per op. 0.4 0.3 0.3 ASV (V BB =0V) -0.3 ABB (V dd =0.35V) 0.2 0.1 1-0.6 10 2 1.8 1.6 1.4 1.2 1 ABB better ASV better 0 Minimum V BB [V] 0.8 0.1 1 10 Norm. throughput 26

E min modeling 90nm 45nm [Hanson, IEEE TED, pp. 175-185, 2008]

Evolution of E min E min [fj] 60 50 40 30 20 10 0 C L S 2 130nm 90nm 65nm 45nm New effects in nanometer technologies In all flavors 28

New effects in nanometer technologies 60 New effects: E min [fj] Bad short-channel S 50 C L S 2 40 30 20 10 0 130nm 90nm 65nm 45nm 30 25 20 Var. I gate DIBL S short S long Drain-induced barrier lowering Gate leakage Variability Gate E min [fj] 15 10 5 C L S 2 Source I gate Drain 0 Bulk Bulk opt. DIBL 29

Fully-depleted SOI technology 60 E min [fj] 50 Undoped channel C L S 2 40 30 20 10 0 130nm 90nm 65nm 45nm 30 25 20 Var. I gate DIBL S short S long Gate E min [fj] 15 I gate Source Drain Low variability Low C j Buried oxide 5 C L S 2 C L S 2 10 Substrate Low S, mid DIBL 0 Bulk FD SOI 30

Evolution of E min 60 E min [fj] 50 40 30 20 C L S 2 Optimum bulk MOSFET -40% FD SOI -60% 10 0 130nm 90nm 65nm 45nm 31

High-temperature operation D 10-6 130nm PD SOI technology I leak G S 10-8 Leakage x 100 I leak [A/µm] 10-10 10-12 25 C 200 C 0 0.2 0.4 0.6 0.8 1 V dd [V] 32

Low-leakage SOI technology 1 or 0.5 µm, 5 or 3.3V E stat ~ I leak E dyn ~ C L V dd 2 Die area 33

Standard SOI technology 0.13 µm, 1 V 34

High-temperature operation D 10-6 130nm PD SOI technology I leak G V gs <0 X S ULP transistor I leak [A/µm] 10-8 10-10 10-12 25 C 200 C 0 0.2 0.4 0.6 0.8 1 V dd [V] 35

ULP logic style V DD V DD 1 X2 0.8 V X1 IN OUT IN OUT V OUT [V] 0.6 0.4 V X2 X1 ULP logic style GND Layout in SOI 0.2 Falling Rising input input 0 0 0.2 0.4 0.6 0.8 1 V IN [V] Hysteresis 36

ULP logic style ULP logic style at 200 C: 1000x P stat reduction Long delay max ~ 1 MOp/s 37

ITRS recommendations ULP? [ITRS07]

Technology/circuit specs 1 Reducing E min 2 Reaching E min Technology level Active Circuit level Single device type for all logic gates Low C L, S, DIBL, variability (I 0 ) I gate, I junc < I sub @ 0.3-0.4V Relaxed constraints: C g,sub R s,d,g I gate, I junc mobility Multi-I 0 devices with coarse granularity On-chip I 0 tuning with fine granularity Stand-by I 0 tuning Design-time device selection Run-time adaptive technique Sleep-mode technique High leakage reduction Low impact on activemode operation 39

Technology/circuit roadmap Node Applications 130 / 90 nm 65 / 45 nm 32 / 22 nm High-temperature ULP industrial applications ULP logic style PD SOI (FD SOI) @ GP flavor Reliability issues Reliability issues Standard ULP applications Subthreshold logic Bulk (+ adapt. RBB) (FD SOI) Subthreshold logic Bulk + adapt. RBB FD SOI Economical issues @ GP flavor @ LP flavor ULP mode in LP applications Performance issues Subthreshold logic Bulk opt. + adapt. RBB FD SOI Subthreshold logic FD SOI + UTBOX/DG + adapt. dual-bg bias @ HP/GP flavor @ dedicated flavor Architectural techniques (//, pipe) for meeting throughput constraint 40

Thank you! Any questions? Acknowledgements: s work was funded by FNRS and Walloon region of Belgium.

Energy consumption 10-12 8-bit RCA multiplier in 0.13 µm technology Sub V t Energy per operation [J] 10-13 10-14 10-15 E min E dyn ~C L V dd 2 T del increase E stat =V dd x I leak x T del 0 0.2 0.4 0.6 0.8 1 1.2 V dd [V]