EECS 427 Lecture 13: Leakage Power Reduction Readings: 6.4.2, CBF Ch.3. EECS 427 F09 Lecture Reminders

Transcription

1 EECS 427 Lecture 13: Leakage Power Reduction Readings: 6.4.2, CBF Ch.3 [Partly adapted from Irwin and Narayanan, and Nikolic] 1 Reminders CAD assignments Please submit CAD5 by tomorrow noon CAD6 is due in a week Lecture on Monday 11/2 will be taught by Wei-Hsiang Zhengya will be away on Monday 11/2 for conference Extended office hour on Wednesday: 3 5 pm HW4 (detailed proposal) is due 11/ weeks away You should have completed your schematic design and simulation and started block layouts by then Quiz 2 on Monday 11/ weeks away Your chance to improve your performance in Quiz 1 2 1

2 Seminar Announcement Prof. Borivoje Nikolic, UC Berkeley 11 am on Friday, November 6, 3427 EECS Title: SRAM variability in space and time Large-scale characterization of static and dynamic read stability and writeability Static noise margin distributions and Vmin Effects of random telegraph noise (RTS) and bias temperature instability (BTI) 3 Power and Energy Design Space Constant Variable Energy Design Time Non-active Modules Run Time Active Logic Design Reduced V dd Sizing Clock Gating Leakage + Multi-V T Sleep Transistors DFS, DVS (Dynamic Freq, Voltage Scaling) + 4 2

3 Clock Gating Most popular method for power reduction of clock signals and functional units Gate off clock to idle functional units e.g., floating point units need logic to generate disable signal increases complexity of control logic consumes power timing critical to avoid clock glitches at OR gate output additional gate delay on clock signal gating OR gate can replace a buffer in the clock distribution tree clock R e g disable Functional unit 5 Pipelined Datapath For idle units (e.g., floating point units in Exec stage, WB stage for instructions with no write back operation) Fetch Decode Execute Memory WriteBack PC Instruction MAR I$ D$ MDR clk No FP No WB 6 3

4 Power and Energy Design Space Constant Variable Energy Design Time Non-active Modules Run Time Active Logic Design Architectural Reduced V considerations dd Clock Gating Sizing Leakage + Multi-V T Sleep Transistors DFS, DVS (Dynamic Freq, Voltage Scaling) + 7 Architectural Consideration 8 4

5 Parallel Datapath 9 Pipelined Datapath 10 5

6 Summary 11 Power and Energy Design Space Constant Variable Energy Design Time Non-active Modules Run Time Active Logic Design Reduced V dd Sizing Clock Gating Leakage + Multi-V T Sleep Transistors DFS, DVS (Dynamic Freq, Voltage Scaling)

7 Power and Energy Design Space Constant Variable Energy Design Time Non-active Modules Run Time Active Leakage Logic Design Reduced V dd Sizing Multi-V T Stack effect Clock Gating Sleep Transistors DFS, DVS (Dynamic Freq, Voltage Scaling) 13 Key to reducing power: exploit slack Timing slack is defined at each (output) node in the circuitcu == (Required arrival time (RAT) Latest arrival time (LAT)) Large positive slack means the gate driving the node can be slowed down a lot Negative slack means the timing goal cannot be met (bad) Required arrival time for all primary outputs Fig courtesy Borkar, Intel 14 7

8 Dual-Thresholds Inside a Logic Block Minimum energy consumption is achieved if all logic paths are critical (have the same delay) Use lower threshold on timing-critical paths Assignment can be done on a per gate or transistor basis; no clustering of the logic is needed No level converters are needed 15 V th Assignment Granularity V th assignment can be at different levels of granularity Gate level assignment Pull up network / Pull down network based assignment (half gate) Single V th in pull up or pull down networks Stack based assignment Single V th in series connected transistors Individually assignment within transistor stacks Possible area penalty (see right) Design rule constraint for different V t assignment Number of library cells increases with finer control Better leakage / delay trade-off Harder for synthesis tools to handle 16 8

9 Choice of optimal 2 nd Vth Vth usually chosen to be about 100mV Too close together not enough performance differential between the choices Too far high-vth becomes too slow or low-vth too leaky 17 Ref: Wei, VLSI 2000 Power and Energy Design Space Constant Variable Energy Design Time Non-active Modules Run Time Active Leakage Logic Design Reduced V dd Sizing Multi-V T Stack effect Clock Gating Sleep Transistors DFS, DVS (Dynamic Freq, Voltage Scaling) 18 9

10 Stack Effect Leakage is a function of the circuit topology and the value of the inputs V th = V T0 + ( -2 F + V SB - -2 F ) where V T0 is the threshold voltage at V SB = 0; V SB is the sourcebulk (substrate) voltage; is the body-effect coefficient A B V X I SUB A A B B 0 0 V th ln(1+n) V GS =V BS = -V X Out V GS =V BS =0 1 0 V DD -V th V GS =V BS =0 V X V SG =V SB =0 Leakage is least when A = B = 0 Leakage reduction due to stacked transistors is called the stack effect 19 Drain-induced Barrier Lowering Subthreshold leakage current depends on V GS,V BS and V DS V th of a short-channel device decreases with increasing V DS due to DIBL (drain-induced barrier lowering) Typical values for DIBL: a 50 to 120mV change in V th per 1V change in V DS V X reduces the drain-source voltage of the top NMOS, increasing its V th and lowering its leakage V X typically settles to ~50-100mV in steady state V GS = V BS = -100mV and V DS = V DD -100mV, 20X reduction in leakage vs. V GS = V BS = 0V and V DS = V DD 20 10

11 State Assignment # of states grows exponentially with # of gate inputs Only a few of the states have significant leakage Dominant leakage states have only one transistor OFF in any path from V dd to Gnd Exploit this by setting the entire circuit to a low leakage state in standby mode (MUX all registers) Due to logical correlations, can t set all gates to their best states simultaneously A B C Leakage Current Leaking Transistors N1, N2, N N1, N N1, N N N2, N N N3 EECS 427 F09 Lecture P1, P2, P3 21 Power and Energy Design Space Constant Variable Energy Design Time Non-active Modules Run Time Active Leakage Logic Design Reduced V dd Sizing Multi-V T Stack effect Clock Gating Sleep Transistors DFS, DVS (Dynamic Freq, Voltage Scaling) 22 11

12 MTCMOS Active mode ON V DD Virtual V DD Low-V th core... Noise on virtual supply ON Virtual V SS V SS 23 Dynamic Sleep Transistor Standby mode OFF V DD Virtual V DD... Virtual supply collapse OFF Virtual V SS V SS Tschanz, JSSC

13 Sizing of Sleep Transistors Circuits in active mode see the sleep transistor as extra power line resistance The wider the sleep transistor, the better Wide sleep transistors cost area Minimize the size of the sleep transistor for a tolerable ripple on virtual supply (e.g. 5%) Sleep transistor is not free it will degrade performance in active mode Typically by a few percent 25 Sleep Transistor Results A high-vth sleep transistor has to be very wide for low resistance in linear region (MTCMOS in table) A low-vth sleep transistor (non-boosted sleep in table) needs much less area for the same resistance [R. Krishnamurthy] Size given as % area cost Boosted uses a larger gate voltage for the sleep signal 5% delay penalty 26 13

14 Sleep Transistor Layout Tschanz, ISSCC Power and Energy Design Space Constant Variable Energy Design Time Non-active Modules Run Time Active Leakage Logic Design Reduced V dd Sizing Multi-V T Stack effect Clock Gating Sleep Transistors DFS, DVS (Dynamic Freq, Voltage Scaling) 28 14

15 Dynamic Body Bias Active mode Forward body bias Idle mode Reverse body bias Triple well needed 29 Conclusions Lots of recent work on circuit and technology techniques to reduce leakage power Standby mode leakage reduction can be orders of magnitude, but it may lose state and it takes time to switch in and out of standby mode Active mode leakage reduction is a tougher problem, smaller savings (<50% typically), must be ready for inputs to toggle at any time 30 15