Leakage Currents: Sources and Solutions for Low-Power CMOS VLSI Martin Martinez IEEE Student Member No Lamar University 04/2007

Transcription

1 Leakage Currents: Sources and Solutions for Low-Power CMOS VLSI Martin Martinez IEEE Student Member No Lamar University 04/2007 1

2 Table of Contents Section Page Title Page 1 Table of Contents 2 Abstract 3 I. Introduction 3 II. Leakage Current Sources in CMOS circuits 4 III. VTCMOS Circuit Techniques 6 IV. MTCMOS Circuit Techniques 7 V. Conclusions 9 VI. Originality Statement 10 VII. Acknowledgments 10 VIII. References 10 2

3 Abstract The low-power advantages of CMOS technology over other semiconductor technologies were recognized from the onset. The power losses are separable into dynamic and static losses. At first, efforts were focused on dynamic losses because they were dominant. However, as the technology advances into deep sub-micron regions, leakage power dissipation, (mostly) a static loss, increases at a faster rate than its counterpart accounting for 40% or more of total losses in some applications. This paper aims to describe the main sources of leakage losses and two circuit-level techniques that have been presented, that is, Variable- Threshold CMOS (VTCMOS) and Multiple- Threshold CMOS (MTCMOS). I. Introduction At the 2002 International Electron Devices Meeting, the chairman of Intel, Andrew Grove, mentioned that leakage currents are a major limiting parameter in future designs of microprocessors [1]. As such, they have been a hot topic of research in the past decade. These currents are largely static losses but also contribute to dynamic losses [2]. Dynamic power dissipation of a transistor arises from the continuous charging and discharging of the capacitancelike load of digital gates in modern integrated circuits. Part of the reason these losses were the focus for many years is that Moore s Law, the scaling of transistor feature sizes, required the reduction of the voltage supply. Because dynamic power is proportional to the square of this voltage, as shown in Equation 1, reducing the voltage effectively controlled dynamic losses, which were far greater than static losses; total power loss was well controlled. 2 DD P = α CV f + VDD I leak (1) The first term on the left hand side is the dynamic loss, where! corresponds to the percentage of gates actively switching, C stands for the total capacitive load of all gates, V DD is the supply voltage, and f is the operating or clock frequency. The second term corresponds to the static power dissipation where I leak corresponds to the total static leakage current. However, as scaling progresses into the sub-micron region, Moore s Law begins to have a negative effect. The geometry of a CMOS transistor introduces parasitic effects that create leakage currents. These leakage currents become significant in the total power equation and will overtake the dynamic losses. In fact, the International Technology Roadmap for Semiconductors (ITRS) forecasts the 65-nm feature size as the turning point [3]. Another concept to note is that while dynamic power is largely dependent on the switching activity of the circuit, leakage power is dependent on the number and type of transistors in an integrated circuit and the operation state, factors that are independent of switching activity. Recalling Moore s Law and the assumption that there is a doubling of onchip transistors every two to three years, static power consumption is clearly the more dominant power-conscious design parameter of the future. As an example, consider the effects higher power consumption has on portable devices. Higher power consumption leads to temperature raises which, in turn, directly affect battery life because more current is drawn. Higher temperatures also affect circuit operation and reliability. To meet this challenge, newer, more complicated cooling and packaging techniques have to be designed. If battery life is not to be affected, then larger batteries are required which, again, involves a redesigning of packaging. 3

4 This paper is organized in the following manner: section II details the sources of leakage currents and static power dissipation in a MOS transistor; sections III and IV detail Variable-Threshold CMOS (VTCMOS) and Multiple-Threshold CMOS (MTCMOS) circuit techniques for reducing leakage power loss, respectively; section VI presents some final conclusions. II. Leakage Current Sources in CMOS Circuits There are four main leakage currents in a CMOS transistor: A. Subthreshold (weak inversion) leakage (I SUB ) B. Reverse-biased Source/Drain junction leakages (I RB ) C. Gate direct-tunneling leakage (I G ) D. Gate-induced drain leakage (I GIDL ). Figure 1: NMOS Leakage Currents A. Subthreshold leakage The subthreshold leakage current is a drain to source current of a transistor when it operates in the weak inversion region. It is due to the diffusion current of minority carriers in the channel of a MOS structure. When the gate voltage is below V th, the turnon or threshold voltage, an NMOS device is turned off. Ideally, there should be no current flowing in the channel region of the device. However, due to the supply voltage existing across the drain to source region, there is a small current present known as the subthreshold leakage current [4, 5]. Figure 2: I SUB of an NMOS Currently, the subthreshold leakage current, I SUB, is the largest leakage component [3]. This is due to the low threshold voltage value in modern CMOS technology. Equation (2) expresses one version of I SUB : Vth VDD & # = nvt $ VT I! SUB K1 We 1 e $! % " (2). This version is originally presented by Anantha Chandrakasan, William Bowhill, and Frank Fox to show subthreshold leakage current dependence on threshold voltage and supply voltage. K 1 and n are experimentally derived values; W is the device width; V th and V T are the threshold and thermal voltages, respectively. Notice that if I SUB were to grow and build up heat, the thermal voltage would increase and lead to a thermal runaway condition [6]. The magnitude of this current is due to many factors such as temperature, supply voltage, dimensions, and process parameters (which give V th a dominant role) [7]. The following equation illustrates these dependencies for the threshold voltage: V th ( 2φ F + VSB φf ) ηv DS = Vth 0 + γ 2 (3) Here, V th0 is the zero-bias threshold voltage, a manufacturing dependent value; " is the body effect coefficient which is dependent on gate-oxide capacitance, doping concentrations, silicon permittivity and other parameters; # F is the Fermi-level surface potential at threshold; V SB is the source-to- 4

5 body voltage; $V DS shows the Drain- Induced Barrier Lowering (DIBL) effect where $ is the DIBL coefficient. With this in mind, consider how changes in these parameters affect the subthreshold current [2, 7]. V th -Rolloff is associated with Short Channel Effects (SCE's) where the threshold voltage is affected by the transistor s feature size, or channel length. As feature size decreases the threshold voltage should also decrease. The DIBL effect arises in deep submicron technology because the source and drain depletion regions lead to some areas of the channel to be depleted under the gate. This decreases the threshold voltage necessary for strong inversion. The consequence of this phenomenon is that the subthreshold leakage current increases. According to Equation (3) an increase in source-to-body biasing will give a corresponding increase in threshold voltage for small values, an effect known as body bias. The body bias effect will decrease the magnitude of the subthreshold leakage current. Returning to the subthreshold current equation, a couple of methods in which it can be reduced are readily apparent. One method would be to turn off the supply voltage. This approach, however, leads to a loss of state. A second approach would be to increase the threshold voltage. The consequence of this method is a reduction of speed as indicated by Equation (4): α ( VDD Vth ) f VDD (4) where, here,! is an experimentally derived constant that is currently 1.3 [7]. B. Reverse-Bias Source/Drain Junctions Leakage Recalling the structure of an NMOS transistor, a reverse-biased p-n junction exists that is formed by either the source or drain to the substrate when it is off. Although a potential barrier exists, there is a leakage current. It has two components: electron-hole generation in the depletion region and minority carrier diffusion/drift at the edge of the same depletion region. Figure 3: I RB of an NMOS Take, for example, an inverter that has a LOW input. Taking the NMOS drain-tosubstrate (or body) voltage in this case, notice that it is equal to the supply voltage. Internally, this voltage is large enough to create a current. This effect is becoming even more dominant due to the high concentrations of impurity doping used in modern devices. These leakages depend, therefore, on the surface areas of the junctions and the concentrations used [8]. C. Gate direct-tunneling leakage The current due to gate directtunneling leakage is a current tunneling into the gate of the transistor. The mechanisms for this tunneling effect are electron conduction band tunneling (ECB), electron valence band tunneling (EVB), and hole valence band tunneling (HVB). Currently, ECB is the dominant phenomenon. Basically, there is electron tunneling because of the high electric fields that exist across the oxide layer [2]. Consider a simplification of the equations of Chandrakasan, Bowhill, and Fox presented by Nam Sung Kim and Todd 5

6 Austin in Equation (5). I ox = K 2 αtox & VDD # VDD W $ e T! 2 (5) ox % " K 2 and! are experimentally derived values. Increasing the oxide thickness, T ox, will reduce gate leakage currents but this is contrary the scaling trends needed to avoid SCE's, so this is not an option [9]. Additionally, studies have shown that this gate current is increasing at a much faster rate than the subthreshold current with each technology node to the extent that in newer technologies the former surpasses the latter in magnitude. The proposed solution is to use a new material for the oxide, so-called high-k gate insulators. These will ensure that the rate of increase will stabilize [3, 7, 9]. Figure 4: I G of an NMOS D. Gate-Induced Drain Leakage The current due to gate-induced drain leakage (GIDL) is a direct consequence of the high field effect in the drain of a MOS transistor. For example, an NMOS with its gate grounded and drain at the supply voltage potential experiences energy band bending in the drain. This allows electron-hole pairs to be generated by virtue of avalanche effects and band-to-band carrier tunneling. Holes are quickly driven to the body, creating a deep depletion situation. Similarly, electrons are collected in the drain. Together, these effects create the I GIDL current [2]. Transistor scaling has led to doping concentrations that try to control DIBL, mentioned previously. Unfortunately, this has the negative effect of increasing bandto-band tunneling. These, in conjunction with high drain-to-body and drain-to-gate voltages, have exacerbated the I GIDL current. Figure 5: I GIDL of an NMOS E. Total leakage current The total leakage current can be determined from: I leak = I SUB + I RB + I G + I GIDL (6) I G does not exist when a transistor is off in an NMOS. Until high-k gate insulators are used in mainstream processes, it must be considered and designs should be optimized for it. As already noted, I SUB is the dominant component of the leakage currents and the following techniques aim to limit said current. III. VTCMOS Circuit Techniques Earlier, the body bias effect was briefly described. VTCMOS take advantage of this effect. Before going on, a couple of clarifications are in order. A gate can be in either active (dynamic) or stand-by (static) mode. Active mode denotes a switching gate whereas stand-by mode denotes a nonswitching gate. Note that different leakages take place during a switching or nonswitching gate. Given these definitions, VTCMOS is used to avoid leakage in stand- 6

7 by mode. To overcome subthreshold leakage, the threshold voltage can be adjusted. This is accomplished by changing the substrate-bias voltage as noticed in Equation (3). V th ( 2φ F + VSB φf ) ηvds = Vth 0 + γ 2 (3) Usually, the substrate of an NMOS is grounded while the PMOS transistor substrate is pulled up to the supply voltage potential. This keeps source and drain regions reverse-biased with respect to the substrate, ensuring that V th is not influenced by the body effect. In a VTCMOS circuit, this is not the case. The transistors are designed as usual, with a low threshold voltage, to keep speed and performance. However, the substrate-bias voltage, V SB, is not connected to either the supply voltage line or the ground potential line, but instead to a substrate-bias control circuit. Figure 6: VTCMOS with Control Circuit This control circuit will vary the substrate voltages for the gate transistors depending on whether it is operating in its active mode or if it is in stand-by mode. If in the active mode, the control circuit generates the usual potentials, that is, a substrate-bias potential of V BN =0 for the NMOS block and a substrate-bias potential of V BP =V DD for the PMOS block. Since the circuit is operating at a low supply voltage and a low threshold voltage there is low power consumption and no loss of performance. This is effectively the same circuit as conventional CMOS circuit. If the logic gate is stand-by mode, though, the control circuit will produce a lower substrate potential for the NMOS block and a higher substrate potential for the PMOS block. This will, in turn, cause the threshold voltages to increase there-by taking advantage of the body effect. Vth VDD & # = nvt $ VT I! SUB K1 We 1 e (2). $! % " Referring to Equation (2), which is repeated above for convenience, the reader will note that increasing the threshold voltage leads to an exponential drop of the subthreshold leakage current, causing static power dissipation to be greatly reduced. VTCMOS techniques look very promising but there are disadvantages. One disadvantage is the manufacturing process. To be effective, it currently relies on twinwell or triple well CMOS processes to construct the different substrate biases. A second disadvantage is that it may be necessary to put extra power pins if the substrate biases cannot be constructed onchip. However, the control circuit itself requires negligible chip area in comparison to the total chip area. More information can be found in references [7, 10]. IV. MTCMOS Circuit Techniques The second leakage reduction technique to be discussed is the use of MTCMOS circuits. Like VTCMOS, it is used in low-voltage applications when the circuit is in stand-by mode. It is designed using an NMOS and a PMOS transistor that have different threshold voltages than the CMOS logic circuit. The CMOS logic circuit is designed with low thresholds as usual to ensure speed and performance. This 7

8 structure will suffer significant leakage currents during the active mode. The separate NMOS and PMOS transistors will have a high threshold voltage and will not suffer significant leakage currents. These will be used to isolate the CMOS logic circuit by being placed in series with the CMOS structure and in essence will isolate the logic circuit in stand-by mode and prevent any significant leakage power. Conceptually, then, the stand-by transistor design creates a virtual power supply and/or virtual ground. series with the logic block. In practice, only one is necessary and this fact has led to two families of MTCMOS, one using an NMOS, the other a PMOS. The PMOS design, however, is not practical considering that supply voltages will continue to scale down to lower than the typical 0.7 threshold voltage. In addition, NMOS transistors have lower on-resistances, which make it the design of choice. Figure 8: Actual MTCMOS Implementation Figure 7: General MTCMOS Structure In the active mode the circuit behaves as normal because the high threshold transistors, referred to as stand-by or sleep transistors, will be turned on and allow the CMOS logic circuit to perform as designed. In the stand-by mode, the stand-by transistors can be turned off and open circuit the conduction path to the leaky circuit. If an analysis is performed on the total leakage power dissipation, one would find that it would be significantly reduced. This leads to the conclusion that having a low threshold, leaky CMOS logic block for performancecritical functions is an acceptable trade off. Notice that in fact it is not necessary to have both an NMOS and a PMOS both in As far as fabrication is concerned, having transistors with different thresholds can be achieved by changing the channel lengths, the doping profile, or using different oxide thicknesses. This is the fabrication complexity that MTCMOS circuits suffer. A second disadvantage is that the stand-by transistors are connected in series. This adds to the overall chip area and is prone to extra propagation delays caused by parasitic capacitances. Despite these drawbacks, MTCMOS is easier to implement in comparison to VTCMOS circuits because it does not require the complex control circuit. In addition, MTCMOS does not use multiple-well designs as the VTCMOS techniques. Another design challenge is the sizing of the stand-by transistor. While in the active state, there will be a voltage drop across the stand-by transistor which decreases the supply voltage available to the CMOS block. Consequences of this could be reduction of noise margins and increases in 8

9 high-to-low delays. In addition, the threshold of the pull-down network increases because of the body effect. It is possible to meet this problem by using large stand-by transistors but this only adds to the area overhead that already exists as well as the additional dynamic power that it consumes. This in turn leads to the observation that there is a minimum amount of idle time that must pass if there is to be any savings in total power consumption at all. One way to reduce the area and power overhead is to use one large stand-by transistor for several CMOS logic gates. This stand-by transistor will be larger than the one used for each gate, but the total area and power consumed will be less. As Farzan Fallah and Massoud Pedram note, however, finding the optimum size of the large standby transistor requires finding the worst case delay in the circuit and the input vector that causes it. Obviously, simulating this test for large circuits is not feasible. Figure 9: One Large Stand-by Transistor for Several Gates To conclude this discussion of MTCMOS techniques, it is noteworthy to mention that future technologies could extend the number of threshold voltages from two to three or even more. Having multiple numbers of threshold voltages available will introduce new optimization design options and trade offs. Take for example a microprocessor s cache. The second level cache, L2, is larger and slower so there is little gained by using low threshold gates to design it. Using higher threshold transistors will most certainly increase access time to the L2 cache but this can be compensated for by using faster, and hence leakier, transistors for the level one cache, L1, or even increasing its size. The total static power consumption, in the end, will still be lower than the previous design without sacrificing speed. The following references detail the topic of MTCMOS techniques: [2, 7, 9, 10, 11]. V. Conclusions This paper developed the sources of leakage currents and some of the techniques that have been proposed at the circuit level to minimize the static power problem. Clearly, VTCMOS and MTCMOS design techniques can be effective in decreasing leakage current power consumption, yet, just as clearly, one can see that they are not a permanent, universal solution for low power CMOS design. Each technology has its advantages and disadvantages. Research in the field continues to date, with hybrid techniques and different level techniques as well. For example, at the system level, architectural solutions such as paralleling and pipelining have been proposed. Notice also that this paper focused on controlling stand-by leakage currents. A complete solution would also address the active mode leakage problem. A final consideration is that the current targeted by these techniques is the subthreshold leakage current. Although it is the dominant one, the gate direct-tunneling leakage current is also problematic. The introduction of high-k materials can control this current, but as far as the author is aware, these materials are not mainstream available at the time. 9

10 VI. Originality Statement The topics of this paper have come to the fore of research within the past two decades or so. Some of these techniques have been around for a while now and presently, more sophisticated and hybrid solutions are being researched. The author is not an expert in the field and has relied heavily on instruction received in class and resources obtained. The presentation and diction used in this paper, however, are original to the extent that it conforms to literature and is presented in the manner in which the author has understood the material researched. VII. Acknowledgments The author would like to acknowledge Dr. Selahattin Sayil, Assistant Professor of Electrical Engineering at Lamar University, for his guidance in instructing the author and in narrowing the field of CMOS digital IC design to pick a topic to research for this paper. VIII. References [1] R.Wilson and D. Lammers, Grove Calls Leakage Chip Designers Top Problem, EE Times, 13 Dec. 2002; OEG S0040. [2] F. Fallah and M. Pedram, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, Oct. 11, 2006; -leakage-review-journal.pdf. [3] Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2005 edition, [4] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, John Wiley & Sons, Inc. N.Y., pp , [5] D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and Design of Digital Integrated Circuits: In Deep Submicron Technology, McGraw-Hill Companies, Inc., N.Y., pp , [6] A. Chandrakasan, W. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, [7] W.M. Elgharbawy and M.A. Bayoumi, Leakage Sources and Possible Solutions in Nanometer CMOS Technologies, IEEE Circuits and Systems Magazine, pp. 8-15, Fourth Quarter [8] B. Van Zeghbroeck, Principles of Semiconductor Devices, m, Ch. 4, [9] N.S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, and V. Narayanan, Leakage Current: Moore s Law Meets Static Power, IEEE Computer Society, pp , Dec [10] S.M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw-Hill Companies, Inc., N.Y., pp , [11] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, John Wiley & Sons, Inc. N.Y., pp