Energy Reduction of Ultra-Low Voltage VLSI Circuits by Digit-Serial Architectures

Transcription

1 Energy Reduction of Ultra-Low Voltage VLSI Circuits by Digit-Serial Architectures Muhammad Umar Karim Khan Smart Sensor Architecture Lab, KAIST Daejeon, South Korea Chong Min Kyung Smart Sensor Architecture Lab, KAIST Daejeon, South Korea Abstract Ultra-low voltage VLSI designs are gaining widespread attention due to the requirements of minimum energy consuming motes. Leakage energy is a considerable part of the overall energy consumed in the ultra-low voltage domain. This paper deals with the overall energy reduction in ultra-low power systems by the use of digit-serial implementations. Leakage energy is reduced by the reduction of hardware in digitserial implementations. However, overhead circuitry adds to the energy budget. It has been shown in this paper that digit-serial implementations do reduce the overall energy consumption in the ultra-low power VLSI circuits compared to bit-serial and wordparallel implementations. 73% and 92% reduction in energy per clock cycle was obtained with an 8-bit adder at a source voltage of.7v compared to the bit-serial and word-parallel implementations respectively. I. INTRODUCTION Low energy VLSI designs have gained widespread recognition in industries as well as research communities. The global cry for energy efficient systems and the advent of portable devices have influenced the industry to shift from paradigm of design for performance to design for battery lifetime. Energy is becoming a primary design constraint as most of consumer and military systems have developed into standalone devices run by a battery []-[3]. Since the energy storage capabilities of Li-ion batteries have saturated quite some time ago, the focus has shifted towards VLSI designs with minimum energy consumption. Future nodes for sensing applications are to have very small sizes (of the order of a millimeter) []. The size of the node is limited by the size of the battery supplying power to it. With the passage of time the desired performance of VLSI chips has increased due to the increasingly complex tasks that computers need to perform. Microprocessors and other VLSI systems operating at high frequencies for both real-time and non-real-time applications consume a lot of dynamic energy. With the humungous increase in number of transistors over a single chip according to the Moore s law, the leakage energy has also increased vehemently. There are different methods of providing energy to portable nodes. Battery-operated systems use a pre-charged battery. The duration of operation of the node depends on the battery lifetime. Energy-scavenging nodes draw energy from the environment and store it in a battery. Battery-less nodes are purely dependent on the energy scavenged by the node as these nodes don t have any mechanism to store energy. Both increase in battery size and energy scavenging capability increase the manufacturing cost as well as the size of the node, therefore it becomes impertinent to come up with strategies for lower energy consumption in VLSI designs [4]. Different methods have been presented in literature for energy minimization. One of the most commonly employed methods is voltage scaling. Reduction in voltage supply provides energy reduction but at the cost of performance. The demands for low energy have increased to an extent that systems with a lifetime of decades is desired. It is for this reason the reduction in voltage levels have reached a new low level by employing sub-threshold voltage in CMOS VLSI designs termed as ultra-low voltage (ULV). Even though energy consumption decreases but the performance also decreases drastically in ULV circuits [5]. The author in [6] has provided an algorithm to design digitserial architectures from bit-serial implementations. In our work the utility of digit-serial implementations has been discussed in reducing energy consumption at ULV VLSI circuits. The rest of the paper is structured as follows. Section II discusses the energy consumption model of CMOS VLSI circuits at ULV. The effect of folding on energy consumption is provided in section III. Energy-Delay analysis is described in section IV. Experimental results are demonstrated in section V. II. ENERGY CONSUMPTION AT ULV The total energy consumed in a CMOS VLSI circuit comprises two components, the dynamic energy and the leakage energy. Dynamic energy is consumed due to the switching activity in the CMOS devices. Surge currents flow through the CMOS devices whenever the input is switching from low to high or vice versa. Leakage energy is consumed due to the flow of leakage current in the transistors at no switching activity in the circuit. There are three leakage currents in the CMOS device. The junction leakage is due to the flow of current through the reverse-biased drain-to-body and source-to-body junctions. Gate leakage is due to the flow of charged particles between the body and the gate through the silicon dioxide. With technology scaling, the width of silicon dioxide is decreasing and the gate leakage is becoming a /3/$3. 23 IEEE 32

2 significant constituent in the overall leakage current. Drain leakage is due to the flow of current from the drain to the source even when no channel is present and is the major part of leakage current. The dynamic and leakage energy consumed per clock cycle are given in expression () and (2) respectively [4], [5], [7]. () (2) And the total energy consumed is the sum of dynamic energy and leakage energy given as Or (3) Here is the activity rate, is the total capacitance, is the supply voltage, is the total leakage current and is the clock period. can be also considered as the propagation delay of the circuit as the clock period and propagation delay are kept the same for maximum speed. From [8] the value of propagation delay is given by expression in (4) (4) 2 The total current flowing through a CMOS transistor with no body-biasing is given by [9]. (5) Here is the DIBL coefficient and is the strength of the transistor. In off state and the off-current is given by. (6) From [8] the ON current of the CMOS transistor at ULV is modelled as (7) Substituting the value of ON current from equation (7) in equation (4) and putting the resulting value of in equation (3) the total energy consumed at ULV per clock cycle is given by 2 Decreasing the supply voltage decreases the dynamic energy as per the square law, however there is an exponential increase in the static energy per clock cycle with it. Thus there exists an optimal value of supply voltage at which the total energy is minimized. The situation is more vividly presented in figure. It shows the total energy consumed for a single stage 6nm CMOS inverter driving a load capacitance of 5 (8) ff using (8). The variation in is almost negligible with voltage and it reaches a peak value of 29nA at supply voltage of.8v. The activity rate is. It is clear from figure that the minimum energy point lies approximately at 25mV. The total energy consumed per clock cycle presented in figure is obtained by putting values in equation (8). For a 6-bit ripple carry adder the minimum energy point is demonstrated using 6nm technology through spice simulations in figure 2. Activity rate of. has been used in the experiment. Energy per cycle(fj) Supply.2 Voltage (volts).3.4 Figure : Total Energy Consumed per clock cycle for a single inverter using Equation (8) Energy per clock cycle (fj) Supply Voltage.6 (volts).8 Figure 2: Total Energy consumed per clock cycle for a 6- bit ripple carry adder Figure 2 shows that the minimum energy point for the adder is somewhat insensitive to supply voltage ranging between.25v to V. For smaller supply voltage the leakage energy is dominating which is decreasing with the increase in voltage. At comparatively larger voltage the dynamic energy overshadows the leakage energy. The energy consumed and the corresponding minimum clock cycle period is presented in figure 3. It clearly shows that for a small reduction in clock period from 3.7ns to 2.52ns the energy is increased approximately seven times. From a design perspective it is better to use a clock period of 3.7ns. 33

3 III. DIGIT-SERIAL IMPLEMENTATIONS AND ENERGY AT ULV In word-parallel implementations all the bits of a word are processed at the same time by hardware working in parallel whereas each bit is processed separately by the same hardware unit in bit-serial implementations. Word-parallel implementations process all the bits of a word in a single clock cycle, however bit-serial implementations process only a single bit during a single clock cycle. Bit-serial and wordparallel architectures can be considered as extremities as shown in the figure 4. Digit-serial Energy (fj) Clock period (ns) Figure 3: Energy vs Minimum Clock period for 6 bit ripple carry adder If is the number of digits in a word,, the overall energy consumed per clock cycle in the digit-serial implementation is given by Here is the energy consumed per clock cycle of the digit-serial implementation, is the additional capacitance due to overhead circuitry, is the leakage current in the word-parallel implementation and is the clock period of the digit-serial implementation. The clock period of the digit-serial implementation is substantially smaller compared to the word-parallel implementation due to smaller critical paths. is the capacitance of the word-parallel implementation which needs to be charged during every clock cycle. This capacitance is reduced by a factor of due to reduction of hardware units. Comparing equation (9) with (3) and analysing the second term of (9) we see that the leakage is reduced by the factor. However, the third term of (9) shows leakage due to the overhead circuitry. The coefficient associated with the leakage due to the overhead circuitry is an increasing function of, denoted as as with increasing the total number of bits to be processed per cycle is reduced, increasing the overhead circuitry required. is the ratio of off-current in the overhead circuit of the digit serial implementation to the off-current in word-parallel implementation of a circuit. In order to compare the energy consumption with the wordparallel implementation we have to consider the total energy consumed by the digit-serial circuits for producing a single sample which is given by the expression in (). (9) () Figure 4: Indication of Bit-serial, Digit-serial and Wordparallel Implementations for a word length of N implementations are at the intermediate levels. They process more bits per clock cycle as compared to the bit-serial implementations but not as many as the word-parallel implementations. In this paper we have adapted the techniques provided in [6] where unfolding transformation is used to design digit-serial implementations from bit-serial ones. Digit-serial systems use less hardware compared to wordparallel systems. Therefore it is expected that the digit-serial implementations will have less leakage current compared to word-serial systems. While shifting from a word-parallel circuit to digit-serial circuit overhead circuitry is added to the system which increases the overall energy consumed per clock cycle by the system. During the design of digit-serial structures two different situations arise. In the first one the bit-processing unit is considered to be very complex whereas the second situation deals with simpler ones. Both of these situations are discussed in the following. A. Complex bit-processing unit In applications using complex units for bit processing, the propagation delay of the overhead circuitry for digit-serial implementation can be ignored compared to the propagation delay of the word-parallel implementation. If is the propagation delay of the word parallel implementation then for complex bit processing units equation () holds / () In other words it takes equal amount of time for the wordparallel circuit and the digit-serial circuit to produce a single sample. Substituting the value of equation () in equation (9) 34

4 (2) From () the energy required to produce a single sample then becomes (3) If (3) shows the total energy consumed in the word-parallel implementation, comparison of (3) with (3) reveals the following inequality for energy reduction (4) Inequality (4) shows that the additional dynamic and leakage energy consumed per clock cycle of the overhead circuit should not overshadow the M-times reduction in leakage of the digit-serial implementation. Further simplification of (4) leads to (5) B. Simple bit-processing units If the complexity of the bit processing unit is relatively smaller, then the propagation delay of the overhead circuitry for the digit-serial implementations becomes a considerable portion of the propagation delay of the word-parallel system. As the number of bits produced per clock cycle is decreased, the complexity of the overhead circuit increases and so does the overhead delay. The delay in this situation is depicted by (6) Using this value of delay and substituting in (9) the total energy consumed per clock cycle of the digit-serial implementation becomes (7) Following the same pattern as the previous subsection a reduction in overall energy consumed is possible if the inequality in (8) is satisfied. (8) Simplification of (8) leads to (9) IV. EXPERIMENTAL RESULTS In our experiments we have used an eight bit adder consisting of eight full adders. Digit-serial implementations of the adder are based on [6] with the constituent full adders switched through multiplexers. The propagation delay of the 8-bit adder is comparable to overhead circuitry. The overhead circuitry is made up of FIFOs, multiplexers and registers. FIFOs with eight bits and different clock periods at input and output are used to provide appropriate bits to the bit processing units. Multiplexers are used for switching. The counters act as select bits for the multiplexers. Registers store the intermediate results. The complexity with respect to the number of bits produced per clock cycle cannot be represented mathematically. Therefore and are represented graphically. g(m) g(m) M voltage=.25v voltage=.3v voltage=.4v voltage=.5v voltage=.6v voltage=.7v Figure 5: The function g(m) against the M (total digits per word). Refer to (6) for g(m) Bits per Clock cycle voltage=.25 V voltage=.3v voltage=.4v voltage=v voltage=.6v Figure 6: The function g(m) against bits generated per clock cycle. Refer to (6) for g(m). 35

5 f(8/3) Supply voltage (V) Figure 7: f(8/3) at different voltages Figure 5 shows the function against different values of. It is seen that the variation in is very small at different supply voltages as the change in voltage is very small. Figure 6 shows the values of with respect to bits per cycle produced. The function is the ration of the offcurrent in the overhead circuit to the off-current in the word- f(m) M Voltage=. 6V Voltage=. 3V Figure 8: f(m) (ratio of off-current in overhead circuit to off-current in word-parallel implementation) against M (ratio of word-length to bits generated per clock cycle) for supply voltage of.6v and.3v. parallel implementation for a given value of. Figure 6 shows the values of at different values of supply voltage. It is clear that the function varies w. r. t. the supply voltage however the variation is so small that its effect is almost negligible as indicated by figure 8 where is plotted for supply voltages of.6v and.3v. The reason for the decrease in the value of w. r. t. increase in supply voltage is due to the implementation of the overhead circuit. The full-adders are based on CMOS NAND gates which are made up of three MOSFETs in series whereas the overhead circuit includes multiplexers made up of four MOSFETs connected in series. Due to stacking effect the increase in leakage current of the overhead circuit is lesser compared to the increase in full-adders with the same increase in supply voltage. Therefore the ratio tends to decrease with increasing source voltage. Figure 9 gives the function with the number of bits generated per clock cycle. In case of an 8-bit adder is linear w. r. t.. The total energy consumed per clock cycle against and bits produced per clock cycle at different values of supply voltage is presented in figure and respectively Bits 4 per cycle f(m) Figure 9: f(m) (ratio of off-current in overhead circuit to off-current in word-parallel implementation) against number of bits generated per clock cycle at.6v Energy per sample (fj) M.25V.3V.4V.5V.6V.7V Figure : Energy per sample at different supply voltages against M (total digits per word) 36

6 Energy per sample (fj) Bits per clock cycle.25v.3v.4v.5v.6v.7v Figure : Energy per sample at different supply voltages against bits produced per clock cycle From figure it is clear that the total energy consumed per clock cycle is minimum at two bits per clock cycle (M=8/2) for all values of supply voltages. Thus the energy consumed in ULP circuits can be further reduced by shifting from wordparallel or bit-serial implementations to digit-serial implementations. The set of energy delay curves are provided in figure. The pareto-optimal energy delay points also lie at a digit-serial implementation with number of bits produced per clock cycle equal to four. VI. REFERENCES [] B. Warneke, M. Last, B. Liebowitz and K. Pister, Smart dust: communicating with a cubic millimetre computer, Computer, vol. 34, January. [2] R. Sarpeshkar, Ultra Low Power Bioelectronics: Fundamentals, Biomedical Applications, and Bio-Inspired Systems, Cambridge University Press, 2. [3] W. Weber, J. Rabaey and E. Aarts, Ambient Intelligence, Springer 5 [4] M. Aliotto, Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial, IEEE Transactions on Circuits and Systems, Vol. 59, January 22. [5] J. Rabaey, Low-Power Design Essentials, Springer 9. [6] K. Parhi, A Systematic Approach for Design of Digit- Serial Signal Processing Architectures, IEEE Transactions on Circuits and Systems, Vol. 38, April 99. [7] N. Weste, D. Harris, CMOS VLSI Design, Addison- Wesley 4. [8] A. Wang, B. Calhoun, A. Chandrakasan, Sub-threshold Design for Ultra Low-Power Systems, Springer 6. [9] M. Aliotto, Understanding DC behaviour of subthreshold CMOS logic through closed-form analysis, IEEE transactions of Circuits and Systems, Vol. 57, July 2. Energy per sample (fj) Delay per sample (ns) Figure 2: Energy-Delay curves for different number of bits produced per clock cycle V. CONCLUSION In this paper an analysis of digit-serial implementations has been performed from the perspective of energy reduction. It has been shown that using digit-serial implementations in the ultra-low power VLSI systems, the overall energy consumed per sample can be reduced. With the reduction in hardware the leakage energy is reduced which is a formidable portion of the overall energy in ultra-low voltage circuits. 37