NT ot atrix L ontroller and river Features Internal L drivers 6 common signal drivers 0 segment signal drivers (can be externally extended to 00 segments using NTA) aximum display dimensions 0 characters * lines or 0 characters * line Interfaces with -bit or -bit PU Versatile display functions provided on chip: isplay lear, ursor Home, isplay N/FF, ursor N/FF, haracter Blinking, ursor hift, and isplay hift Three duty factors, selected by PR: /, /, and /6 isplays ata ( ): 0 X bits (displays up to 0 characters) haracter enerator ( ): 6 X bits for general data, X programmable dot patterns, or X 0 programmable dot patterns Low voltage reset NVATK Identification code Bonding option for A-type and B-type waveform haracter enerator R ( R): kinds of R sizes: 9 characters: 60 X dot patterns X 0 dot patterns 0 characters: 9 X dot patterns X 0 dot patterns 6 characters: 9 X dot patterns 6 X 0 dot patterns ustom R is also available Built-in power-on reset function Logic power supply: single +V supply L driver power supply: V - V (V+0. - V-.) Three oscillator operations (Freq. = 0KHz - 0KHz): x Internal oscillation x eramic resonator x xternal clock Process Available in 0-pin QFP or in HIP FR eneral escription The NT is a dot matrix L controller and driver LI that can operate with either a -bit or an -bit microprocessor (PU). NT receives control character codes from the PU, stores them in an internal (up to 0 characters), transforms each character code into a X, X, or X 0 dot matrix character pattern, and then displays the codes on the L panel. The built-in haracter enerator R consists of 6 different character patterns. The NT also contains haracter enerator where the user can store different character patterns at run time. These memory features make character display flexible. NT also provides many display instructions to achieve versatile L display functions. The NT is fabricated on a single LI chip using the process, resulting in very low power requirements. With several NTA driver Is connected to the NT, up to 0 characters can be displayed. V. November, 999
NT Pin onfiguration NTF 0 9 6 0 9 6 N 6 9 0 6 B B0 R/W R V L L V V V V V 9 0 6 0 9 6 B B 6 B B B B 6 6 6 6 60 9 6 0 9 6 6 66 6 6 69 0 6 9 0 6 9 0 6 9 0 0 9 6 0 9 6
NT Pad onfiguration 6 9 0 6 0 9 6 0 69 6 6 66 6 6 9 6 0 0 6 6 9 6 60 6 9 6 9 6 0 0 9 NTH 0 6 9 0 6 9 6 9 6 B 0 B6 N V B B B B 6 9 0 6 9 0 B V V V V V L L V A R R /W B0 B
NT Block iagram V V V V V V N INTRUTIN RITR (IR) INTRUTIN R AR UNTR TIIN NRATR L L R R/W UR0R AR URTR IPLAY ATA ( ) 0 X BIT 6-BIT HIFT RITR 6 N INAL RIVR 6 6 I/ BUTTR B~B ATA RITR URR /BLINK (R) NTRLLR B~B0 BUY FLA (BF) HARATR NRATR ( ) 6 X BIT HARATR NRATR R ( R) 0-BIT LATH IRUIT 0 NT INAL RIVR 0 0 PARALLL-T-RIAL NVRTR 0-BIT HIFT RITR
NT Pin and Pad escriptions Pin and Pad No. esignation I/ xternal onnection escription - - L panel egment signal output pins,, Pins connected to resistor or ceramic filter for internal clock oscillation. For external clock operation, clock inputs to. 6-0 V - V P Power supply Power supply for L driver L NTA lock to latch serial data sent to NTA. L NTA lock to shift serial data VA VB P Power supply V: +V A-Type waveform: V bond to VA B-Type waveform: V bond to VB N P Power supply N: 0V NTA witch signal to convert L drive waveform to A NTA haracter pattern data corresponding to each common signal is transmitted serially from this output. 0-Non selection, -selection. 6 R I PU Register select signal 0: Instruction register (write) Busy flag, address counter (read) : ata register (write, read) R/W I PU Read/Write control signal 0: Write : Read I PU Read/Write start signal 9 - B0 - B I/ PU Lower tri-state bi-directional data bus for transmitting data between PU and NT. Not used during -bit operation. - 6 B - B I/ PU Higher tri-state bi-directional data bus for transmitting data between PU and NT. B is also used as busy flag. - 6-6 L panel ommon signal output pins 6-0 0 - L panel egment signal output pins
NT Functional escription The NT is a dot-matrix L controller and driver LI. It operates with either a -bit or an -bit microprocessor (PU). The NT receives both instructions and data from the PU. ome instructions set operation modes, such as the function mode, data entry mode, and display mode; as well as some control L display functions, such as clear display, restore display, shift display, and cursor. ther instructions include read and write both data and addresses. All instructions allow users convenient and powerful functions to control the L dot-matrix displays. ata is written into and read from the ata isplay ( ) or the haracter enerator ( ). As display character codes, the data stored in the decodes a set of dot-matrix character patterns that are built into the haracter enerator R ( R). The R, with many character patterns (up to 6 patterns), defines the character pattern fonts. The NT regularly scans the character patterns through the segment drivers. The stores character pattern fonts at run time if users intend to show character patterns that are not defined in the R. This feature makes character display flexible. ther unused bytes can be used as general-purpose data storage. The L driver circuit consists of 6 common signal drivers and 0 segment signal drivers allowing a variety of application configurations to be implemented. Additionally, the user can extend display size by cascading the segment driver LI NTA. The maximum display dimensions can be either 0 characters in a -line display or 0 characters in a -line display. haracter enerator R ( R) The character generator R generates L dot character patterns from the -bit character pattern codes. The NT provides R configurations:. 9 haracters: The R contains 60 X dot character patterns and X 0 dot character patterns. An example is the NT-0, in which the relation between the character codes and character patterns is shown in Table. The character codes from 00H to 0FH are used to get character patterns from the. haracter codes from 0H to FH and from 0H to 9FH map to full character patterns. haracter codes from 0H to FFH are assigned to generate X 0 dot character patterns, and other codes are used to generate x dot character patterns.. 0 haracters: The R contains 9 X dot character patterns and X 0 dot character patterns. An example of this type is the NT-0, in which the relation between the character codes and character patterns is shown in Table. The character codes from 00H to 0FH are used to get character patterns from the. haracter codes from 0H to FH and from 0H to FFH are assigned to generate X 0 dot character patterns, and other codes to generate X dot character patterns. No null character pattern exists in this type. Note that the underlined cursor, displayed on the th duty may be obscure if the th row of a dot character pattern is coded. We recommend that users display the cursor in the blinking mode if they code x dot character patterns is their custom R.. 6 haracters: The R contains 9 X dot character patterns and 6 X 0 dot character patterns. No adequate example is presented here. The only difference between this type and the just mentioned second type is that the character codes from 00H to 0FH get character patterns from the R rather than from the. These character codes are assigned to generate X 0 dot character patterns. In this application, the would be employed as a general-purpose data storage. ustom character patterns are available by maskprogramming R. For convenience of character pattern development, NVATK has developed a userfriendly editor program for the NT to help determine the character patterns users prefer. By executing the program on the computer, users can easily create and modify their character patterns. By transferring the resulting files generated by the program through a modem or some other communication method, the user and NVATK have established a reliable, fast link for programming the R. 6
NT Absolute aximum Ratings* Power upply Voltage (V)......... -0.V to +0.V Power upply Voltage (V to V)...........................................V -.V to V+0.V Input Voltage (V I)............... -0.V to V +0.V perating Temperature (TPR).......-0q to +0q torage Temperature (TT)........-q to +q *omments tresses above those listed under "Absolute aximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. xposure to the absolute maximum rating conditions for extended periods may affect device reliability. All voltage values are referenced to N = 0V V to V, must maintain V t V t V t V t V t V. lectrical haracteristics (V =.0V, N = V = 0V, TA = q) ymbol Parameter in. Typ. ax. Unit onditions Applicable Pin VIH "H" Level Input Voltage (). - V V VIL "L" Level Input Voltage () -0. - 0. V VIH "H" Level Input Voltage () V -.0 - V V B0 - B, R, R/W, VIL "L" Level Input Voltage () N -.0 V VH "H" Level utput Voltage (). - - V IH = -0.mA VL "L" Level utput Voltage () - - 0. V IL =.ma VH "H" Level utput Voltage () 0.9 V - - V IH = -0.0mA VL "L" Level utput Voltage () - - 0. V V IL = 0.0mA B0 - B (TTL) L, L,, () V river Voltage escending () - -.9 V I = 0.0mA - 6 V river Voltage escending () - -. V I = 0.0mA - 0 IIL Input Leakage urrent - - PA VIN = 0 to V -IP Pull-up urrent 0 0 PA V = V R, R/W, B0-B IP upply urrent Power upply urrent - 0. 0. PA Rf oscillation, from external clock V = V, f = fp = 0KHz V
NT lectrical haracter (continued) ymbol Parameter in. Typ. ax. Unit onditions Applicable Pin xternal lock peration fp xternal lock perating Frequency 0 0 KHz tuty xternal lock uty ycle 0 % trp xternal lock Rise Time 0. - 0. Ps tfp xternal lock Fall Time 0. - 0. Ps Internal lock peration (R scillator) f scillator Frequency 90 0 0 KHz Rf = 9K: r % Internal lock peration (eramic Resonator scillator) f scillator Frequency 0 KHz eramic resonator VL VL L riving Voltage.6.0 - V V V - V A haracteristics Read ycle (V =.0V, N = V = 0V, TA = q) ymbol Parameter in. Typ. ax. Unit onditions ty nable ycle Time 00 - - ns Figure twh nable "H" Level Pulse Width 00 - - ns Figure tr, tf nable Rise/Fall Time - - ns Figure ta R, R/W etup Time 60 - - ns Figure 00 tah R, R/W Address Hold Time 0 - - ns Figure tr Read ata utput elay - - 90 ns Figure thr Read ata Hold Time 0 - - ns Figure
NT A haracteristics (continued) Write ycle (V =.0V, N = V = 0V, TA = q) ymbol Parameter in. Typ. ax. Unit onditions ty nable ycle Time 00 - - ns Figure twh nable "H" Level Pulse Width 00 - - ns Figure tr, tf nable Rise/Fall Time - - ns Figure ta R, R/W etup Time 60 - - ns Figure 00 tah R, R/W Address Hold Time 0 - - ns Figure t ata utput elay 00 - - ns Figure thr ata Hold Time 0 - - ns Figure Notes: : -bit operation mode : -bit operation mode Timing haracteristics of Interface ignals with egment river LI NTA (V = V, N = V = 0V, TA = q) ymbol Parameter in. Typ. ax. Unit onditions twh lock Pulse Width High 00 - - ns Figure twl lock Pulse Width Low 00 - - ns Figure tu ata etup Time 00 - - ns Figure th ata Hold Time 00 - - ns Figure tu lock etup Time 00 - - ns Figure t elay Time -000-000 ns Figure Power upply onditions Using Internal Reset ircuit ymbol Parameter in. Typ. ax. Unit onditions trn Power upply Rise Time 0. - 0 ms Figure tff Power upply FF Time - - ms Figure 9
NT Timing Waveforms Read peration R V IH V IL ta V IH V IL tah R/W V IH tw tah V IH V IL tf V IL V IL tr tr thr B0~B V IH V IL VAL ATA V IH V IL ty Figure. Bus Read peration equence (Reading out data from NT to PU) Write peration R V IH V IL ta V IH V IL tah R/W V IL V IL tw tah V IH V IL tr V IH V IL tf V IL t thw B0 ~ B V IH V IL VAL ATA V IH V IL ty Figure. Bus Write peration equence (Writing data from PU to NT) 0
NT Timing Waveforms (continued) Interface ignals with egment river LI LK 0.9 V 0.9 V LK twh tu twh 0.9 V 0. V 0.9 V 0. V 0. V tu twl 0.9 V 0. V tu th 0.9 V 0. V 0. V t Figure. ending ata to egment river LI NTA Interface ignals with egment river LI (continued).v V 0.V 0.ms > trn > 0ms trn 0.V tff > ms tff 0.V Figure. t FF stipulates the time of power FF for instantaneouspower supply to or when power supply repeats N and FF. Note : The NT has three clock options: A. Internal scillator peration (With eramic Filter) Rd:.K: r % = : 60pF r 0% I FILTR Rf: : r 0%
NT B. Internal scillator (With Rf Resistor) nly Rf may be connected between and. The wire connection Rf must be as short as possible. Rf: 9kohm + %. xternal lock peration and. PUL INPUT Note : Input/utput Terminals: A. Input Terminal Applicable Terminal : (No Pull Up ) V P N Applicable Terminals: R, R/W (with Pull Up ) PULL UP V P V P N
NT B. utput Terminal Applicable Terminals: L, L,, V P N. I/ Terminal Applicable Terminals: B0 to B V PULL UP V P P V NABL P N N (UTPUT IRUIT) (TRITAT) ATA
NT Table. orrespondence between haracter odes and haracter Patterns (NVATK tandard NT-0) Higher -bit ( to ) of haracter ode (Hexadecimal) 0 6 9 A B F 0 () () () () () Lower -bit (0 to ) of haracter ode (Hexadecimal) 6 9 A (6) () () () () () B () () (6) () F ()
NT Table. orrespondence between haracter odes and haracter Patterns (NVATK tandard NT-0) Higher -bit ( to ) of haracter ode (Hexadecimal) 0 6 9 A B F 0 () () () () () Lower -bit (0 to ) of haracter ode (Hexadecimal) 6 9 A (6) () () () () () B () () (6) () F ()
NT Instruction et Instruction ode Function R RW B B6 B B B B B B0 isplay lear 0 0 0 0 0 0 0 0 0 isplay/ ursor Home 0 0 0 0 0 0 0 0 * ntry ode et 0 0 0 0 0 0 0 I/ isplay N/FF isplay/ ursor hift 0 0 0 0 0 0 B lear entire display area, restore display from shift, and load address counter with address 00H. Restore display from shift and load address counter with address 00H. pecify direction of cursor movement and display shift mode. This operation takes place after each data transfer (read/write). pecify activation of display () cursor () and blinking of character at cursor position (B). xecution time (max) (f = 0KHz).6ms.6ms 0 0 0 0 0 / R/L * * hift display or move cursor. 0Ps Function et 0 0 0 0 L N F * * Address et Address et Busy Flag/ Address ounter Read / ata Write / ata Read 0 0 0 A 0 0 A 0 A 0 Write data Read data I/ = : Increment I/ = 0 : ecrement = : isplay hift n = : isplay n = : ursor isplay n B = : ursor Blink n / = : hift isplay / = 0 : ove ursor R/L = : hift Right R/L = 0 : hift Left L = : -Bit L = 0 : -Bit N = : ual Line N = 0 : ignal Line F = : x0 dots F = 0 : x dots BF = : Internal peration BF = : Ready for Instruction Note : ymbol "*" signifies an insignificant bit (disregard). Note : orrect input value for "N" is predetermined for each model. et interface data length (L), number of display line (N), and character font (F). Load the address counter with a address. ubsequent data access is for data. Load the address counter with a address. ubsequent data access is for data. Read Busy Flag (BF) and contents of Address ounter (A). Write data to or. Read data from or. : isplay ata : haracter enerator A : haracter enerator Address A : isplay ata Address A : Address ounter 0Ps 0Ps 0Ps 0Ps 0Ps 0Ps 0Ps 0Ps 6
NT Interface to L () haracter Font and Number of Lines The NT provides a X dot character font -line mode, a X 0 dot character font -line mode and a X dot character font -line mode, as shown in the table below. Three types of common signals are available as displayed in the table. The number of lines and the font type can be selected by the program. Number of Lines haracter Font Number of ommon ignals uty Factor X dots + ursor (or x dots) / X 0 dots + ursor / X dots + ursor (or x dots) 6 /6 () onnection to L The following L connection examples show the various combinations between characters and lines. NT can directly drive the following combinations: (a) X Font - character X line (/ duty cycle, / bias) L PANL NT 0
NT (b) X 0 Font - character X line (/ duty cycle, / bias) L PANL NT 0 (c) X Font - character X lines (/6 duty cycle, / bias) L PANL 9 6 NT 0
NT (d) X Font - 6 character X line (/6 duty cycle, / bias) L PANL NT 0 9 6 9
NT () Bias Power onnection NT provides / or / bias for various duty cycle applications. The power division voltage is described in the following table. The connection of NT, power supply, and resistors are also shown as follows: Power ivision /, / uty ycle - / Bias /6 uty ycle - / Bias V V - / VL V - / VL V V - / VL V - / VL V V - / VL V - / VL V V - / VL V - / VL V V - VL V - VL V V V V V NT V V V L V V V NT V V L VR V V V VR V Note: The resistance value depends on the L panel size. 0
NT () L Waveform A-type, / uty ycle, / Bias 00 LK V V V (V ) V V F sec Frame = 0k X 00 X =.9ms Frame frequency =.9ms =.ms A-type, / uty ycle, / Bias 00 LK V V V (V ) V V F sec Frame = 0k X 00 X = 6.ms Frame frequency = 6.ms = 6.ms A-type, /6 uty ycle, / Bias 00 LK 6 V V V (V ) V V F sec Frame = 0k X 00 X 6 =.9ms Frame frequency =.9ms =.ms
NT Application ircuit (for reference only) L PANL - 6-0 L L L V N - 0-0 NT R L L L R L F L V L N NT R L R F L L V V V V V V 6 V V V V V V 6 L NT L V N V V V V V R R R R R VR N or other negative voltage
NT Bonding iagram 0 9 6 0 69 6 6 66 6 6 6 6 6 60 6 9 9 NTH 6 0 Y (0, 0) X 6 Pm 0 6 9 9 6 0 6 9 0 6 9 0 Pm * ubstrate onnect to V or keep floating * Pad window area: 0Pm X 0Pm
NT Bonding imensions unit: Pm Pad No. esignation X Y Pad No. esignation X Y -69 B 69-0 -69 9 B 69-0 -69 B 69-0 9-69 9 B 69 - -69 B6 69-0 6-69 99 6 B 69-9 6-69 69-0 -69 69 69-6 9-69 9 69-0 0-69 9 0 69 - -69 69-0 -69 9 6 69-0 -69-69 9 9-69 -0 69-69 - 9 69 9 6-69 -0 6 0 69 6-69 -6 69 69-69 -0 69 9-69 -9 9 69 99 0-69 -0 60 69-69 - 6 69 9-69 -0 6 6 69 N -69-6 0 69 9-69 -0 6 9 69 - -6 6 6 6 V -0-6 66 9 6 V - -6 6 6 6 V - -6 6 6 6 9 V - -6 69 6 0 V - -6 0 6 L - -6 6 L - -6 6 VA 6-69 0-6 6-6 9-6 -6-6 6 R 6-6 6-6 R/W 9-6 6-6 6 0-6 - 6 9 B0 00-6 9-9 6 0 B 0-6 0-6 VB 6-6
NT rdering Information Part No. Package Remarks NTH-0 HIP FR Refer to Table NTF-0 0L QFP/B-type waveform Refer to Table NTH-0 HIP FR Refer to Table NTF-0 0L QFP/B-type waveform Refer to Table
NT Package Information QFP 0L utline imensions unit: inches/mm 0 H 6 6 H e b 0 ~ c ee etail F eating Plane y A A A L L etail F ymbol imensions in inches imensions in mm A 0.0 ax..0 ax. A 0.00 in. 0.0 in. A 0.±0.00.±0. b 0.0 +0.00 0. +0.0-0.00-0.0 c 0.006 +0.00 0. +0.0-0.00-0.0 0.±0.00.00±0. 0.±0.00 0.00±0. e 0.0±0.006 0.0±0. 0.69 N..60 N. 0.99 N..60 N. H 0.0±0.0.0±0. H 0.96±0.0.9±0. L 0.0±0.00.9±0.0 L 0.09±0.00.±0.0 y 0.006 ax. 0. ax. T 0q ~ q 0q ~ q Notes:. imensions & do not include resin fins.. imensions & are for P Board surface mount pad pitch design reference only 6