UM61512A Series 64K X 8 BIT HIGH SPEED CMOS SRAM. Features. General Description. Pin Configurations UM61512AV UM61512A
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1 Series 64K X 8 BIT HIGH SPEE CMOS SRAM Features Single +5V power supply Access times: 15/20/25ns (max.) Current: Operating: 160mA (max.) Standby: 10mA (max.) Full static operation, no clock or refreshing required All inputs and outputs are directly TTL compatible Common I/O using three-state output Output enable and two chip enable inputs for easy application ata retention voltage: 3V (min.) Available in 32-pin SKINNY IP, TSOP, SOP, SOJ and both 300/400 mil packages General escription The UM61512A is a low operating current 524,288-bit static random access memory organized as 65,536 words by 8 bits and operates on a single 5V power supply. It is built using UMC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-OWN and device enable and an output enable input is included for easy interfacing. ata retention is guaranteed at a power supply voltage as low as 3V. Pin Configurations SKINNY/SOJ/SOP TSOP (forward type) NC NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GN UM61512A VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O UM61512AV Pin No. Pin Name Pin No. Pin Name 1 A11 17 A3 2 A9 18 A2 3 A8 19 A1 4 A13 20 A0 5 WE 21 I/O1 6 CE2 22 I/O2 7 A15 23 I/O3 8 VCC 24 GN 9 NC 25 I/O4 10 NC 26 I/O5 11 A14 27 I/O6 12 A12 28 I/O7 13 A7 29 I/O8 14 A6 30 CE1 15 A5 31 A10 16 A4 32 OE 1
2 Block iagram A0 VCC GN A13 A14 A15 ECOER 512 X 2048 MEMORY ARRAY I/O1 I/O8 INPUT ATA CIRCUIT COLUMN I/O CE2 CE1 OE WE CONTROL CIRCUIT Pin escriptions SKINNY/SOJ/SOP Pin escription TSOP Pin No. Symbol escription 1, 2 NC No Connection 3-12, 23, 25-28, 31 A0 - A15 Address Inputs 13-15, I/O1 - I/O8 ata Input/Outputs 16 GN Ground 22 CE1 Chip Enable 24 OE Output Enable 29 WE Write Enable 30 CE2 Chip Enable 32 VCC Power Supply Pin No. Symbol escription 1-4, 7, 11-20, 31 A0 - A15 Address Inputs 5 WE Write Enable 6 CE2 Chip Enable 8 VCC Power Supply 9, 10 NC No Connection 21-23, I/O1 - I/O8 ata Input/Outputs 24 GN Ground 30 CE1 Chip Enable 32 OE Output Enable 2
3 Recommended C Operating Conditions(TA = 0 C to + 70 C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V GN Ground V VIH Input High Voltage VCC V VIL Input Low Voltage V CL Output Load pf TTL Output Load Absolute Maximum Ratings* VCC to GN V to +7.0V IN, IN/OUT Volt to GN V to VCC +0.5V Operating Temperature, Topr C to +70 C Storage Temperature, Tstg C to +125 C Temperature Under Bias, Tbias C to +85 C Power issipation, Pt W Soldering Temp. & Time C, 10 sec *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. C Electrical Characteristics (TA = 0 C to + 70 C, VCC = 5V ± 5%, GN = 0V) Symbol Parameter UM61512A-15/20/25 Unit Conditions Min. Max. ILI Input Leakage Current - 2 µa VIN = GN to VCC ILO Output Leakage Current - 2 µa CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GN to VCC ICC1 (1) ynamic Operating Current ma CE1 = VIL, CE2 = VIH II/O = 0 ma ISB - 30 ma CE1 = VIH or CE2 = VIL ISB1 Standby Power Supply Current - 20 ma CE1 VCC - 0.2V, CE2 VCC - 0.2V, VIN 0.2V or VIN VCC - 0.2V ISB2-20 ma CE1 0.2V, CE2 0.2V VIN 0.2V or VIN VCC - 0.2V VOL Output Low Voltage V IOL = 8 ma VOH Output High Voltage V IOH = -4 ma Note: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns. 3
4 Truth Table Mode CE1 CE2 OE WE I/O Operation Supply Current Standby H X X X High Z ISB, ISB1 X L X X High Z ISB, ISB2 Output isable L H H H High Z ICC1 Read L H L H OUT ICC1 Write L H X L IN ICC1 Note: X = H or L Capacitance (TA = 25 C, f = 1.0 MHz) Symbol Parameter Min. Max. Unit Conditions CIN * Input Capacitance 8 pf VIN = 0V CI/O * Input/Output Capacitance 10 pf VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0 C to +70 C, VCC = 5V ± 10%) Symbol Parameter UM61512A-15 UM61512A-20 UM61512A-25 Unit Min. Max. Min. Max. Min. Max. Read Cycle trc Read Cycle Time ns taa Address Access Time ns tace1 Chip Enable Access Time CE ns tace2 CE ns toe Output Enable to Output Valid ns tclz1 Chip Enable to Output in Low Z CE ns tclz2 CE2 5-5 * 5 - ns tolz Output Enable to Output in Low Z ns tchz1 Chip isable to Output in High Z CE ns tchz2 CE ns tohz Output isable to Output in High Z ns toh Output Hold from Address Change ns 4
5 AC Characteristics (continued) Symbol Parameter UM61512A-15 UM61512A-20 UM61512A-25 Unit Min. Max. Min. Max. Min. Max. Write Cycle twc Write Cycle Time ns tcw Chip Enable to End of Write ns tas Address Setup Time of Write ns taw Address Valid to End of Write ns twp Write Pulse Width ns twr Write Recovery Time ns twhz Write to Output in High Z ns tw ata to Write Time Overlap ns th ata Hold from Write Time ns tow Output Active from End of Write ns Notes: tchz1, tchz2, tohz and twhz are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1 (1,2,4) trc Address taa toh toh OUT 5
6 Timing Waveforms (continued) Read Cycle 2 (1,3,4,6) CE1 tace1 tclz1 5 tchz1 5 OUT Read Cycle 3 (1,4,7,8) CE2 tace2 tclz2 5 tchz2 5 OUT 6
7 Timing Waveforms (continued) Read Cycle 4 (1) trc Address taa OE toe toh CE1 tolz 5 tace1 tclz2 5 tchz1 5 CE2 tace2 tohz 5 tclz2 5 tchz2 5 OUT Notes: 1. WE is high for Read Cycle. 2. evice is continuously enabled CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high. 7. CE1 is low. 8. Address valid prior to or coincident with CE2 transition high. 7
8 Timing Waveforms (continued) Write Cycle 1 (6) (Write Enable Controlled) twc Address taw twr 3 CE1 (4) tcw 5 CE2 (4) tas 1 twp 2 WE tw th IN twhz tow OUT 8
9 Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) twc Address taw twr 3 tcw 5 CE1 tas 1 (4) CE2 (4) tcw 5 twp 2 WE tw th IN twhz 7 OUT Notes: 1. tas is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP) of a low CE1, a high CE2 and a low WE. 3. twr is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. 4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tcw is measured from the later of CE going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 9
10 AC Test Conditions Input Pulse Levels 0V to 3.0V Input Rise and Fall Time 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 +5V 480Ω +5V 480Ω I/O I/O 255Ω 30pF* 255Ω 5pF* * Including scope and jig. * Including scope and jig. Figure 1.Output Load Figure 2. Output Load for tclz1, tclz2, tolz, tchz1, tchz2, tohz, twhz, and tow ata Retention Characteristics (TA = 0 C to 70 C) Symbol Parameter Min. Max. Unit Conditions VR1 VCC for ata Retention V CE1 VCC - 0.2V CE2 VCC - 0.2V or CE2 0.2V VR V CE2 0.2V CE1 VCC - 0.2V or CE1 0.2V ICCR1 ata Retention Current - 5 ma VCC = 3.0V CE1 VCC - 0.2V CE2 VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V ICCR2-5 ma VCC = 3.0V CE2 0.2V CE1 0.2V VIN VCC - 0.2V or VIN 0.2V tcr Chip isable to ata Retention Time 0 - ns tr Operation Recovery Time 5 - ms See Retention Waveform 10
11 Low VCC ata Retention Waveform (1) (CE1 Controlled) ATA RETENTION MOE VCC 4.75V 4.75V tcr VR 3V tr CE1 VIH VIH CE1 VR - 0.2V Low VCC ata Retention Waveform (2) (CE2 Controlled) ATA RETENTION MOE VCC 4.75V 4.75V tcr VR 3V tr CE2 VIL VIL CE2 0.2V Ordering Information Part No. Access Time (ns) Operating Current Max. (ma) Standby Current Max. (ma) Package UM61512AK L SKINNY UM61512AK L SKINNY UM61512AS L SOJ (300 mil) UM61512AS L SOJ (300 mil) UM61512ASW L SOJ (400 mil) UM61512ASW L SOJ (400 mil) UM61512AM L SOP UM61512AV L TSOP 11
12 Package Information SKINNY 32L Outline imensions unit: inches/mm E S E A A2 C A1 Base Plane L Seating Plane B B1 e1 \ ea Symbol imensions in inches imensions in mm A Max Max. A Min Min. A B B C Typ. (1.620 Max.) Typ. (41.15 Max.) E E Typ. (0.300 Max.) 7.32 Typ. (7.62 Max.) e L \ 0 ~ 15 0 ~ 15 ea S Max Max. Notes: 1. The maximum value of dimension includes end flash. 2. imension E1 does not include resin fins. 3. imension S includes end flash. 12
13 Package Information SOJ 32/32L (300mil BOY) Outline imensions unit: inches/mm b c E F ETAIL "A" F BASE METAL WITH PLATING SECTION F-F 1 16 ETAIL "A" HE b1 y s SEATING PLANE b e MIN 0.026" A y y A A1 e1 Symbol imensions in inches imensions in mm Min. Nom. Max. Min. Nom. Max. A A A b b c HE E e e s y Notes: 1. The maximum value of dimension includes end flash. 2. imension E doesn't include resin fins. 3. imension e 1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. 13
14 Package Information SOJ 32/32L (400mil BOY) Outline imensions unit: inches/mm b b1 c1 c E1 F ETAIL "A" F BASE METAL WITH PLATING SECTION F-F 1 16 ETAIL "A" E b2 y S SEATING PLANE b e MIN 0.025" A y y A A1 E2 Symbol imensions in inches imensions in mm Min. Nom. Max. Min. Nom. Max. A A A b b c E ` E E e S y Notes: 1. imension includes end flash. 2. imension E doesn't include resin fins. 3. imension E1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. 14
15 Package Information SOP (W.B.) 32L Outline imensions unit: inches/mm e1 ~ E HE L 1 b 16 etail F e1 c s Seating Plane y e A1 A2 A See etail F LE Symbol imensions in inches imensions in mm A Max Max. A Min Min. A b c Typ. (0.820 Max.) Typ. (20.83 Max.) E e e NOM NOM. HE L LE S Max Max. y Max Max. θ 0 ~ 10 0 ~ 10 Notes: 1. The maximum value of dimension includes end flash. 2. imension E does not include resin fins. 3. imension e 1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. 15
16 Package Information TSOP 32L TYPE I (8 X 20mm) Outline imensions unit: inches/mm A2 e 12.0 X A E c GAUGE PLANE A1 c 0.25 BSC L LE H etail "A" etail "A" y S b 0.10(0.004) M Symbol imensions in inches imensions in mm A Max Max. A A b c E e TYP TYP. H L LE TYP TYP. S TYP TYP. Y Max Max. θ 0 ~ 6 0 ~ 6 Notes: 1. The maximum value of dimension includes end flash. 2. imension E does not include resin fins. 3. imension e 1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. 16
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