MIT Wireless Gigabit Local Area Network WiGLAN Charles G. Sodini Department of Electrical Engineering and Computer Science Room 39-527 Phone (617) 253-4938 E-Mail: sodini@mit.edu Sponsors: MARCO, SRC, MIT CICS
Wireless Gigabit Local Area Network (WiGLAN( WiGLAN) PC Peripherals Consumer Electronics Interactive Video HDTV videophone stereo controller (NGI) novelties
Research Goals Demonstrate key circuit and system concepts to advance wireless LAN to Gb/sec data rates Adaptive system architecture to support wide range of data rates and quality of service Develop low power design techniques at the circuit, chip architecture and system level to support portable appliances
WiGLAN Architecture Network Controller Allocates channels Measures SNR Space-Time Diversity WiGLAN ADAPTER Appliance WiGLAN ADAPTER Appliance NGI Network Controller Processor W i G L A N A D A P T E R WiGLAN ADAPTER High Data Rate Appliance WiGLAN ADAPTER Appliance
Network Controller with Space-Time Diversity Receiver Chain Transmitter Chain Network Server DSP Multi-Carrier Adaptive Rate QAM DSP Space-Time Processing Receiver Chain Transmitter Chain Receiver Chain Transmitter Chain Receiver Chain Transmitter Chain Digital Modulation Digital Space-Time Diversity Processing Improves channel capacity Replicated Transmit/Receive Chain
OFDM 150 MHz bandwidth available in 5.8 GHz band, with bins ~1 MHz wide Conversion between time and frequency via (I)FFT Narrow bins provide more granularity for changing data demands Narrow bins increase total complexity, but allow greater potential for parallelism Cyclic prefix similar to frequency guard bands
Adaptive Modulation Can adaptively change modulation for each bin based on measured channel response. Either optimal (gray) or coarse (dark gray) water pouring can be used. Most of the benefit comes from avoiding very bad frequency bins. Optimal: 54 b/s/hz Coarse: All equal 40 b/s/hz 48 b/s/hz (best) Threshold may differ for each block Coarse requires less overhead to identify bin modulation
Network Adapter Block Diagram Network adapter RF Trans. Baseband Mixed-Signal Processor Digital Signal Processor Appliance Physically Small - Requires High Integration 3 Major IC s - RF, Baseband Mixed Signal, DSP Quality of Service - Scaleable with Power Dissipation
Baseband Mixed-Signal Processor Wideband A/D Conversion DC-150MHz, oversampled at 600MSPS ~12 bit linearity/resolution Low power (~1W, core) Programmable Gain Amplifier 0-20dB, 72 db Linearity Channel Equalization Channel fading characteristic requires only modest amplitude equalization
Proposed ADC Architecture Highly parallel array of time-interleaved ADCs 16 banks of 8 14-bit pipeline ADCs, each running at approximately 5MHz 2x oversampling at 600 MHz effective sampling rate Continuous background digital calibration of gain, offset, and interchannel timing skew and input path mismatch errors Novel token-passing control scheme to reduce clock interconnect Back-end cubic interpolation to resample the output data stream and cancel timing skew
Proposed Architecture, Cont d
Network Adapter Block Diagram Network adapter RF Trans. Baseband Mixed-Signal Processor Digital Signal Processor Appliance Physically Small - Requires High Integration 3 Major IC s - RF, Baseband Mixed Signal, DSP Quality of Service - Scaleable with Power Dissipation
WiGLAN Receiver: Architectural Approach 5.8 G H z R F In pu t A na l og B as eba n d P roce ssi ng Primary Goals Multiple receivers in parallel Fully integrated analog front end Major Challenges 1 st LO 2 nd LO Design & implementation of widebandwidth high frequency filters Isolation between receivers
WiGLAN Receiver: Integrated Filters Motivations: Isolation & matching complexities with use of multiple external discrete filters Approaches: Q-enhancement techniques to compensate low Q on-chip inductors Simple & novel filter building blocks Traditional passive & active integrated circuit techniques reuse, where appropriate, to implement higher order filters Challenges: Filter stability with component tolerances Receiver linearity and noise degradation
WiGLAN Receiver: Image Reject Filter (Prototype Building Block) Tunable rejection response Tunable center frequency
Power Amplifier Efficiency V c V c V q V q I c t I c t I q I q t t To improve efficiency at low power: Adapt the biasing current, or Adapt the supply voltage, or Adapt both current and voltage
Adaptive biasing Concepts Adapt the bias current based on power level Improve efficiency at lower power levels
The Averaging Circuit τ ave. circuit time constant T C carrier period T S QAM symbol period T << τ = RC << C T S T C τ I V averfrms T S V RFrms st 1 SYMBOL nd 2 SYMBOL rd 3 SYMBOL th 4 SYMBOL
Die Photo and Test Board Chip Dimension: 1.05mm x 1.25mm IBM 7HP SiGe BiCMOS The chip is mounted directly on board to minimize lead inductance
Adaptive biasing Results I C ma) P dc (mw) 350 300 250 200 150 Power Consumption across Power Range Gain remains nearly constant during adaptation 100 20 Gain 50 adaptive-sim conventional-sim adaptive-measured perfectly adaptive 0 0 10 20 30 40 50 60 70 80 90 100 P o ut P out (mw) Adaptation saves up to 2.5X power Gain (db) Gain (db) 15 10 conventional-sim adaptive-measured 5-5 0 5 10 15 20 P out (dbm) P out (db) adaptive-sim
Summary Wireless Gigabit LAN Provides a Research Platform for High Data Rate/Low Power Circuit Design DSP. Baseband Analog RFIC That can be applied to a variety of applications