A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology Shahriar Shahramian Sorin P. Voinigescu Anthony Chan Carusone

Transcription

1 A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology Shahriar Shahramian Sorin P. Voinigescu Anthony Chan Carusone Department of Electrical & Computer Eng. University of Toronto Canada

2 Introduction & Motivation I Equalization required at high bit rates Analog equalization up to 40 Gb/s Digital equalization is more robust and flexible Photo Detector Digital Equalizer ADC T/H Adaptive Equalizer Equalized Data Clock Recovery Require full rate Track & Hold Amplifiers

3 Introduction & Motivation II Demonstrated 40-GS/sec THA in SiGe BiCMOS f T and f MAX of 160 GHz CMOS technologies scaling to nanometre f T and f MAX exceed 200 GHz for in production CMOS CMOS is a serious contender for implementing DSP based equalizers above 10 Gb/s

4 Introduction & Motivation III Diode Sampling Bridge Switched Emitter Follower J. C. Jensen, et. al. CICC 02 S. Shahramian, et. al. CSICS 05 High speed Low dynamic range Requires diodes High speed Lower supply Isolation in hold mode

5 Introduction & Motivation IV Series CMOS Sampler Switched Source Follower I. H. Wang, et. al. Electronic Letters 06 This work CICC 06 Low supply Low speed due to series CMOS R ON Take advantage of high speed CMOS source follower

6 0.13-µm CMOS Technology Simulated f T and f MAX of 80 GHz 8 layer metallization back end with thick RF top metal layers Available triple-well CMOS transistors Available low power (high V TH ) transistors

7 THA Block Diagram Data Path Input TIA CS CS Diff. Pair Diff. Pair T/H DRV DRV Output Clock CML INV TIA CS CS CML INV CML INV Clock Path

8 Input Stage Design TIA Active loads Improve open loop Gain, T

9 Input Stage Design TIA Eliminating current source transistor reduces power supply voltage

10 Input Stage Design TIA Signal matching through resistive feedback Z R 1 + F in = = T 50Ω

11 Noise matching through transistor sizing Input Stage Design TIA ( ) = 2 2 C o 2 o F OPT B G R G R Z 1 ω 1 R 1 ω 1 W

12 Input Stage Design TIA Transistors biased at J = 0.25 ma/µm, increased noise figure for higher bandwidth Simulated bandwidth: 30 GHz Simulated input integrated noise over 30 GHz: 0.5 mv rms

13 Input Stage Design TIA Inductors improve bandwidth, input matching and filter high frequency noise

14 Input Stage Design TIA CS CS Transistors Q 1 and Q 2 are diode-connected at DC and therefore can bias the next CS stage

15 THA Stage Design T/H Switched source follower for maximum bandwidth

16 THA Stage Design T/H During Track, Q SF acts as a source follower with current I T

17 THA Stage Design T/H During Hold, I T flows through R L which turns Q SF off and isolates C H

18 THA Stage Design T/H Q T and Q H operate in digital mode and thus are biased at J = 0.15mA/µm

19 THA Stage Design T/H High V TH devices are used to drive Q T further into OFF region and reduce leakage

20 THA Stage Design T/H Q SF is implemented as a triple well transistor to reduce V EFF and lower power supply voltage

21 THA Stage Design Diff. Pair T/H A linear buffer drives the T/H block with 600mV PP input and output swing

22 THA Stage Design Diff. Pair T/H Capacitor C fth is used to match Q SF-CGS and thus cancel input signal feedthrough during hold mode

23 THA Stage Design Diff. Pair T/H DRV DRV A linear output driver provides signal to external 50Ω resistors and measurement equipment

24 Clock Distribution CML INV CML INV CML INV Converts a single-ended 30-GHz clock signal to a differential signal with 750mV PP swing

25 Chip Micrograph Manufactured using IBM s 0.13µm CMOS technology TIA CS Diff. Pair Diff. Pair THA DRV The circuit operates from a 1.8V supply and consumes 150mA. CML INV CML INV CML INV TIA CS 1mm 1mm

26 Measurement Results: SP

27 Measurement Results: SP II

28 Time Domain

29 Frequency Domain I

30 Frequency Domain II

31 Frequency Domain III

32 Circuit Comparison f sample [GS/s] Track BW [GHz] THD f in ] Supply [V] Power [mw] Process [N / f T ] This Work 30 1GHz CMOS 7GHz 0.13µm I. H. Wang el. al. 10 N/A 5GHz CMOS Electronic Letters µm J. Lee et. al GHz InP JSSC GHz S. Shahramian et al GHz SiGe CSICS 10GHz 160 GHz Y. Lu et. al GHz SiGe BCTM GHz

33 Conclusion CMOS emerges as a contender for high speed DSP based equalizers Discussed the design methodology for CMOS switched source follower THA Demonstrated the first 30-GS/sec THA in CMOS

34 Acknowledgement CMC for chip fabrication and providing CAD tools NSERC for financial support OIT and CFI for equipment ECIT for providing the network analyzer