Flexible Radio - BWRC Summer Retreat 2003
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1 Radio - BWRC Summer Retreat 2003 Viktor Öwall Digital ASIC Group Competence Center for Circuit Design Department of Electroscience Lund University
2 Lund University Founded 1666 All Faculties students 3000 PhD students
3 Department of Electroscience Circuit Design & CCCD Analog Mixed Signal Digital Signal Processing Telecommunication Medical Signal Processing Radio Systems MAC-layer Channel measurements Electromagnetic wave theory Antenna design etc
4 CCCD Competence Center for Circuit Design Annual budget 2002: 1.7M US$ VINNOVA 37% University 25% Industry 38% (money and resources) Companies Axis Communications Cadence Design Systems Ericsson Mobile Platforms Ericsson Radio Systems Infineon St. Jude Medical TeliaSonera + 3 more 10 Professors (4 in circuit design) 4 adjunct Professors ca 30 PhD students Manager: Prof. Jiren Yuan
5 Radio Aim: put a price on flexibility! What flexibility? Run time, design time,...
6 Multi Standard Radio Terminals PAN Sensors Wide coverage UMTS/GSM/... Multi standard device WLAN Bluetooth
7 Adapt to Channel Conditions APP PHY Quality information between OSI-layers Fast variations dealt with at lower layers Slow variations can be handled up to application layer Hardware must provide necessary nobs!
8 Radio Co-funded by EU-project Digital Baseband Design space Exploration Radio Frontend ADC Multiple antennas OFDM Coding Decoding
9 PACWOMAN Power Aware Communications for Wireless OptiMised Personal Area Networks EU-project: 8 partners from 7 countries To enable low-power low-cost flexible WPAN Tackling all ISO layers (OFDM, UWB, MAC, Networking, Security,...) NTUA
10 Radio Front-end Digital Baseband Design space Exploration Radio Frontend Henrik Sjöland ADC MIMO & Adaptive antennas OFDM Coding Decoding
11 1V CMOS Bluetooth Front-End Common-gate LNA + passive mixer Maximum signal headroom, i.e. no stacked transistors Wideband input and resonant output of LNA Fredrik Tillman
12 Measurement Data and Die Photo 0.25µm CMOS 1V, 2.5mA, 2.4GHz 14dB Conversion Gain 5dB NF -5dBm IIP 3, -15dBm CP 1 ESSCIRC 02
13 Improved Switched Tuning b 0 b 0 b 0 To differential resonator C W C Digital coarse frequency tuning High linearity Flexibility Doubled Q compared to single-ended scheme IEEE TCAS-II, 2002 b 1 b 1 b 1 2C 2W 2C b 2 b 2 b 2 4C 4W 4C Henrik Sjöland
14 Front-end Choose frequency band Coarse tuning Kittichai Phansathitwong
15 ADC Digital Baseband Design space Exploration Radio Frontend ADC MIMO & Adaptive antennas OFDM Coding Decoding Jiren Yuan
16 ADC specifications Resolution, N: 6 12 bits Sampling rate, f S : MS/s f S Peformance limits FLASH TIME INTERLEAVED INTERPOLATING FOLDING SUBRANGING PIPELINED The flexible range of interest ALGORITHMIC SUCCESSIVE APPROXIMATION CYCLIC / RECURSIVE OVERSAMPLING CONVERTERS N
17 A flexible pipelined ADC V IN Sampling rates: f S = f clk, f clk /2, f clk /3... f clk /(N/2) Resolutions: N = 3 to N max Stages can be turned on/off depending on requirements Anderson, Norling, Yuan On the effects of static errors in a Pipelined ADC, SSOCC 03 Martin Andersson
18 A flexible time-interleaved ADC Parallel ADs calculating concurrently Digital calibration
19 Floating-point ADC for wireless For rapid fluctuation, AGC fails, effective resolution decreases Too expensive to cover the dynamic range with a full resolution Input Passive weighting 1 1/2 1/4 1/8 1/ S/H S/H S/H S/H S/H Compare & select 8-10 bit pipeline ADC 10-bit Mantissa 4-5 bit Exponent
20 CMOS floating-point ADCs A 10+5 bit 100MS/s CMOS FADC in fabrication A tested 8+4 bit CMOS FADC 0.35 µm digital CMOS 12-bit dynamic range 8-bit resolution 30 MS/s, 3.3V, 25mW ISCAS 01 Johan Piper
21 Digital Digital Baseband Design space Exploration Radio Frontend ADC MIMO & Adaptive antennas OFDM Coding Decoding Viktor Öwall and Peter Nilsson
22 Multiple Antennas Matrix inversion High MIPS Studying trade-offs: calculation complexity performance precision etc Low MIPS CORDIC
23 Implementation of Square root algorithm for MIMO Avioding channel matrix pseudo-inversion using a single processing element + Low complexity + Numerically stable Implementation data: 0.35µm 5-Metal 3.3V CMOS Max. freq. 80 MHz Max. throughput 128 Mb/s 190 K equivalent gates RAM size < 3 Kbits Core area: 9.0 mm 2 Presented at IASTED/CSS 03 Zhan Gou
24 OFDM OFDM transmitter coder Constellation mapper with bit loading mapper Pipelined points IFFT/FFT processor Variable choice of cyclic prefix (CP) point IFFT processor Signal reordering and CP insertion Unused parts are turned off Compatible with the physical layer of Hiperlan2 and IEEE802.11a D/A converter Presented at IASTED/CSS 03 Fredrik Kristensen
25 Signal Mapper Data from encoder Constellation Clock gating CG CG CG CG CG CG ZERO BPSK QPSK 8PSK 16QAM 64QAM Power control POWER CONTROLLER To IFFT Bitloading: Maps BPSK, QPSK, 8PSK, 16QAM and 64QAM constellation on each sub carrier Shift constellation and scale power for each sample in order to support bit loading algorithms
26 FFT/IFFT Implementation Data In Radix 2 2 and Radix 2 Stage 5 Radix 2 2 Stage 4 Radix 2 2 Stage 3 Radix 2 2 Stage 2 Radix 2 2 Stage 1 Data Out Clock Gate Clock Gate Clock Gate Clock Gate Clock Advantages High throughput Resize points Turn off unused stages Optimized bit width in each stage 0.35 μm 5ML CMOS
27 Older FFT Designs 8k points FFT for DVB (Digital Video Broadcasting) 1k points FFT for OFDM Demonstrator ca. 0.5M Transistors Radix 2 2 =low complexity and reduced memory Shousheng He
28 OFDM chip Mapper, FFT/IFFT and cyclic prefix insertion 0.35µm 5ML CMOS 8.5 mm 2 Sent for fabrication Fredrik Kristensen
29 OFDM Synchronization Cyclic Prefix longer than impulse response of the channel. One complex Frame frame FIFO 2x1024 words FIFO 2x256 words CORDIC Rotator Correlator Abolute Value Controller Argument Maximum Counter Angle Update Angle Calculation Frame Start 2000MIPS on DSP 3000gates + RAM Presented at ICECS 00 Stefan Johansson
30 Coding/Decoding Architectures Decoder Combined VA and MAP decoders Trade-off Window size vs. Memory req Complexity/precission Higher rate decoders Encoder Recursive and non-recursive convolutional codes with M max =10 Rate b/c, b=1..15, c=2..16, b<c by configuration encoder on FPGA platform Presented at ISCAS 03 Matthias Kamuf
31 Tack så mycket!
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