802.11a Hardware Implementation of an a Transmitter

Transcription

1 802a Hardware Implementation of an 802a Transmitter IEEE Standard for wireless communication Frequency of Operation: 5Ghz band Modulation: Orthogonal Frequency Division Multiplexing Elizabeth Basha, Steve Gerding, Rose Liu May 9, 2005 OFDM symbol - unit of data transmission One symbol consists of 48 data-encoded complex pairs and 4 pilot complex pairs which protect against noise 2 Transmitter Overview Design Specifications Tasks: Encodes data for forward error correction Maps data into complex pairs & distributes them among the different frequency indices Transform frequency data into time domain Packet Format: Preamble Header Data Data Transmit at 3 datarates: 6Mb/s 24-bit input data frame per OFDM symbol 2Mb/s 2 24-bit input data frames per OFDM symbol 24Mb/s 4 24-bit input data frames per OFDM symbol Design Goals: Minimize Area Minimize Power by reducing frequency and lowering V DD Just-in-time performance to meet the required datarates 3 4

2 Top Level Model Basic Serial Scrambler Design Bit Processes input bit per cycle MAC Controller Scrambler Mapper Convolutional Encoder IFFT Interleaver Cyclic Extend Send header control messages DAC Scramble Sequence Bit Simultaneously generates scramble sequence bit and computes output bit Repeatedly generates a 27-bit scramble sequence Send body control messages = Control Queue = Data Queue Send header and body data Process header Process body Bit 5 6 Initial Scrambler Design Unrolled Scrambler Design For Each Message: Generates the entire 27-bit scramble sequence 27 cycles Stores the scrambler sequence to be used throughout the message Advantage: Processes 24-bit input frame per cycle Disadvantage: Large initialization overhead is especially apparent for a series of very short messages Simultaneously generates frame of the scrambler sequence and processes frame of input data per cycle Updates the state of the seed register at end of each cycle Advantages: cycle initialization Processes 24-bit frame per cycle 7 8

3 Convolutional Encoder Design Interleaver Algorithm Serial Design Unrolled Design History Buffer input output Reorders input data bits Datarate dependent: Interleaving Pattern # of bits interleaved together 9 0 Mapper Algorithm IFFT Initial Design bits 0 Lookup tables ( for each rate) I 0x8000 0x7FFF Q 0x0000 0x0000 Frequency domain OFDM symbol 0x5A7E DataQ 6-Node Stage 6-Node Stage 2 6-Node Stage 3 DataQ 0 I 0x5A82 Q Twiddle Multiply Stage Combining Stage Radix4 Node Combining Stage 2 Rate 0 I 0x8692 0x796E Q 0x8692 0x8692 Area = 292mm 2 Cycle Time = 638ns Radix4 Nodes 48 *

4 IFFT Design Exploration IFFT Design Exploration 2 DataQ Data and Twiddle Setup 6-Node Stage DataQ DataQ Start Data and Twiddle Setup 6-Node Stage DataQ Area = 59mm 2 Area = 457mm 2 Cycle Time = 3050ns Cycle Time = 3289ns 3 4 Cyclic Extender Strategy 64 Complex Pairs of Data First Complex Pair Last 6 Complex Pairs 64 Complex Pairs of Data Our test structure must enable us to: Debug each module separately Quickly verify new version of modules Verify correctness of entire system Measure throughput of individual modules and system as a whole To do this, we leveraged the framework of the Extreme Benchmark Suite (XBS) 5 6

5 XBS Overview XBS Overview XBS is a benchmark suite designed to measure the performance of highly parallel processors and custom hardware implementations All XBS benchmarks have the following structure: Under Under Creates sets of test inputs to be read by test harness and output checker Generates both random and directed tests Under 7 8 XBS Overview XBS Overview Under Under Encapsulates device under test Reads in input files and generates output files Measures performance [throughput in bits per cycle] of device under test Reads in input and output files and determines if output files are correct Usually contains an ANSI C reference version of DUT If output is incorrect, displays location of discrepancy and correct value for debugging purposes 9 20

6 Results Evaluation Place and route results: Total Area 527 mm 2 Critical Path Delay 3289 ns XBS testing results: Module Throughput bits per cycle OFDM symbols per cycle Scrambler Convolutional Encoder Interleaver Mapper IFFT Cyclic Extend = 6 Mbps = 2 Mbps = 24 Mbps Our design fully conforms to the IEEE 802a standard Our design meets timing for the 6, 2, and 24 Mbps transmission rates Total system throughput (24 Mbps) = 2 bits / cycle Clock Frequency = 304 MHz Maximum data rate of system = 3648 Mbps We can turn our timing slack into power savings by reducing V DD and clock frequency Clock frequency can be reduced to 20 MHz Transmitter System