OPA3 OPA3 OPA23 OPA23 OPA43 OPA43 OPA43 OPA3 OPA23 OPA43 SBOS4A NOVEMBER 994 REVISED DECEMBER 22 General-Purpose FET-INPUT OPERATIONAL AMPLIFIERS FEATURES FET INPUT: I B = 5pA max LOW OFFSET VOLTAGE: 75µV max OPA3 WIDE SUPPLY RANGE: ±4.5V to ±8V SLEW RATE: V/µs WIDE BANDWIDTH: 4MHz EXCELLENT CAPACITIVE LOAD DRIVE SINGLE, DUAL, QUAD VERSIONS DESCRIPTION Offset Trim In +In V 2 3 4 DIP-8, SO-8 8 7 6 5 NC V+ Output Offset Trim The OPA3 series of FET-input op amps provides high performance at low cost. Single, dual, and quad versions in industry-standard pinouts allow cost-effective design options. The OPA3 series offers excellent general-purpose performance, including low offset voltage, drift, and good dynamic characteristics. Single, dual, and quad versions are available in DIP and SO packages. Performance grades include commercial and industrial temperature ranges. Out A In A +In A V 2 3 4 OPA23 A B DIP-8, SO-8 8 7 6 5 V+ Out B In B +In B OPA43 OPA43 Out A 4 Out D Out A 6 Out D In A +In A 2 3 A D 3 2 In D +In D In A +In A 2 3 A D 5 4 In D +In D V+ 4 V V+ 4 3 V +In B In B 5 6 B C 9 +In C In C +In B In B 5 6 B C 2 +In C In C Out B 7 8 Out C Out B 7 Out C DIP-4, SO-4 NC = No Connection NC 8 SOL-6 9 NC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 994, Texas Instruments Incorporated
ABSOLUTE MAXIMUM RATINGS () Supply Voltage, V+ to V... 36V Input Voltage... (V ).7V to (V+) +.7V Output Short-Circuit (2)... Continuous Operating Temperature... 55 C to +25 C Storage Temperature... 55 C to +25 C Junction Temperature... 5 C Lead Temperature (soldering, s)... 3 C NOTES: () Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) Short-circuit to ground, one amplifier per package. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR () RANGE MARKING NUMBER MEDIA, QUANTITY Single OPA3 SO-8 D 4 C to +85 C OPA3UJ OPA3UJ Rails, " " " " " OPA3UJ/2K5 Tape and Reel, 25 OPA3 SO-8 D 4 C to +85 C OPA3UA OPA3UA Rails, " " " " " OPA3UA/2K5 Tape and Reel, 25 OPA3 SO-8 D 4 C to +85 C OPA3U OPA3U Rails, " " " " " OPA3U/2K5 Tape and Reel, 25 Dual OPA23 SO-8 D 4 C to +85 C OPA23UJ OPA23UJ Rails, " " " " " OPA23UJ/2K5 Tape and Reel, 25 OPA23 SO-8 D 4 C to +85 C OPA23UA OPA23UA Rails, " " " " " OPA23UA/2K5 Tape and Reel, 25 Quad OPA43 DIP-4 N 4 C to +85 C OPA43PJ OPA43PJ Rails, 25 " " " " OPA43PA OPA43PA Rails, 25 OPA43 SOL-6 DW 4 C to +85 C OPA43UA OPA43UA Rails, 48 " " " " " OPA43UA/K Tape and Reel, OPA43 SOL-4 D 4 C to +85 C OPA43NJ OPA43NJ Rails, 58 " " " " OPA43NA OPA43NA Rails, 58 NOTE: () For the most current specifications and package information, refer to our web site at. 2 OPA3, 23, 43 SBOS4A
ELECTRICAL CHARACTERISTICS At T A = +25 C, V S = ±5V, and R L = 2kΩ, unless otherwise noted. OPA3UA OPA23UA OPA43PA, UA, NA OPA3UJ OPA23UJ OPA43PJ, NJ PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage ±.2 ± ±.5 mv OPA3U model only ±.2.75 mv vs Temperature () Operating Temperature Range ±2 ± µv/ C vs Power Supply V S = ±4.5V to ±8V 5 2 µv/v OPA3U model only 5 µv/v INPUT BIAS CURRENT (2) Input Bias Current V CM = V +5 ±5 pa vs Temperature See Typical Characteristic Input Offset Current V CM = V ± ±5 pa NOISE Input Voltage Noise Noise Density, f = Hz 2 nv/ Hz f = Hz 6 nv/ Hz f = khz 5 nv/ Hz f = khz 5 nv/ Hz Current Noise Density, f = khz 3 fa/ Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range (V ) + 3 (V+) V Common-Mode Rejection V CM = 2V to +4V 7 8 db OPA3U model only 8 86 db INPUT IMPEDANCE Differential Ω pf Common-Mode V CM = V 2 3 Ω pf OPEN-LOOP GAIN Open-Loop Voltage Gain V O = 2V to +2V 94 db OPA3U model only db FREQUENCY RESPONSE Gain-Bandwidth Product 4 MHz Slew Rate V/µs Settling Time.% G =, V Step, C L = pf.5 µs.% G =, V Step, C L = pf 2 µs Total Harmonic Distortion + Noise khz, G =, V O = 3.5Vrms.8 % OUTPUT Voltage Output, Positive (V+) 3 (V+) 2.5 V Negative (V ) + 3 (V ) + 2.5 V Short-Circuit Current ±25 ma POWER SUPPLY Specified Operating Voltage ±5 V Operating Voltage Range ±4.5 ±8 V Quiescent Current (per amplifier) I O = ±.5 ±.75 ±2 ma TEMPERATURE RANGE Operating Range 55 +25 55 +25 C Storage 55 +25 C Thermal Resistance, θ JA DIP-8 C/W SO-8 5 C/W DIP-4 8 C/W SO-4, SOL-6 C/W Specifications same as OPA3UA. NOTES: () Ensured by wafer test. (2) High-speed test at T J = 25 C. OPA3, 23, 43 3 SBOS4A
TYPICAL CHARACTERISTICS At T A = +25 C, V S = ±5V, and R L = 2kΩ, unless otherwise noted. 2 OPEN-LOOP GAIN/PHASE vs FREQUENCY 2 POWER SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY 2 Voltage Gain (db) 8 6 4 2 G 45 9 35 8 Phase Shift ( ) Power Supply Rejection (db) 8 6 4 2 CMR +PSR PSR 8 6 4 2 Common-Mode Rejection (db) 2 k k k M M Frequency (Hz) k k k M Frequency (Hz) k INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY k 6 CHANNEL SEPARATION vs FREQUENCY R L = Voltage Noise (nv/ Hz) Voltage Noise Current Noise k k k M Frequency (Hz) Current Noise (fa/ Hz) Channel Separation (db) 4 2 Dual and quad devices. R G =, all channels. L = 2kΩ Quad measured channel A to D or B to C other combinations yield improved rejection. 8 k k k Frequency (Hz) Input Bias and Input Offset Current (pa) k k. INPUT BIAS AND INPUT OFFSET CURRENT vs TEMPERATURE V CM = V. 75 5 25 25 5 75 25 I B Ambient Temperature ( C) I OS Input Bias Current (pa) k INPUT BIAS CURRENT vs INPUT COMMON-MODE VOLTAGE Input bias current is a function of the voltage between the V supply and the inputs. V S = ±5V V S = ±5V 5 5 5 5 Common-Mode Voltage (V) 4 OPA3, 23, 43 SBOS4A
TYPICAL CHARACTERISTICS (Cont.) At T A = +25 C, V S = ±5V, and R L = 2kΩ, unless otherwise noted. 2 OPEN-LOOP GAIN vs TEMPERATURE.8 QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE 4 Voltage Gain (db) 5 5 Quiescent Current (ma).6.4.2 I SC+ I SC I Q V S = ±5V I Q V S = ±5V 3 2 Short-Circuit Current (ma) 75 5 25 25 5 75 25 Ambient Temperature ( C) 75 5 25 25 5 75 25 Temperature ( C) 2 5 OFFSET VOLTAGE PRODUCTION DISTRIBUTION Typical production distribution of packaged units. Single, dual and quad units included. 35 3 25 OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION Typical production distribution of packaged units. Single, dual and quad units included. Units (%) Units (%) 2 5 5 5 4 2 8 6 4 2 2 4 6 8 2 4 7 6 5 4 3 2 2 3 4 5 6 7 Offset Voltage Drift (µv/ C) Offset Voltage (µv) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY V O = 3.5Vrms Bandwidth- Limited 3 V S = ±5V MAXIMUM OUTPUT VOLTAGE vs FREQUENCY THD + Noise (%)... G = V/V G = V/V Output Voltage (Vp-p) 2 V S = ±5V Maximum output voltage without slew-rate induced distortion. G = V/V. k k k k k M M Frequency (Hz) Frequency (Hz) OPA3, 23, 43 5 SBOS4A
TYPICAL CHARACTERISTICS (Cont.) At T CASE = +25 C, V S = ±5V, and R L = 2kΩ, unless otherwise noted. SMALL-SIGNAL STEP RESPONSE G =, C L = 3pF LARGE-SIGNAL STEP RESPONSE G =, C L = 3pF 5mV/div 5V/div 2ns/div µs/div Settling Time (µs) SETTLING TIME vs CLOSED-LOOP GAIN V O = V Step R L = 2kΩ C L = pf.% Overshoot (%) 5 4 3 2 SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE R L = 2kΩ Higher R L value generally reduces overshoot. G = +2 G = G = G = ±.% Closed-Loop Gain (V/V) pf nf nf Load Capacitance Output Voltage Swing (V) 5 4 3 2 2 3 4 5 OUTPUT VOLTAGE SWING vs OUTPUT CURRENT V IN = 5V 25 C 55 C 25 C 25 C 25 C 55 C V IN = 5V 5 5 2 25 3 Output Current (ma) 6 OPA3, 23, 43 SBOS4A
APPLICATIONS INFORMATION The OPA3 series op amps are unity-gain stable and suitable for a wide range of general-purpose applications. Power-supply pins should be bypassed with nf ceramic capacitors or larger. The OPA3 series op amps are free from unexpected output phase-reversal common with FET op amps. Many FET-input op amps exhibit phase-reversal of the output when the input common-mode voltage range is exceeded. This can occur in voltage-follower circuits, causing serious problems in control-loop applications. All circuitry is completely independent in dual and quad versions, assuring normal behavior when one amplifier in a package is overdriven or shortcircuited. OFFSET VOLTAGE TRIM The OPA3 (single op amp version) provides offset voltage trim connections on pins and 5. Offset voltage can be adjusted by connecting a potentiometer as shown in Figure. This adjustment should be used only to null the offset of the op amp, not system offset or offset produced by the signal source. 2 3 V+ V 7 OPA3 (Single op amp only) OPA3 6 4 5 kω Trim Range: ±2mV typ FIGURE. OPA3 Offset Voltage Trim Circuit. INPUT BIAS CURRENT The input bias current is approximately 5pA at room temperature and increases with temperature as shown in the typical characteristic Input Bias Current vs Temperature. Input bias current also varies with common-mode voltage and power supply voltage. This variation is dependent on the voltage between the negative power supply and the common-mode input voltage. The effect is shown in the typical curve Input Bias Current vs Common-Mode Voltage. OPA3, 23, 43 7 SBOS4A
PACKAGE OPTION ADDENDUM 7-Mar-27 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan OPA3U ACTIVE SOIC D 8 75 Green (RoHS OPA3UA ACTIVE SOIC D 8 75 Green (RoHS OPA3UA/2K5 ACTIVE SOIC D 8 25 Green (RoHS OPA3UAE4 ACTIVE SOIC D 8 75 Green (RoHS OPA3UG4 ACTIVE SOIC D 8 75 Green (RoHS OPA3UJ ACTIVE SOIC D 8 75 Green (RoHS OPA3UJ/2K5 ACTIVE SOIC D 8 25 Green (RoHS OPA3UJE4 ACTIVE SOIC D 8 75 Green (RoHS OPA23UA ACTIVE SOIC D 8 75 Green (RoHS OPA23UA/2K5 ACTIVE SOIC D 8 25 Green (RoHS OPA23UA/2K5E4 ACTIVE SOIC D 8 25 Green (RoHS OPA23UA/2K5G4 ACTIVE SOIC D 8 25 Green (RoHS OPA23UAE4 ACTIVE SOIC D 8 75 Green (RoHS OPA23UAG4 ACTIVE SOIC D 8 75 Green (RoHS OPA23UJ ACTIVE SOIC D 8 75 Green (RoHS OPA23UJ/2K5 ACTIVE SOIC D 8 25 Green (RoHS (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 3U CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 3U A CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 3U A CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 3U A CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 3U CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 3UJ CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 3UJ CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 3UJ CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 23UA CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 23UA CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 23UA CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 23UA CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 23UA CU NIPDAU-DCC Level-3-26C-68 HR -55 to 25 OPA 23UA CU NIPDAU-DCC Level-3-26C-68 HR OPA 23UJ CU NIPDAU-DCC Level-3-26C-68 HR OPA 23UJ Device Marking (4/5) Samples Addendum-Page
PACKAGE OPTION ADDENDUM 7-Mar-27 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan OPA23UJ/2K5G4 ACTIVE SOIC D 8 25 Green (RoHS OPA23UJG4 ACTIVE SOIC D 8 75 Green (RoHS OPA43NA ACTIVE SOIC D 4 5 Green (RoHS OPA43NAG4 ACTIVE SOIC D 4 5 Green (RoHS OPA43NJ ACTIVE SOIC D 4 5 Green (RoHS (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) CU NIPDAU-DCC Level-3-26C-68 HR OPA 23UJ CU NIPDAU-DCC Level-3-26C-68 HR OPA 23UJ CU NIPDAU-DCC Level-3-26C-68 HR -4 to 85 OPA43NA CU NIPDAU-DCC Level-3-26C-68 HR -4 to 85 OPA43NA CU NIPDAU-DCC Level-3-26C-68 HR -4 to 85 OPA43NJ OPA43NJG4 ACTIVE SOIC D 4 TBD Call TI Call TI -4 to 85 Device Marking (4/5) Samples OPA43PA ACTIVE PDIP N 4 25 Green (RoHS OPA43PAG4 ACTIVE PDIP N 4 25 Green (RoHS OPA43PJ ACTIVE PDIP N 4 25 Green (RoHS OPA43PJG4 ACTIVE PDIP N 4 25 Green (RoHS OPA43UA ACTIVE SOIC DW 6 4 Green (RoHS OPA43UA/K ACTIVE SOIC DW 6 Green (RoHS OPA43UAG4 ACTIVE SOIC DW 6 4 Green (RoHS CU NIPDAU N / A for Pkg Type -4 to 85 OPA43PA CU NIPDAU N / A for Pkg Type -4 to 85 OPA43PA CU NIPDAU N / A for Pkg Type -4 to 85 OPA43PJ CU NIPDAU N / A for Pkg Type -4 to 85 OPA43PJ CU NIPDAU-DCC Level-3-26C-68 HR -4 to 85 OPA43UA CU NIPDAU-DCC Level-3-26C-68 HR -4 to 85 OPA43UA CU NIPDAU-DCC Level-3-26C-68 HR -4 to 85 OPA43UA () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS - please check http:///productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 2
PACKAGE OPTION ADDENDUM 7-Mar-27 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3
PACKAGE MATERIALS INFORMATION 9-Sep-23 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A (mm) B (mm) K (mm) P (mm) W (mm) Pin Quadrant OPA3UA/2K5 SOIC D 8 25 33. 2.4 6.4 5.2 2. 8. 2. Q OPA3UJ/2K5 SOIC D 8 25 33. 2.4 6.4 5.2 2. 8. 2. Q OPA23UA/2K5 SOIC D 8 25 33. 2.4 6.4 5.2 2. 8. 2. Q OPA23UJ/2K5 SOIC D 8 25 33. 2.4 6.4 5.2 2. 8. 2. Q OPA43UA/K SOIC DW 6 33. 6.4.75.7 2.7 2. 6. Q Pack Materials-Page
PACKAGE MATERIALS INFORMATION 9-Sep-23 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA3UA/2K5 SOIC D 8 25 367. 367. 35. OPA3UJ/2K5 SOIC D 8 25 367. 367. 35. OPA23UA/2K5 SOIC D 8 25 367. 367. 35. OPA23UJ/2K5 SOIC D 8 25 367. 367. 35. OPA43UA/K SOIC DW 6 367. 367. 38. Pack Materials-Page 2