SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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1 Typical V OLP (Output Ground Bounce) <1 V at V CC = 5 V, T A = 25 C High-Drive Outputs ( 32-mA I OH, 64-mA I OL ) I off and Power-Up 3-State Support Hot Insertion SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002 Latch-Up Performance Exceeds 500 ma Per JEDEC Standard JESD-17 ESD Protection Exceeds JESD V Human-Body Model (A114-A) 200-V Machine Model (A115-A) SN54ABT125...J OR W PACKAGE SN74ABT D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1OE 1A 1Y 2OE 2A 2Y GND V CC 4OE 4A 4Y 3OE 3A 3Y description/ordering information SN74ABT RGY PACKAGE (TOP VIEW) 1A 1Y 2OE 2A 2Y OE 3Y V GND CC OE 4A 4Y 3OE 3A SN54ABT FK PACKAGE (TOP VIEW) 1Y NC 2OE NC 2A 1A 1OE NC V CC 4OE Y GND NC 3Y 3A NC No internal connection 4A NC 4Y NC 3OE The ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. These devices are fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION T A PACKAGE ORDERABLE TOP-SIDE PART NUMBER MARKING PDIP N Tube SN74ABT125N SN74ABT125N QFN RGY Tape and reel SN74ABT125RGYR AB125 Tube SN74ABT125D 40 C to 85 C SOIC D Tape and reel SN74ABT125DR ABT125 SOP NS Tape and reel SN74ABT125NSR ABT125 SSOP DB Tape and reel SN74ABT125DBR AB125 TSSOP PW Tape and reel SN74ABT125PWR AB125 CDIP J Tube SNJ54ABT125J SNJ54ABT125J 55 C to 125 C CFP W Tube SNJ54ABT125W SNJ54ABT125W LCCC FK Tube SNJ54ABT125FK SNJ54ABT125FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX DALLAS, TEXAS

2 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002 FUNCTION TABLE (each buffer) INPUTS OUTPUT OE A Y L H H L L L H X Z logic diagram (positive logic) 1OE 1 3OE 10 1A 2 3 1Y 3A 9 8 3Y 2OE 4 4OE 13 2A 5 6 2Y 4A Y Pin numbers shown are for the D, DB, J, N, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (see Note 1) V to 7 V Voltage range applied to any output in the high or power-off state, V O V to 5.5 V Current into any output in the low state, I O : SN54ABT ma SN74ABT ma Input clamp current, I IK (V I < 0) ma Output clamp current, I OK (V O < 0) ma Package thermal impedance, θ JA (see Note 2): D package C/W (see Note 2): DB package C/W (see Note 2): N package C/W (see Note 2): NS package C/W (see Note 2): PW package C/W (see Note 3): RGY package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD The package thermal impedance is calculated in accordance with JESD POST OFFICE BOX DALLAS, TEXAS 75265

3 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002 recommended operating conditions (see Note 4) SN54ABT125 SN74ABT125 MIN MAX MIN MAX V CC Supply voltage V V IH High-level input voltage 2 2 V V IL Low-level input voltage V V I Input voltage 0 V CC 0 V CC V I OH High-level output current ma I OL Low-level output current ma Δt/Δv Input transition rise or fall rate ns/v Δt/ΔV CC Power-up ramp rate μs/v T A Operating free-air temperature C NOTE 4: All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. UNIT POST OFFICE BOX DALLAS, TEXAS

4 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS T A = 25 C SN54ABT125 SN74ABT125 MIN TYP MAX MIN MAX MIN MAX V IK V CC = 4.5 V, I I = 18 ma V V CC = 4.5 V, I OH = 3 ma V CC = 5 V, I OH = 3 ma V OH I OH = 24 ma 2 2 V CC = 45V 4.5 I OH = 32 ma 2* 2 V OL V CC = 45V 4.5 I OL = 48 ma I OL = 64 ma 0.55* 0.55 V hys 100 mv I I V CC = 0 to 5.5 V, V I = V CC or GND ±1 ±1 ±1 μa I OZPU V CC = 0 to 2.1 V, V O = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 μa I OZPD V CC = 2.1 V to 0, V O = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 μa I OZH V CC = 2.1 V to 5.5 V, V O = 2.7 V, OE 2 V μa I OZL V CC = 2.1 V to 5.5 V, V O = 0.5 V, OE 2 V μa I off V CC = 0, V I or V O 4.5 V ±100 ±100 μa I CEX V CC = 5.5 V, V O = 5.5 V UNIT Outputs high μa I O V CC = 5.5 V, V O = 2.5 V ma V CC = 5.5 V, Outputs high μa I CC I O = 0, Outputs low ma V I = V CC or GND Outputs disabled μa V CC = 5.5 V, Data One input at 3.4 V, Outputs enabled ΔI CC inputs Other inputs at V CC or GND Outputs disabled ma Control V CC = 5.5 V, One input at 3.4 V, inputs Other inputs at V CC or GND C i V I = 2.5 V or 0.5 V 3 pf C o V O = 2.5 V or 0.5 V 7 pf * On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at V CC = 5 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This limit may vary among suppliers. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V CC or GND. V V 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM TO (INPUT) (OUTPUT) t PLH t PHL A Y t PZH t PZL OE Y t PLZ OE Y t PHZ This limit may vary among suppliers. V CC = 5 V, T A = 25 C SN54ABT125 SN74ABT125 MIN TYP MAX MIN MAX MIN MAX UNIT ns ns ns POST OFFICE BOX DALLAS, TEXAS

6 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I FEBRUARY 1997 REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test C L = 50 pf (see Note A) 500 Ω 500 Ω S1 7 V Open GND TEST t PLH /t PHL t PLZ /t PZL t PHZ /t PZH S1 Open 7 V Open LOAD CIRCUIT Timing Input 1.5 V 3 V 0 V t w Input 1.5 V 1.5 V 3 V 0 V Data Input t su t h 1.5 V 1.5 V 3 V 0 V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input Output Output t PLH t PHL 1.5 V 1.5 V 1.5 V 1.5 V t PHL 1.5 V t PLH 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 3 V 0 V V OH V OL V OH V OL Output Control Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) t PZL t PZH 1.5 V t PLZ 1.5 V t PHZ 1.5 V 1.5 V V OL V V OH 0.3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50 Ω, t r 2.5 ns, t f 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 3 V 0 V 3.5 V V OL V OH 0 V 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 PACKAGE OPTION ADDENDUM 17-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to Q2A SNJ54ABT 125FK Device Marking QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to QC A SNJ54ABT125J QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to QD A SNJ54ABT125W SN74ABT125D ACTIVE SOIC D Green (RoHS SN74ABT125DBR ACTIVE SSOP DB Green (RoHS SN74ABT125DBRG4 ACTIVE SSOP DB Green (RoHS SN74ABT125DE4 ACTIVE SOIC D Green (RoHS SN74ABT125DG4 ACTIVE SOIC D Green (RoHS SN74ABT125DR ACTIVE SOIC D Green (RoHS SN74ABT125DRE4 ACTIVE SOIC D Green (RoHS SN74ABT125DRG4 ACTIVE SOIC D Green (RoHS SN74ABT125N ACTIVE PDIP N Pb-Free (RoHS) SN74ABT125NE4 ACTIVE PDIP N Pb-Free (RoHS) SN74ABT125NSR ACTIVE SO NS Green (RoHS SN74ABT125NSRG4 ACTIVE SO NS Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT125 CU NIPDAU N / A for Pkg Type -40 to 85 SN74ABT125N CU NIPDAU N / A for Pkg Type -40 to 85 SN74ABT125N CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT125 (4/5) Samples Addendum-Page 1

8 PACKAGE OPTION ADDENDUM 17-Mar-2017 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan SN74ABT125PW ACTIVE TSSOP PW Green (RoHS SN74ABT125PWE4 ACTIVE TSSOP PW Green (RoHS SN74ABT125PWG4 ACTIVE TSSOP PW Green (RoHS SN74ABT125PWR ACTIVE TSSOP PW Green (RoHS SN74ABT125PWRE4 ACTIVE TSSOP PW Green (RoHS SN74ABT125PWRG4 ACTIVE TSSOP PW Green (RoHS SN74ABT125RGYR ACTIVE VQFN RGY Green (RoHS SN74ABT125RGYRG4 ACTIVE VQFN RGY Green (RoHS (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB125 CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB125 CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AB125 CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AB125 SNJ54ABT125FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to Q2A SNJ54ABT 125FK Device Marking SNJ54ABT125J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to QC A SNJ54ABT125J SNJ54ABT125W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to QD A SNJ54ABT125W (4/5) Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 2

9 PACKAGE OPTION ADDENDUM 17-Mar-2017 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT125, SN74ABT125 : Catalog: SN74ABT125 Military: SN54ABT125 NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications Addendum-Page 3

10 PACKAGE MATERIALS INFORMATION 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74ABT125DBR SSOP DB Q1 SN74ABT125DR SOIC D Q1 SN74ABT125DR SOIC D Q1 SN74ABT125NSR SO NS Q1 SN74ABT125PWR TSSOP PW Q1 SN74ABT125RGYR VQFN RGY Q1 Pack Materials-Page 1

11 PACKAGE MATERIALS INFORMATION 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT125DBR SSOP DB SN74ABT125DR SOIC D SN74ABT125DR SOIC D SN74ABT125NSR SO NS SN74ABT125PWR TSSOP PW SN74ABT125RGYR VQFN RGY Pack Materials-Page 2

24 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DALLAS, TEXAS 75265

SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS Typical V OLP (Output Ground Bounce)