SINGLE INVERTER GATE Check for Samples: SN74LVC1G04

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1 1 SN74LVC1G04 SCES214Z APRIL 1999 REVISED NOVEMBER 2012 SINGLE INVERTER GATE Check for Samples: SN74LVC1G04 1FEATURES 2 Available in the Texas Instruments NanoFree I off Supports Live Insertion, Partial Power Package Down Mode, and Back Drive Protection Supports 5-V Operation Latch-Up Performance Exceeds 100 ma Per Inputs Accept Voltages to 5.5 V JESD 78, Class II Max t pd of 3.3 ns at 3.3 V ESD Protection Exceeds JESD 22 Low Power Consumption, 10- A Max I CC 2000-V Human-Body Model (A114-A) ±24-mA Drive at 3.3 V 200-achine Model (A115-A) 1000-V Charged-Device Model (C101) DBV PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) DRL PACKAGE (TOP VIEW) NC A NC 1 5 A Y NC A Y 3 4 Y DRY PACKAGE (TOP VIEW) DSF PACKAGE (TOP VIEW) NC No internal connection See mechanical drawings for dimensions. NC 1 6 NC A 2 5 NC A 3 4 Y NC Y YZP PACKAGE (TOP VIEW) DNU A DNU Do not use YZV PACKAGE (TOP VIEW) A A1 B1 C1 A1 B1 A2 B2 C2 A2 B2 Y Y Table 1. YZP PACKAGE TERMINAL ASSIGNMENTS 1 2 A DNU B A No ball C Y Table 2. YZV PACKAGE TERMINAL ASSIGNMENTS 1 2 A A B Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright , Texas Instruments Incorporated

2 SN74LVC1G04 SCES214Z APRIL 1999 REVISED NOVEMBER DESCRIPTION/ORDERING INFORMATION This single inverter gate is designed for 1.65-V to 5.5-V operation. The SN74LVC1G04 performs the Boolean function Y = A. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Table 3. ORDERING INFORMATION T A PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (3) NanoFree WCSP (DSBGA) 0.23-mm Large Bump YZP (Pb- SN74LVC1G04YZPR _ CC_ free) NanoFree WCSP (DSBGA) 0.23-mm Large Bump YZV (Pb- SN74LVC1G04YZVR _ CC_ free) SN74LVC1G04DSFR µqfn DSF Reel of 5000 CC SN74LVC1G04DSF2 (4) SN74LVC1G04DRYR 40 C to 85 C QFN DRY Reel of 5000 CC SN74LVC1G04DRYRG4 SOT (SOT-23) DBV SOT (SC-70) DCK Reel of 3000 Reel of 250 Reel of 3000 Reel of 250 Jumbo Reel of SN74LVC1G04DBVR SN74LVC1G04DBVT SN74LVC1G04DCKR SN74LVC1G04DCKT SN74LVC1G04DCKJ SOT (SOT-553) DRL Reel of 4000 SN74LVC1G04DRLR (1) Package drawings, thermal data, and symbolization are available at (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at (3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YZP/YZV: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free). (4) Pin 1 orientation at quadrant 3 in Tape. C04_ CC_ 2 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: SN74LVC1G04

3 SN74LVC1G04 SCES214Z APRIL 1999 REVISED NOVEMBER 2012 FUNCTION TABLE INPUT OUTPUT A Y H L L H LOGIC DIAGRAM (POSITIVE LOGIC) (DBV, DCK, DRL, DRY, DSF, AND YZP PACKAGE) A 2 4 Y LOGIC DIAGRAM (POSITIVE LOGIC) (YZV PACKAGE) A 1 3 Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage range V Input voltage range V V O Voltage range applied to any output in the high-impedance or power-off state (2) V V O Voltage range applied to any output in the high or low state (2) (3) V I IK Input clamp current < 0 50 ma I OK clamp current V O < 0 50 ma I O Continuous output current ±50 ma Continuous current through or ±100 ma DBV package 206 DCK package 252 DRL package 142 JA Package thermal impedance (4) DRY package 234 C/W YZP package 132 YZV package 116 DSF package 300 T stg Storage temperature range C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of is provided in the recommended operating conditions table. (4) The package thermal impedance is calculated in accordance with JESD Copyright , Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SN74LVC1G04

4 Recommended Operating Conditions (1) MIN MAX UNIT SN74LVC1G04 SCES214Z APRIL 1999 REVISED NOVEMBER Operating Supply voltage V Data retention only 1.5 = 1.65 V to 1.95 V 0.65 = 2.3 V to 2.7 V 1.7 H High-level input voltage V = 3 V to 3.6 V 2 = 4.5 V to 5.5 V = 1.65 V to 1.95 V = 2.3 V to 2.7 V 0.7 L Low-level input voltage V = 3 V to 3.6 V 0.8 = 4.5 V to 5.5 V 0.3 Input voltage V V O voltage 0 V = 1.65 V 4 = 2.3 V 8 I OH High-level output current 16 ma = 3 V 24 = 4.5 V 32 = 1.65 V 4 = 2.3 V 8 I OL Low-level output current 16 ma = 3 V 24 = 4.5 V 32 = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 t/ v Input transition rise or fall rate = 3.3 V ± 0.3 V 10 ns/v = 5 V ± 0.5 V 5 T A Operating free-air temperature C (1) All unused inputs of the device must be held at or to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: SN74LVC1G04

5 SN74LVC1G04 SCES214Z APRIL 1999 REVISED NOVEMBER 2012 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT V OH V OL I OH = 100 A 1.65 V to 5.5 V 0.1 I OH = 4 ma 1.65 V 1.2 I OH = 8 ma 2.3 V 1.9 I OH = 16 ma V I OH = 24 ma 2.3 I OH = 32 ma 4.5 V 3.8 I OL = 100 A 1.65 V to 5.5 V 0.1 I OL = 4 ma 1.65 V 0.45 I OL = 8 ma 2.3 V 0.3 I OL = 16 ma V I OL = 24 ma 0.55 I OL = 32 ma 4.5 V 0.55 I I A input = 5.5 V or 0 to 5.5 V ±5 A I off or V O = 5.5 V 0 ±10 A I CC = 5.5 V or I O = V to 5.5 V 10 A I CC One input at 0.6 V, Other inputs at or 3 V to 5.5 V 500 A C i = or 3.3 V 3.5 pf (1) All typical values are at = 3.3 V, T A = 25 C. V V Copyright , Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN74LVC1G04

6 SN74LVC1G04 SCES214Z APRIL 1999 REVISED NOVEMBER Switching Characteristics over recommended operating free-air temperature range, C L = 15 pf (unless otherwise noted) (see Figure 1) = 1.8 V = 2.5 V = 3.3 V = 5 V FROM TO PARAMETER ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX t pd A Y ns Switching Characteristics over recommended operating free-air temperature range, C L = 30 pf or 50 pf (unless otherwise noted) (see Figure 2) = 1.8 V = 2.5 V = 3.3 V = 5 V FROM TO PARAMETER ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX t pd A Y ns Operating Characteristics T A = 25 C TEST = 1.8 V = 2.5 V = 3.3 V = 5 V PARAMETER UNIT CONDITIONS TYP TYP TYP TYP C pd Power dissipation capacitance f = 10 MHz pf 6 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: SN74LVC1G04

7 SN74LVC1G04 SCES214Z APRIL 1999 REVISED NOVEMBER 2012 PARAMETER MEASUREMENT INFORMATION From Under Test C L (see Note A) R L R L S1 V LOAD Open TEST t PLH /t PHL t PLZ /t PZL t PHZ /t PZH S1 Open V LOAD LOAD CIRCUIT INPUTS t r /t f V LOAD C L R L V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 3 V 2 ns 2 ns 2.5 ns 2.5 ns VCC/2 /2 1.5 V / V 2 15 pf 15 pf 15 pf 15 pf 1 MΩ 1 MΩ 1 MΩ 1 MΩ 0.15 V 0.15 V 0.3 V 0.3 V t w Timing Input t su t h Input Data Input VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input Control t PLH t PHL V OH V OL Waveform 1 S1 at V LOAD (see Note B) t PZL t PLZ V OL + V V LOAD /2 V OL t PHL t PLH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS V OH V OL Waveform 2 S1 at (see Note B) t PZH t PHZ V OH V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING V OH NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. t PLZ and t PHZ are the same as t dis. F. t PZL and t PZH are the same as t en. G. t PLH and t PHL are the same as t pd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Copyright , Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: SN74LVC1G04

8 SN74LVC1G04 SCES214Z APRIL 1999 REVISED NOVEMBER PARAMETER MEASUREMENT INFORMATION From Under Test C L (see Note A) R L R L S1 V LOAD Open TEST t PLH /t PHL t PLZ /t PZL t PHZ /t PZH S1 Open V LOAD LOAD CIRCUIT INPUTS t r /t f V LOAD C L R L V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 3 V 2 ns 2 ns 2.5 ns 2.5 ns VCC/2 /2 1.5 V / V 2 30 pf 30 pf 50 pf 50 pf 1 kω 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V t w Timing Input t su t h Input Data Input VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input Control t PLH t PHL V OH V OL Waveform 1 S1 at V LOAD (see Note B) t PZL t PLZ V OL + V V LOAD /2 V OL t PHL t PLH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS V OH V OL Waveform 2 S1 at (see Note B) t PZH t PHZ V OH V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING V OH NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. t PLZ and t PHZ are the same as t dis. F. t PZL and t PZH are the same as t en. G. t PLH and t PHL are the same as t pd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: SN74LVC1G04

9 SN74LVC1G04 SCES214Z APRIL 1999 REVISED NOVEMBER 2012 REVISION HISTORY Changes from Revision X (June 2011) to Revision Y Page Added new orderable package type SN74LVC1G04DSF Changes from Revision Y (October 2011) to Revision Z Page Added Jumbo Reel to ORDERING INFORMATION TABLE Copyright , Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74LVC1G04

10 PACKAGE OPTION ADDENDUM 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan SN74LVC1G04DBVR ACTIVE SOT-23 DBV Green (RoHS SN74LVC1G04DBVRE4 ACTIVE SOT-23 DBV Green (RoHS SN74LVC1G04DBVRG4 ACTIVE SOT-23 DBV Green (RoHS SN74LVC1G04DBVT ACTIVE SOT-23 DBV Green (RoHS SN74LVC1G04DBVTE4 ACTIVE SOT-23 DBV Green (RoHS SN74LVC1G04DBVTG4 ACTIVE SOT-23 DBV Green (RoHS SN74LVC1G04DCKR ACTIVE SC70 DCK Green (RoHS SN74LVC1G04DCKRE4 ACTIVE SC70 DCK Green (RoHS SN74LVC1G04DCKRG4 ACTIVE SC70 DCK Green (RoHS SN74LVC1G04DCKT ACTIVE SC70 DCK Green (RoHS SN74LVC1G04DCKTE4 ACTIVE SC70 DCK Green (RoHS SN74LVC1G04DCKTG4 ACTIVE SC70 DCK Green (RoHS SN74LVC1G04DRLR ACTIVE SOT DRL Green (RoHS SN74LVC1G04DRLRG4 ACTIVE SOT DRL Green (RoHS SN74LVC1G04DRYR ACTIVE SON DRY Green (RoHS SN74LVC1G04DRYRG4 ACTIVE SON DRY Green (RoHS (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp ( C) Top-Side Markings CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C042 ~ C045 ~ C04F ~ C04K ~ C04R) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C042 ~ C045 ~ C04F ~ C04K ~ C04R) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C042 ~ C045 ~ C04F ~ C04K ~ C04R) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C045 ~ C04F ~ C04K ~ C04R) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C045 ~ C04F ~ C04K ~ C04R) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C045 ~ C04F ~ C04K ~ C04R) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC5 ~ CCF ~ CCK ~ CCR) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC5 ~ CCF ~ CCK ~ CCR) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC5 ~ CCF ~ CCK ~ CCR) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC5 ~ CCF ~ CCK ~ CCR) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC5 ~ CCF ~ CCK ~ CCR) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC5 ~ CCF ~ CCK ~ CCR) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC7 ~ CCR) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC7 ~ CCR) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CC CU NIPDAU Level-1-260C-UNLIM -40 to 85 CC (4) Addendum-Page 1 Samples

11 PACKAGE OPTION ADDENDUM 11-Apr-2013 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan SN74LVC1G04DSF2 ACTIVE SON DSF Green (RoHS SN74LVC1G04DSFR ACTIVE SON DSF Green (RoHS SN74LVC1G04YZPR ACTIVE DSBGA YZP Green (RoHS SN74LVC1G04YZVR ACTIVE DSBGA YZV Green (RoHS (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp ( C) Top-Side Markings CU NIPDAU Level-1-260C-UNLIM -40 to 85 CC CU NIPDAU Level-1-260C-UNLIM -40 to 85 CC SNAGCU Level-1-260C-UNLIM -40 to 85 (CC2 ~ CC7 ~ CCN) SNAGCU Level-1-260C-UNLIM -40 to 85 CC (2 ~ 7) (4) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 Samples

12 PACKAGE OPTION ADDENDUM 11-Apr-2013 OTHER QUALIFIED VERSIONS OF SN74LVC1G04 : Automotive: SN74LVC1G04-Q1 Enhanced Product: SN74LVC1G04-EP NOTE: Qualified Version Definitions: Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3

13 PACKAGE MATERIALS INFORMATION 28-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter Reel Width W1 A0 B0 K0 P1 W Pin1 Quadrant SN74LVC1G04DBVR SOT-23 DBV Q3 SN74LVC1G04DBVR SOT-23 DBV Q3 SN74LVC1G04DBVR SOT-23 DBV Q3 SN74LVC1G04DBVR SOT-23 DBV Q3 SN74LVC1G04DBVT SOT-23 DBV Q3 SN74LVC1G04DBVT SOT-23 DBV Q3 SN74LVC1G04DCKR SC70 DCK Q3 SN74LVC1G04DCKR SC70 DCK Q3 SN74LVC1G04DCKR SC70 DCK Q3 SN74LVC1G04DCKT SC70 DCK Q3 SN74LVC1G04DCKT SC70 DCK Q3 SN74LVC1G04DCKT SC70 DCK Q3 SN74LVC1G04DRLR SOT DRL Q3 SN74LVC1G04DRLR SOT DRL Q3 SN74LVC1G04DRYR SON DRY Q1 SN74LVC1G04DSF2 SON DSF Q3 SN74LVC1G04DSFR SON DSF Q2 SN74LVC1G04YZPR DSBGA YZP Q1 Pack Materials-Page 1

14 PACKAGE MATERIALS INFORMATION 28-Jun-2013 Device Package Type Package Drawing Pins SPQ Reel Diameter Reel Width W1 A0 B0 K0 P1 W Pin1 Quadrant SN74LVC1G04YZVR DSBGA YZV Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length Width Height SN74LVC1G04DBVR SOT-23 DBV SN74LVC1G04DBVR SOT-23 DBV SN74LVC1G04DBVR SOT-23 DBV SN74LVC1G04DBVR SOT-23 DBV SN74LVC1G04DBVT SOT-23 DBV SN74LVC1G04DBVT SOT-23 DBV SN74LVC1G04DCKR SC70 DCK SN74LVC1G04DCKR SC70 DCK SN74LVC1G04DCKR SC70 DCK SN74LVC1G04DCKT SC70 DCK SN74LVC1G04DCKT SC70 DCK SN74LVC1G04DCKT SC70 DCK SN74LVC1G04DRLR SOT DRL SN74LVC1G04DRLR SOT DRL SN74LVC1G04DRYR SON DRY SN74LVC1G04DSF2 SON DSF Pack Materials-Page 2

15 PACKAGE MATERIALS INFORMATION 28-Jun-2013 Device Package Type Package Drawing Pins SPQ Length Width Height SN74LVC1G04DSFR SON DSF SN74LVC1G04YZPR DSBGA YZP SN74LVC1G04YZVR DSBGA YZV Pack Materials-Page 3

ORDERING INFORMATION SOT (SOT-23) DBV SOT (SC-70) DCK

ORDERING INFORMATION SOT (SOT-23) DBV SOT (SC-70) DCK www.ti.com FEATURES Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V V CC Operation Inputs Accept Voltages to 5.5 V Max t pd of 4.1 ns at 3.3 V Low Power Consumption, 10-µA