High Precision OPERATIONAL AMPLIFIERS

Transcription

1 OPA OPA OPA OPA OPA OPA OPA OPA OPA OPA OPA High Precision OPERATIONAL AMPLIFIERS SBOS09A MARCH 999 REVISED APRIL 00 FEATURES ULTRA LOW OFFSET VOLTAGE: 0µV ULTRA LOW DRIFT: ±0.µV/ C HIGH OPEN-LOOP GAIN: db HIGH COMMON-MODE REJECTION: 0dB HIGH POWER SUPPLY REJECTION: 0dB LOW BIAS CURRENT: na max WIDE SUPPLY RANGE: ±V to ±V LOW QUIESCENT CURRENT: 00µA/amplifier SINGLE, DUAL, AND QUAD VERSIONS REPLACES OP-0, OP-, OP- APPLICATIONS TRANSDUCER AMPLIFIER BRIDGE AMPLIFIER TEMPERATURE MEASUREMENTS STRAIN GAGE AMPLIFIER PRECISION INTEGRATOR BATTERY POWERED INSTRUMENTS TEST EQUIPMENT Offset Trim In OPA Offset Trim DESCRIPTION The OPA series precision op amps replace the industry standard OP-. They offer improved noise, wider output voltage swing, and are twice as fast with half the quiescent current. Features include ultra low offset voltage and drift, low bias current, high common-mode rejection, and high power supply rejection. Single, dual, and quad versions have identical specifications for maximum design flexibility. OPA series op amps operate from ±V to ±V supplies with excellent performance. Unlike most op amps which are specified at only one supply voltage, the OPA series is specified for real-world applications; a single limit applies over the ±V to ±V supply range. High performance is maintained as the amplifiers swing to their specified limits. Because the initial offset voltage (±0µV max) is so low, user adjustment is usually not required. However, the single version (OPA) provides external trim pins for special applications. OPA op amps are easy to use and free from phase inversion and overload problems found in some other op amps. They are stable in unity gain and provide excellent dynamic behavior over a wide range of load conditions. Dual and quad versions feature completely independent circuitry for lowest crosstalk and freedom from interaction, even when overdriven or overloaded. Single (OPA) and dual (OPA) versions are available in DIP-, SO-, and DFN- (mm x mm) packages. The quad (OPA) comes in DIP- and SO- surface-mount packages. All are fully specified from 0 C to + C and operate from C to + C. OPAAIDRM +In V -Pin DIP, SO- Output NC Out A In A +In A A OPA D Out D In D +In D OPAAIDRM Offset Trim In +In Pin Indicator Offset Trim Output V V NC Out A In A OPA A +In B In B Out B Out B B -Pin DIP, SO- C 0 9 +In C In C Out C Out A In A +In A Pin Indicator Out B In B DFN- mm x mm (top view) Thermal Pad on Bottom (Connect to V ) +In A B In B V +In B V +In B -Pin DIP, SO- NC = No connection. DFN- mm x mm (top view) Thermal Pad on Bottom (Connect to V ) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright , Texas Instruments Incorporated

2 ABSOLUTE MAXIMUM RATINGS () Supply Voltage... V Input Voltage... (V ) 0.V to () +0.V Output Short-Circuit ()... Continuous Operating Temperature... C to + C Storage Temperature... C to + C Junction Temperature... 0 C Lead Temperature (soldering, 0s) C ESD Rating (Human Body Model) V (Machine Model)... 00V NOTE: () Stresses above these rating may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. () Short-circuit to ground, one amplifier per package. PACKAGE/ORDERING INFORMATION () ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. OFFSET OFFSET VOLTAGE VOLTAGE DRIFT PRODUCT max, µv max, µv/ C PACKAGE-LEAD Single OPAPA ±0 ± DIP- OPAP ±0 ±0. DIP- OPAUA ±0 ± SO- Surface Mount OPAU ±0 ±0. SO- Surface Mount OPAAIDRM ±00 ± DFN- (mm x mm) Dual OPAPA ±0 ± DIP- OPAP ± ±0. DIP- OPAUA ±0 ± SO- Surface Mount OPAU ± ±0. SO- Surface Mount OPAAIDRM ±00 ± DFN- (mm x mm) Quad OPAPA ±0 ± DIP- OPAUA ±0 ± SO- Surface Mount NOTE: () For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet or visit the TI web site at. PIN DESCRIPTIONS OPA OPAAIDRM Offset Trim Offset Trim Out A Out B In +In Output In A Pin Indicator V NC () OPA +In A In B -Pin DIP, SO- Out A Out D V +In B In A +In A +In B In B A B D C 0 9 In D +In D V +In C In C Offset Trim DFN- mm x mm (top view) OPAAIDRM Thermal Pad on Bottom (Connect to V ) Offset Trim OPA Out B -Pin DIP, SO- Out C In Pin Indicator Out A +In Output In A +In A A B Out B In B V NC V -Pin DIP, SO- +In B NOTE: () NC = No connection. DFN- mm x mm (top view) Thermal Pad on Bottom (Connect to V ) OPA, OPA, OPA SBOS09A

3 ELECTRICAL CHARACTERISTICS: V S = ±V to V S = ±V At T A = + C, and R L = kω, unless otherwise noted. Boldface limits apply over the specified temperature range, 0 C to + C. OPAPA, UA OPAP, U OPAPA, UA OPAAIDRM, OPAP, U OPAPA, UA OPAAIDRM PARAMETER CONDITION MIN TYP () MAX MIN TYP () MAX MIN TYP () MAX UNITS OFFSET VOLTAGE Input Offset Voltage: V OS OPAP, U (high grade, single) ±0 ±0 µv OPAP, U (high grade, dual) ±0 ± µv All PA, UA, Versions ±0 ±0 µv AIDRM Versions ± ±00 µv Input Offset Voltage Over Temperature OPAP, U (high grade, single) T A = 0 C to + C ±0 µv OPAP, U (high grade, dual) T A = 0 C to + C ±0 µv All PA, UA, Versions T A = 0 C to + C ±00 µv AIDRM Versions T A = 0 C to + C ± µv Input Offset Voltage Drift dv OS /dt OPAP, U (high grade, single) T A = 0 C to + C ±0. ±0. µv/ C OPAP, U (high grade, dual) T A = 0 C to + C ±0. ±0. µv/ C All PA, UA, AIDRM Versions T A = 0 C to + C ±0. ± ±0. ± µv/ C Input Offset Voltage: (all models) vs Time 0. µv/mo vs Power Supply PSRR V S = ±V to ±V ±0. ±0. ± ± µv/v T A = 0 C to + C V S = ±V to ±V ±0. ± ± µv/v Channel Separation (dual, quad) dc 0. µv/v INPUT BIAS CURRENT Input Bias Current I B ±0. ± ±. ±. na T A = 0 C to + C ± ± ± na Input Offset Current I OS ±0. ± ±. ±. na T A = 0 C to + C ± ± ± na NOISE Input Voltage Noise, f = 0. to 0Hz 0. µv PP 0.0 µvrms Input Voltage Noise Density, f = 0Hz e n nv/ Hz f = 00Hz nv/ Hz f = khz nv/ Hz f = 0kHz nv/ Hz Current Noise Density, f = khz i n 0. pa/ Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range V CM (V ) + () V Common-Mode Rejection CMRR V CM = (V ) +V to () V 0 0 db T A = 0 C to + C V CM = (V ) +V to () V db INPUT IMPEDANCE Differential 00 MΩ pf Common-Mode V CM = (V ) +V to () V 0 GΩ pf OPEN-LOOP GAIN Open-Loop Voltage Gain A OL V O = (V )+0.V to ().V, R L = 0kΩ 0 db V O = (V )+.V to ().V, R L = kω db T A = 0 C to + C V O = (V )+.V to ().V, R L = kω db FREQUENCY RESPONSE Gain-Bandwidth Product GBW MHz Slew Rate SR 0. V/µs Settling Time, 0.% V S = ±V, G =, 0V Step µs 0.0% V S = ±V, G =, 0V Step µs Overload Recovery Time V IN G = V S µs Total Harmonic Distortion + Noise THD+N khz, G =, V O =.Vrms 0.00 % Specifications same as OPAP, U. NOTE: () V S = ±V. OPA, OPA, OPA SBOS09A

4 ELECTRICAL CHARACTERISTICS: V S = ±V to V S = ±V (CONT) At T A = + C, and R L = kω, unless otherwise noted. Boldface limits apply over the specified temperature range, 0 C to + C. OPAPA, UA OPAP, U OPAPA, UA OPAAIDRM, OPAP, U OPAPA, UA OPAAIDRM PARAMETER CONDITION MIN TYP () MAX MIN TYP () MAX MIN TYP () MAX UNITS OUTPUT Voltage Output V O R L = 0kΩ (V ) +0. (). V T A = 0 C to + C R L = 0kΩ (V ) +0. (). V R L = kω (V ) +. (). V T A = 0 C to + C R L = kω (V ) +. (). V Short-Circuit Current I SC ± ma Capacitive Load Drive C LOAD See Typical Curve POWER SUPPLY Specified Voltage Range V S ± ± V Operating Voltage Range ± ± V Quiescent Current (per amplifier) I Q I O = 0 ±90 ± µa T A = 0 C to + C I O = 0 ±900 µa TEMPERATURE RANGE Specified Range 0 + C Operating Range + C Storage Range + C Thermal Resistance θ JA SO- Surface-Mount 0 C/W DIP- 00 C/W DIP- 0 C/W SO- Surface-Mount 00 C/W DFN- () C/W Specifications same as OPAP, U. NOTES: () V S = ±V. () Thermal pad soldered to printed circuit board (PCB). OPA, OPA, OPA SBOS09A

5 TYPICAL CHARACTERISTICS At T A = + C, V S = ±V, and R L = kω, unless otherwise noted. A OL (db) G φ OPEN-LOOP GAIN/PHASE vs FREQUENCY C L = 0 C L = 00pF Phase ( ) PSR, CMR (db) POWER SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY PSR +PSR CMR k 0k 00k M 0M Frequency (Hz) k 0k 00k M Frequency (Hz) 000 INPUT NOISE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY INPUT NOISE VOLTAGE vs TIME Voltage Noise (nv/ Hz) Current Noise (fa/ Hz) 00 0 Current Noise Voltage Noise 0nV/div Noise signal is bandwidth limited to lie between 0.Hz and 0Hz k 0k Frequency (Hz) s/div 0 CHANNEL SEPARATION vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY V OUT =.Vrms Channel Separation (db) Dual and quad devices. G =, all channels. Quad measured channel A to D or B to C other combinations yield similar or improved rejection. THD+Noise (%) G = 0, R L = kω, 0kΩ G =, R L = kω, 0kΩ k 0k 00k Frequency (Hz) M k 0k 00k Frequency (Hz) OPA, OPA, OPA SBOS09A

6 TYPICAL CHARACTERISTICS (CONT) At T A = + C, V S = ±V, and R L = kω, unless otherwise noted. Percent of Amplifiers (%) 0 OFFSET VOLTAGE PRODUCTION DISTRIBUTION Typical distribution of packaged units. Single, dual, and quad included. Percent of Amplifiers (%) OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION Typical distribution of packaged units. Single, dual, and quad included Offset Voltage (µv) Offset Voltage (µv/ C) WARM-UP OFFSET VOLTAGE DRIFT 0 A OL, CMR, PSR vs TEMPERATURE Offset Voltage Change (µv) 0 A OL, CMR, PSR (db) CMR A OL PSR Time from Power Supply Turn-On (s) Temperature ( C) INPUT BIAS CURRENT vs TEMPERATURE 000 QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE Input Bias Current (na) 0 Curves represent typical production units Quiescent Current (µa) I SC I SC ±I Q Short-Circuit Current (ma) Temperature ( C) Temperature ( C) OPA, OPA, OPA SBOS09A

7 TYPICAL CHARACTERISTICS (CONT) At T A = + C, V S = ±V, and R L = kω, unless otherwise noted. I B (na) CHANGE IN INPUT BIAS CURRENT vs POWER SUPPLY VOLTAGE V CM = 0V Curve shows normalized change in bias current with respect to V S = ±0V (+0V). Typical I B may range from 0.nA to +0.nA at V S = ±0V. I B (na) CHANGE IN INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE Curve shows normalized change in bias current with respect to V CM = 0V. Typical I B may range from 0.nA to +0.nA at V CM = 0V. V S = ±V V S = ±V Supply Voltage (V) Common-Mode Voltage (V) Quiescent Current (µa) QUIESCENT CURRENT vs SUPPLY VOLTAGE per amplifier Settling Time (µs) SETTLING TIME vs CLOSED-LOOP GAIN 0V step C L = 00pF 0.0% 0.% 00 0 ± ±0 ± ±0 Supply Voltage (V) 0 ± ±0 ±00 Gain (V/V) Output Voltage (V PP ) MAXIMUM OUTPUT VOLTAGE vs FREQUENCY V S = ±V V S = ±V 0 k 0k 00k Frequency (Hz) M Output Voltage Swing (V) () () () () () () (V ) + (V ) + (V ) + (V ) + (V ) + (V ) OUTPUT VOLTAGE SWING vs OUTPUT CURRENT C C C C C C 0 ± ±0 ± ±0 ± ±0 Output Current (ma) OPA, OPA, OPA SBOS09A

8 TYPICAL CHARACTERISTICS (CONT) At T A = + C, V S = ±V, and R L = kω, unless otherwise noted. 0 0 SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE Gain = LARGE-SIGNAL STEP RESPONSE G = +, CL = 00pF, V S = +V Overshoot (%) Gain = + V/div 0 Gain = ± k 0k 00k Load Capacitance (pf) 0µs/div SMALL-SIGNAL STEP RESPONSE G = +, C L = 0, V S = ±V SMALL-SIGNAL STEP RESPONSE G = +, C L = 00pF, V S = ±V 0mV/div 0mV/div µs/div µs/div OPA, OPA, OPA SBOS09A

9 APPLICATIONS INFORMATION The OPA series is unity-gain stable and free from unexpected output phase reversal, making it easy to use in a wide range of applications. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins. In most cases 0.µF capacitors are adequate. The OPA series has very low offset voltage and drift. To achieve highest performance, circuit layout and mechanical conditions should be optimized. Offset voltage and drift can be degraded by small thermoelectric potentials at the op amp inputs. Connections of dissimilar metals will generate thermal potential which can degrade the ultimate performance of the OPA series. These thermal potentials can be made to cancel by assuring that they are equal in both input terminals. Keep thermal mass of the connections made to the two input terminals similar. Locate heat sources as far as possible from the critical input circuitry. Shield op amp and input circuitry from air currents such as cooling fans. OPERATING VOLTAGE OPA series op amp operate from ±V to ±V supplies with excellent performance. Unlike most op amps which are specified at only one supply voltage, the OPA series is specified for real-world applications; a single limit applies over the ±V to ±V supply range. This allows a customer operating at V S = ±0V to have the same assured performance as a customer using ±V supplies. In addition, key parameters are assured over the specified temperature range, 0 C to + C. Most behavior remains unchanged through the full operating voltage range (±V to ±V). Parameters which vary significantly with operating voltage or temperature are shown in typical performance curves. OFFSET VOLTAGE ADJUSTMENT The OPA series is laser-trimmed for very low offset voltage and drift so most circuits will not require external adjustment. However, offset voltage trim connections are provided on pins and. Offset voltage can be adjusted by connecting a potentiometer as shown in Figure. This adjustment should be used only to null the offset of the op amp. This adjustment should not be used to compensate for offsets created elsewhere in a system since this can introduce additional temperature drift. 0.µF 0.µF V 0kΩ OPA Trim Range: Exceeds Offset Voltage Specification OPA single op amp only. Use offset adjust pins only to null offset voltage of op amp see text. FIGURE. OPA Offset Voltage Trim Circuit. INPUT PROTECTION The inputs of the OPA series are protected with kω series input resistors and diode clamps. The inputs can withstand ±0V differential inputs without damage. The protection diodes will, of course, conduct current when the inputs are over-driven. This may disturb the slewing behavior of unity-gain follower applications, but will not damage the op amp. INPUT BIAS CURRENT CANCELLATION The input stage base current of the OPA series is internally compensated with an equal and opposite cancellation circuit. The resulting input bias current is the difference between the input stage base current and the cancellation current. This residual input bias current can be positive or negative. When the bias current is canceled in this manner, the input bias current and input offset current are approximately the same magnitude. As a result, it is not necessary to use a bias current cancellation resistor as is often done with other op amps (Figure ). A resistor added to cancel input bias current errors may actually increase offset voltage and noise. R R R R Op Amp OPA R B = R R (a) Conventional op amp with external bias current cancellation resistor. (b) No bias current cancellation resistor (see text) OPA with no external bias current cancellation resistor. FIGURE. Input Bias Current Cancellation. OPA, OPA, OPA 9 SBOS09A

10 / OPA R V OUT = (V V )( + ) R R V V R R R+ R Load Cell R+ R V R R / OPA R V R R For integrated solution see: INA, INA (dual) INA (on-board reference) INA (single-supply) FIGURE. Load Cell Amplifier. I REG ma V Type J / OPA V LIN + V IN I R I R 0 V REG R F 0kΩ R G R Ω R F 0kΩ R G 0Ω R G XTR0 B E 9 0Ω kω / OPA V V IN I RET I O + I O = ma + (V IN V IN ) 0 R G Ω R CM = 0Ω 0.0µF R (G = + F = 0) R FIGURE. Thermocouple Low Offset, Low Drift Loop Measurement with Diode Cold Junction Compensation. 0 OPA, OPA, OPA SBOS09A

11 DFN PACKAGE The OPA series uses the -lead DFN (also known as SON), which is a QFN package with contacts on only two sides of the package bottom. This leadless, near-chip-scale package maximizes board space and enhances thermal and electrical characteristics through an exposed pad. DFN packages are physically small, have a smaller routing area, improved thermal performance, and improved electrical parasitics, with a pinout scheme that is consistent with other commonly-used packages, such as SO and MSOP. Additionally, the absence of external leads eliminates bent-lead issues. The DFN package can be easily mounted using standard printed circuit board (PCB) assembly techniques. See Application Note, QFN/SON PCB Attachment (SLUA) and Application Report, Quad Flatpack No-Lead Logic Packages (SCBA0), both available for download at. The exposed leadframe die pad on the bottom of the package should be connected to V. LAYOUT GUIDELINES The leadframe die pad should be soldered to a thermal pad on the PCB. Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad. Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and longterm reliability. OPA, OPA, OPA SBOS09A

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