EPC5 EPC5 Enhancement Mode Power Transistor V DSS, 4 V R DS(ON), 4 mw I D, A PRELIMINARY EFFICIENT POWER CONVERSION HAL Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 55 years. GaN s exceptionally high electron mobility and low temperature coefficient allows very low R DS(ON), while its lateral device structure and majority carrier diode provide exceptionally low Q G and zero Q RR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings V DS Drain-to-Source Voltage 4 V Continuous (T A = 5 C, θ JA = ) I D Pulsed (5 C, Tpulse = µs) 5 Gate-to-Source Voltage 6 V GS Gate-to-Source Voltage -5 T J Operating Temperature -4 to 5 T STG Storage Temperature -4 to 5 A V C EPC5 egan FETs are supplied only in passivated die form with solder bars Applications High Speed DC-DC conversion Class D Audio Hard Switched and High Frequency Circuits Benefits Ultra High Efficiency Ultra Low R DS(on) Ultra low Q G Ultra small footprint PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics (T J = 5 C unless otherwise stated) BV DSS Drain-to-Source Voltage V GS = V, I D = 5 µa 4 V I DSS Drain Source Leakage V DS = V, V GS = V 4 µa Gate-Source Forward Leakage V GS = 5 V.5 7 I GSS Gate-Source Reverse Leakage V GS = -5 V..5 ma V GS(TH) Gate Threshold Voltage V DS = V GS, I D = 9 ma.7.4.5 V R DS(ON) Drain-Source On Resistance V GS = 5 V,. 4 mω Source-Drain Characteristics (T J = 5 C unless otherwise stated) V SD I S =.5 A, V GS = V, T = 5 C Source-Drain Forward Voltage I S =.5 A, V GS = V, T = 5 C All measurements were done with substrate shorted to source..75.8 V Thermal Characteristics TYP R θjc Thermal Resistance, Junction to Case.6 C/W R θjb Thermal Resistance, Junction to Board 5 C/W R θja Thermal Resistance, Junction to Ambient (Note ) 54 C/W Note : R θja is determined with the device mounted on one square inch of copper pad, single layer oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/appnote_thermal_performance_of_egan_fets.pdf for details. EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT PAGE
EPC5 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dynamic Characteristics (T J = 5 C unless otherwise stated) C ISS C OSS C RSS Q G Total Gate Charge (V GS = 5 V).5.6 Q GD Q GS Q OSS Q RR Input Capacitance Output Capacitance V DS = V, V GS = V 575 75 Reverse Transfer Capacitance 6 7 Gate to Drain Charge..7 Gate to Source Charge V DS = V,.5 Output Charge 8.5 Source-Drain Recovery Charge All measurements were done with substrate shorted to source. pf nc ID Drain Current (A) 5 5 Figure : Typical Output Characteristics V GS = 5 V GS = 4 V = GS V GS = ID Drain Current (A) 5 5 Figure : Transfer Characteristics 5 C 5 C V DS = V.5.5 V DS Drain to Source Voltage (V).5.5.5.5 4 4.5 RDS(ON) Drain to Source Resistance (mω) 8 6 4 Figure : R DS(on) vs V GS for Various Current I D = A I D = A I D = 5 A I D = A RDS(ON) Drain to Source Resistance (mω) 5 5 Figure 4: R DS(on) vs V GS for Various Temperature 5 C 5 C.5.5.5 4 4.5 5 5.5 V GS Gate to Source Voltage (V).5.5 4 4.5 5 5.5 EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT PAGE
EPC5 C Capacitance (nf).6.4..8.6.4. Figure 5: Capacitance C OSS = C GD + C SD C ISS = C GD + C GS C RSS = C GD VG Gate to Source Voltage (V) 5 4.5 4.5.5.5.5 Figure 6: Gate Charge V D = V V DS Drain to Source Voltage (V) 4 6 8 Q G Gate Charge (nc) ISD Source to Drain Current (A) 5 5 Figure 7: Reverse Drain-Source Characteristics 5 C 5 C Normalized On-State Resistance RDS(ON).5.5.5 Figure 8: Normalized On Resistance Vs Temperature V GS = 5 V.5.5.5.5 4 4.5 V SD Source to Drain Voltage (V) - 4 6 8 4 T J Junction Temperature ( C ) Normalized Threshold Voltage.5..5.95 Figure 9: Normalized Threshold Voltage vs. Temperature I D = 9 ma IG Gate Current (A).5..5..5 Figure : Gate Current 5 C 5 C.9-4 6 8 4 T J Junction Temperature ( C ) 4 5 6 EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT PAGE
EPC5 Figure : Transient Thermal Response Curve ZθJB, Normalized Thermal Impedance, C/Watt Duty Factors:.5....5... Normalized Maximum Transient Thermal Impedance P DM t.. Single Pulse Notes: Duty Factor: D = t /t Peak T J = P DM x Z θjb x R θjb + T B -5-4 - - - t t p, Rectangular Pulse Duration, seconds TAPE AND REEL CONFIGURATION 4mm pitch, mm wide tape on 7 reel b d e f g Loaded Tape Feed Direction 7 reel a c Die orientation dot Gate solder bar is under this corner EPC5 (note ) Dimension (mm) target min max a..7. b.75.65.85 c (note ) 5.5 5.45 5.55 d 4..9 4. e 4..9 4. f (note )..95.5 g.5.5.6 Die is placed into pocket solder bar side down (face side down) Note : MSL (moisture sensitivity level ) classified according to IPC/JEDEC industry standard. Note : Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 5 Die orientation dot Gate Pad solder bar is under this corner YYYY ZZZZ Part Number Part # Marking Line Laser Markings Lot_Date Code Marking line Lot_Date Code Marking Line EPC5 5 YYYY ZZZZ EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT PAGE 4
EPC5 DIE OUTLINE Solder Bar View c d X f A f X9 4 5 6 7 8 9 B DIM MICROMETERS MIN Nominal MAX A 475 45 45 B 6 6 66 c 79 8 85 d 577 58 58 e 5 5 65 f 95 5 g 4 4 4 e g (685) 85 Max g X8 Side View +/- SEATING PLANE RECOMMENDED LAND PATTERN (units in µm) Pad no. is Gate; Pads no., 5, 7, 9, are Drain; Pads no. 4, 6, 8, are Source; Pad no. is Substrate. Information subject to change without notice. Revised March, EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT PAGE 5