ELT-44007/RxArch2/1 Receiver Architectures - Part 2 Increasing the role of DSP in receiver front-ends Markku Renfors Laboratory of Electronics and Communications Engineering Tampere University of Technology, Finland markku.renfors@tut.fi Topics: - Classification of DSP-based receiver architectures - Characteristics of alternative flexible wideband receiver architectures - DSP for flexible receivers - Digital channel selection & down-conversion techniques
ELT-44007/RxArch2/2 Classification of DSP-Based Receiver Architectures Location of ADC (A/D-converter) 1. Baseband or low IF 2. IF 3. RF Analog front-end bandwidth - ADC bandwidth 1. Single channel 2. Few channels 3. Frequency slice 4. Service band (e.g., GSM) 5. Multi-system frequency band (like 2 GHz range) The bandwidths of the analog front-end and ADC may or may not go hand in hand. Some examples below.
ELT-44007/RxArch2/3 Narrowband front-end Per-channel down-conversion (0, or IF) - Selectivity in analog part, good IF filters needed. - Per-channel frequency sythesizer needed. - No big demands for ADC dynamic range or jitter. - Sampling rate requirements are such that it is enough to attenuate aliasing to the desired band. - Narrowband (baseband or bandpass) ADC (like SD) can be utilized. RF-stages Mixer IF-stages BP/LP filter ADC LO f IF
ELT-44007/RxArch2/4 Wideband front-end, per-channel downconversion so that desired channel is around a fixed center frequency (0 or IF) - Analog front-end simplified in the sense that highly selective IF filters are not needed. - per-channel frequency synthesizer needed. - Selectivity in digital part, with fixed center frequency. - High demands for ADC dynamic range and jitter. - Sampling rate requirements are such that it is enough to attenuate aliasing to the desired band. - Narrowband ADC (like SD) can be utilized. RF-stages Mixer IF-stages BP/LP filter ADC LO f IF B IF
ELT-44007/RxArch2/5 Wideband front-end, wideband (like slice or service band) down-conversion so that desired channel is located in a wider frequency range - Analog front-end simplified in the sense that highly selective IF filters are not needed. - Single or few LO frequencies needed for each service band -> simplified synthesizer; fast frequency hopping becomes easier. - Selectivity in digital part, with tunable center frequency. - High demands for ADC dynamic range and jitter. - Sampling rate requirements are such that no aliasing into the whole band is allowed. - Wideband ADC (or SD with tunable center frequency!) needed. RF-stages Mixer IF-stages BP filter ADC LO B IF
ELT-44007/RxArch2/6 About the Choice Between Lowpass and Bandpass Sampling Due to the I/Q gain and phase imbalance problems in practical analog circuitry, the wideband downconversion - wideband sampling approach is very difficult to implement at 0 (or low) IF. But utilizing a combination of different techniques for mitigating these effects, the mentioned approach is becoming feasible, but mostly on the basestation side. On the other hand, wideband IF sampling is very challenging due to the apperture jitter and other implementation problems concerning the sampling circuitry (usually track&hold). The ADC requirements (apart from the sampling process) concern mainly the spurious-free dynamic range, and are not so heavily depending on the choice between lowpass or IF sampling. However, the useful ADC bandwidth has a great impact, e.g., on power consumption. So the cost/complexity metrics for per-channel A/D-conversion (usually SD) and multichannel A/D-conversion (usually something else than SD) are quite different.
ELT-44007/RxArch2/7 Some Dependencies and Conclusions Considering sampling and A/D-conversion highest signal frequency determines the T/H bandwidth and jitter requirements signal bandwidth (after analog RF/IF/baseband filtering) determines the minimum sampling rate Increasing the degree of bandpass subsampling ( f / f ) leads to c s lower sampling rate more selectivity needed before sampling more noise aliasing => more gain needed before sampling lower processing gain -> more bits from ADC & tighter jitter requirements Implementing the receiver selectivity in DSP-part leads to simplified analog part hard requirements for the T/H and ADC dynamic range Wideband sampling has been mostly considered at IF due to I/Qimbalance problems; direct conversion/low-if becoming feasible, depending on system specs Using IF sampling sets hard requirements for the T/H circuitry and jitter of the sampling clock.
ELT-44007/RxArch2/8 Connection to Advanced Broadband Wireless System Developments The latest and future wireless communication systems use increasing bandwidths for data transmission. For example, LTE has the maximum bandwidth of 20 MHz, and up to 100 MHz in LTE-A with carrier aggregation. 5G is targeting to significantly higher bandwidths. Especially, LTE is using frequency-division duplexing, and the spectrum entering the receiver resembles that of a multichannel receiver for more narrowband systems. Some characteristics and comments: - The wide bandwidth makes it possible to utilize fast frequency hopping and other forms of frequency diversity, to enhance the transmitted data rate. - In LTE (and other similar systems) the power levels of the frequency slots of different users are well-controlled (e.g., 20 db maximum variation in the power levels). This is in contrast to, e.g., multichannel GSM receiver, were the dynamic range is much bigger. This makes it feasible to implement the needed wideband receivers for such systems. - Direct conversion architecture is preferred. Actually, for most of the frequency channels, the low-if model is valid. - IQ-imbalance is significant, but not very critical because of the well-controlled power levels. DSP-based IQimbalance compensation is interesting in case of highorder modulations. - In these systems, and in OFDM systems in general, the frequencies at or close to DC in baseband processing are commonly not utilized in order to make direct conversion receiver design easier.
ELT-44007/RxArch2/9 About Direct Sampling Architecture In high-performance systems, it is necessary to have some selectivity and gain before sampling. The reasons are signal aliasing noise aliasing Sampling is commonly considered to be more noisy operation than mixing! Sampling directly from the antenna signal is usually not adequate. The Ultimate SW Radio Architecture Antenna a bank of RF filters and LNA s for different frequency bands T/H A/D DSP The needed technologies are not mature for challenging radio system specifications in the frequency bands used in mobile systems! However, direct sampling is already an interesting architecture in various applications o For example, satellite-based positioning (GPS/Galileo) where the dynamic range requirements are greatly reduced comparing with wireless communications.
ELT-44007/RxArch2/10 Direct Sampling & Analog Discrete-Time Processing Texas Instruments (TI) has introduced so-called digital radio processor (DRP) concept that is based on direct sampling, together with analog discrete-time processing to implement main part of the channel selectivity, downconversion, and sampling rate reduction. o For example, CIC/running-sum filters can be implemented with switched-capacitor techniques with analog processing. o Then the ADC is operating at relatively low rate and has reduced dynamic range requirements compared to digital direct-sampling approach. TI is marketing DRP-based transceiver chips for GPS, Bluetooth, and GSM/GPRS, i.e., for systems with relatively narrow bandwidth or reduced dynamic range, together with low-order modulation. In such architectures, also the sampling process may be designed to provide frequency selectivity. Then the idea of the sampling process is not anymore just taking instantaneous sample values, but to - Integrate the signal over a finite-length interval - Weighting the input signal by a proper window during the integration interval. Rectangular window results in sinc-response, other kind of windows can be designed for optimized performance.
ELT-44007/RxArch2/11 Multimode Receivers In flexible multi-mode receivers, the target is to use common blocks for different systems as much as possible. A long-term target is to make the transceiver configurable for any system. However, presently a combination of a few predetermined systems is more realistic. A realistic approach has the following elements: - Separate RF stages for different systems. - Common IF/baseband analog parts; bandwidth according to the most wideband system. - Common ADC at IF or baseband; fixed sampling rate. - Especially in the terminal side: careful choice of IF frequency & sampling rate to make the downconversion simple. Typically, f IF = (2k+1) f S /4. - Digital channel selection filtering optimized for the different systems. LNA IF 1 filter AGC S&H I DSP IF 2 ADC Q 0,1,0,-1 DSP LO 1,0,-1,0
ELT-44007/RxArch2/12 Rephrasing Critical Issues in Modern Receiver Architectures: SWOT Analysis on Flexible Receiver Architectures with Wideband Analog Front-End Alternatives: 1. Multimode direct-conversion receiver 2. Multimode low IF receiver 3. Multimode IF-sampling receiver 4. Wideband IF sampling architecture 5. Wideband direct-conversion/low-if architecture 6. Direct-sampling architecture Common features for 1-3: Analog & A/D bandwidth according to the widest channel bandwidth Common features for 4 and 5: Tunable digital channel selection and down-conversion Interesting mostly for base-station applications
ELT-44007/RxArch2/13 1. Multimode direct-conversion receiver Strengths - Simple analog part - Sampling jitter not critical - Narrowband A/D-conversion can be used Weaknesses - DC-offset problems, especially difficult to handle in flexible receiver - 2nd-order intermodulation -> bigger demands for the linearity of the analog parts Oportunities - Fast and flexible DC-offset compensation techniques, facilitated by high resolution A/D-conversion techniques.
ELT-44007/RxArch2/14 2. Multimode low IF receiver Strengths - Rather simple analog part - Sampling jitter not critical - Narrowband A/D-conversion can be used - DC-problems avoided Weaknesses - 2nd-order intermodulation -> bigger demands for the linearity of the analog parts - Higher demands for I/Q balance - Multimode concept not very clear (different low-if's for different systems, or very hard demands for I/Q balance) Oportunities - Adaptive I/Q imbalance compensation can be used to loosen the requirements of the analog part.
ELT-44007/RxArch2/15 3. Multimode IF-sampling receiver Strengths - Well-known architecture, high-quality analog RF possible - 2nd-order intermodulation not a problem - Narrowband A/D-conversion can be used - DC-problems avoided Weaknesses - Challenging demands for sampling jitter and linearity - IF filter difficult to integrate Oportunities - New technologies for flexible IF/RF filter implementation (e.g., MEMS)
ELT-44007/RxArch2/16 4. Wideband IF sampling architecture Strengths - Reduced IF filtering requirements - Simplified frequency synthesizer - Possibility to use common blocks for multiple channels - Facilitates fast frequency hopping/channel switching - DC-problems avoided Weaknesses - Very challenging demands for sampling jitter and linearity - Wideband A/D-conversion needed - 2nd-order intermodulation may be a problem - Lot of DSP power needed - High power consumption Oportunities - Advances in ADC technologies and DSP HW
ELT-44007/RxArch2/17 5. Wideband direct-conversion/low-if architecture Strengths - Simplified frequency synthesizer - Possibility to use common blocks for multiple channels - Facilitates fast frequency hopping/channel switching - Rather simple analog part - Sampling jitter not critical Weaknesses - Hard demands for I/Q balance - Multimode concept not very clear (avoiding DC-offset problems in all different systems) - Wideband A/D-conversion needed - 2nd-order intermodulation -> bigger demands for the linearity of the analog parts - High power consumption Oportunities - Adaptive I/Q imbalance compensation can be used to loosen the requirements of the analog part.
ELT-44007/RxArch2/18 6. Direct-sampling receiver Strengths - Simplest possible analog part - Highly flexible for multi-standard receivers. Weaknesses - Very hard jitter requirements. - Currently not feasible for demanding system specs or high-order modulation. Oportunities - Novel ideas for sampling and ADCs - Analog discrete-time processing techniques.
ELT-44007/RxArch2/19 Case Study on Wideband IF Sampling in GSM Receivers* Introduction Specifications and selectivity requirements for GSM Sampling and quantization requirements as Functions of analog filter bandwidth Requirements for digital filtering * This part is based on the diploma thesis work of Juho Pirskanen carried out at TUT/ICE during years 1999-2000.
ELT-44007/RxArch2/20 Multi-Standard Receivers When several systems with different bandwidths are desired to be used, we have two basic choices: Several different analog front-ends in the receiver o This is still the typical choice in mobile devices OR Wideband analog front-end and wideband ADconversion Notice that we have basically the same choices also in multi-channel base-station receivers.
ELT-44007/RxArch2/21 Wideband GSM Receiver Receiver with wideband front-end and wideband ADconversion o Analog front-end can be simplified o One AD-converter can be used for different systems Performance requirements of the ADC are harder Channelization filtering must be done in digital domain to obtain desired system characteristics.
ELT-44007/RxArch2/22 GSM Case: Interference Mask Obtained from the GSM specifications Includes interference signals from adjacent channel out of band blocking intermodulation test
ELT-44007/RxArch2/23 GSM Case: Attenuation Requirements Attenuation requirements for GSM can be expressed as ( ) A ( f ) = P ( f ) - P - SIR - A S I sign m P I power of the interference signal P sign power of the desired signal SIR required signal to interference ratio A m extra noise margin
ELT-44007/RxArch2/24 GSM Case: ADC Dynamic Range ADC dynamic range requirement can be calculated as dynamic { S ( ) ( )} SNR = max A f + H f A S ( f ) is the attenuation requirement in db H( f ) the amplitude response of the analog filter in db Fourth-order Chebyshev type two filters: f The red squares mark the critical points where the dynamic range requirement is maximized for each filter bandwidth.
ELT-44007/RxArch2/25 GSM Case: ADC Dynamic Requirements By combining the above equations and the ADC analysis from p. 33 of Sampling and Multirate Techniques for Complex and Bandpass Signals lecture, and noting that GSM uses constant enevelope modulation, the minimum number of bits can be evaluated by é f SNRdynamic 1.76 10log æ s öù ê - - 10 ç 2B ú b = è ø ê ú ê 6.02 ú ê ú This is a worst-case model, assuming that the interference comes from a blocking tone signal at the frequency where SNR is maximized. dynamic Below the minimum number of bits is shown as a function of sampling rate and analog bandwidth for two common filter types. Used sampling rates Multiples of GSM symbol rate 17.33 MHz, 34.66 MHz and 69.33 MHz Studied filter types Butterworth and Chebyshev type II filters Used filter orders Fourth and sixth order filters Filter bandwidth From 100 khz to 2.5 MHz
ELT-44007/RxArch2/26 GSM Case: Number of Bits Required in ADC Fourth-order Butterworth filters: Sixth-order Chebyshev type II filters: Notice that in practice the minimum number of bits is higher than the lowest values indicated here, in order to be able to carry out the channel equalization properly.
ELT-44007/RxArch2/27 GSM Case: Jitter Noise The maximum signal power to be sampled is: ADC max I f { ( ) ( ) 2 } P = P f H f Using the standard white-noise model for the jitter effects, the maximum allowed standard deviation of the timing error (RMS sampling jitter) is given by: T = F S A 2 2 4p fmax ( Psig SIR Am ) - - 2B P ADC
ELT-44007/RxArch2/28 GSM Case: Jitter Requirements for f IF =156 MHz The timing jitter requirements when using fourth-order Butterworth filters: The timing jitter requirements when using sixth-order Chebyshev type II filters:
ELT-44007/RxArch2/29 GSM Case: Digital Filtering Requirements Channelization and noise filtering requirements for DSP in the GSM case. Sixth order Chebyshev type II analog filter Second order Sigma-delta modulator with 2 quantization bits The total decimation factor can be divided into several stages, e.g., 256 = 64 * 2*2 First stage can be implemented by using CIC-filters Simple structure, no multipliers Good attenuation for aliasing signal bands
ELT-44007/RxArch2/30 Wideband GSM Receiver: Conclusions Dynamic requirement of the ADC Highly effected by the analog filter bandwidth Analog filter order and type has only one bit effect on ADC requirement (together 2 bits in some cases) Standard deviation of timing jitter Highly effected by the analog filter bandwidth and used IF frequency (IF sampling) Analog filter order and type has only slight effect When considering GSM/WCDMA receivers The analog bandwidth should be about 2 MHz It is convenient to use common sampling rate for both systems Fractional sampling rate conversion has to be done because the WCDMA chip rate is not an integer multiple of the GSM symbol rate.
ELT-44007/RxArch2/31 DSP for Flexible Receivers In advanced SW radio concepts, the selectivity filtering and down-conversion are moved from analog continuoustime part to the discrete-time/dsp part. => Here efficient multirate filtering techniques become very important, also by non-integer factors. It also helps to move as much as possible functionality from the analog or digital front-end to baseband processing. => All-digital synchronization concept becomes very interesting in this context. Some errors due to RF-front-end can be corrected by DSP. Example: Adaptive I/Q imbalance compensation. => DSP-enhanced radio (a.k.a. dirty RF)
ELT-44007/RxArch2/32 All-Digital Synchronisation Concept Free-running local oscillators for demodulation and frequency conversion. Free-running sampling clock. Errors are compensated in digital part. => All synchronisation functions can be implemented using digital techniques
ELT-44007/RxArch2/33 Digital Channel Selection & Down-Conversion
ELT-44007/RxArch2/34 Digital Channel Selection & Down-Conversion Digital Down-Conversion 1. Desired channel centered at fixed IF => Fixed down-conversion Special choices of f IF and f S make things easy. Especially when f IF = (2k+1) f S /4, the signal aliases to f S /4 and down-conversion is very easy. 2. Wideband sampling case => Tunable down-conversion and NCO (numerically controlled oscillator) needed. 3. Stepwise mixing and decimation => Tunable digital down-conversion is possible also without I/Q mixing, or by doing fine-tuning mixing at low rate after decimation. However, it is not easy to find sufficiently efficient and flexible schemes. Channel Selection Filtering - After down-conversion, efficient lowpass decimator structure is needed. - CIC-filters are commonly used in the first decimation stages, FIR-filters and the last stages. Half-band FIR filters also an efficient and fairly common solution. (See Multirate Filtering lecture notes.) Adjusting Symbol Rates - Different systems use different symbol/chip rates. - Common sampling clock frequency is preferred. => Decimaton by a fractional factor is needed. - This can be done at baseband or earlier in the decimation chain. (See lecture notes on Polynomial-based interpolation)
ELT-44007/RxArch2/35 CIC-Filters z -1 z -1 32 z -1 z -1 CIC = Cascaded Integrator - Comb Transfer function and frequency response: ( 2 p / ) S H e H ( z) R N æ - z ö ç1- = ç -1 z è 1- ø ( p S ) ( p ) jp N ( R 1) f / f j f f S sin R f / f - æ ö = e ç Rsin f / f è S ø N Here R is the decimation factor and N is the order of the CIC-filter. A first-order CIC-filter takes the avarage of R consequtive input samples and decimates by R. It is also called moving average or running sum filter. It is important to use modulo arithmetic (like 2's complement) in the implementation, because there will be inevitable internal overflows.
ELT-44007/RxArch2/36 CIC-Filters In CIC filter, those frequencies aliasing to 0-frequency are heavily attenuated. For a relatively narrowband signal, low-order CIC-filters are sufficient; more wideband signals neede higher CIC-filter orders Example (for a GSM application): N=2, R=32.
ELT-44007/RxArch2/37 NCO-Based Arbitrary Digital Down- Conversion Dedicated processors implementing the following kind of down-conversion and channel selection structure are available from several vendors (like Harris). Sampling rates in the 50... 100 MHz range are possible. However, the power consumption is still too high for terminal applications.
ELT-44007/RxArch2/38 Example Using Harris HSP50214 for GSM channel selection filtering. - Input sample rate: 39 MHz - CIC-filter: decimation by 18, order=5 - Two pre-designed FIR half-band filters are used for the next decimation stages. - The final filter stage is an FIR design. - Output sample rate: 541.667 khz Frequency responses of the filter stages:
ELT-44007/RxArch2/39 Example (continued) Overall frequency response and the effects of different stages: