GRETINA. Electronics. Auxiliary Detector Workshop. Sergio Zimmermann LBNL. Auxiliary Detectors Workshop. January 28, 2006
|
|
- Clinton Glenn
- 5 years ago
- Views:
Transcription
1 GRETINA Auxiliary Detector Workshop Electronics Sergio Zimmermann LBNL 1
2 Outline Electronic Interface Options Digitizers Trigger/Timing System Grounding and Shielding Summary 2
3 Interface Options Three options Ethernet readout: connects directly to the switch Use standard Gretina digitizers: the auxiliary detectors connect directly to GRETINA digitizers Digital data stream: example: FERA interface (Mario s talk) Presently, the only interface that is funded and is part of the requirement document is the Ethernet Readout 3
4 System Local Trigger and Timing Module Digitizer Crystal Modules Pre amplifier Global Trigger and Timing Module Readout Computer 30 Crystals 2.2 MB/s 66 MB/s Processing Farm Network Switch 75 dual Processors 6.9 MB/s Aux. Det. Trigger Workstations, Servers Aux. Det. Data Data Storage 2.3 MB/s + Aux. Data 4
5 Ethernet Readout Is part of the requirement document and it will be part of GRETINA Requirement 2.1.1: Readout Data from the auxiliary detectors shall be combined with the GRETINA data (Ethernet switch) Requirement 2.1.2: Trigger The GRETINA trigger system shall provide 8 digital inputs with any logical combination [look up table]. 8 digital outputs that inform when a Level 2 trigger occurred [etc.] 5
6 Ethernet Readout Requirement 2.1.3: Time Stamp The auxiliary detectors shall provide their own time stamp with the same resolution as the GRETINA time stamp. Requirement 2.1.4: Clock Synchronization and Verification GRETINA shall provide clock and reset signals to synchronize the auxiliary detectors with GRETINA. Verification methods shall be implemented to verify that the auxiliary detector is properly synchronized with GRETINA. 6
7 Ethernet Readout Example: The auxiliary detectors have a circular buffer where data is stored. The buffer depth (size of the memory) allows for the GRETINA and Auxiliary Detector latency. GRETINA (or the auxiliary detector) provides a trigger. The data is removed from the circular buffer and moved to the readout buffer. If no trigger, the data is overwritten on the circular buffer. After some reasonable amount of data is stored in the readout buffer, it is transmitted to the GRETINA DAQ (through Ethernet). 7
8 Standard GRETINA Digitizers The auxiliary detectors are connected to the GRETINA digitizers Most likely, the same timing (with time stamp), trigger and readout applies. The data is readout by the same type of CPU readout controller and sent to the switch Information we will need: Number of channels Voltage range Rise time Pulse shape Condition for trigger, etc. Also, more in Mario s talk 8
9 System Local Trigger and Timing Module Digitizer Crystal Modules Pre amplifier Global Trigger and Timing Module Readout Computer 30 Crystals 2.2 MB/s 66 MB/s Processing Farm Network Switch 75 dual Processors 6.9 MB/s Aux. Det. Trigger Workstations, Servers Aux. Det. Data Data Storage 2.3 MB/s + Aux. Data 9
10 Digitizers 10
11 Digitizers Preamp/adc 100 MHz FPGA FIFO VME Preamp/adc 10 Inputs Preamp/adc Serial Interface Trigger/Timing Digital Inputs/Outputs Control and monitor registers External synch 100 MHz clock Clock distribution & local oscillator When the digitizer received a trigger, it transfer the data from a circular buffer (inside the FPGA) to the FIFO. If not, the data is overwritten. When the FIFO has data (say, half full), the Crate Controller readouts out the data. 11
12 Digitizers Data processing in FPGA Leading Edge Discrimination: yn = xn xn k (differentiation) yn = (xn + xn 2) + xn 1<<1 ( 4, Gaussian filtering) Threshold comparison LED time Constant Fraction Discrimination: yn = xn xn k (differentiation) yn = (xn + xn 2) + xn 1<<1 ( 2, Gaussian filtering) yn = xn k fxn (constant fraction, f is an attenuation factor) Zero crossing comparison CFD time Trapezoidal filter and energy determination (V.T Jordanov, G.F. Knoll, NIM A345 (1994) ) yn = yn 1 + ( (xn + xn 2m k) ) (xn m + xn m k) ) Maximum tracking energy Pole Zero correction yn = xn + In /t (where t is the pre amplifier time constant) In = In 1 + xn 12
13 Digitizers Flow of data in the DSP board From ADC Delay 1 k Leading Edge Disc. Delay 2 m Delay 3 k LED Time Const. Fraction Disc. Energy P/Z Delay 4 m CFD Time CFD Amplitudes Energy 13
14 Digitizers Detector Digitizer Connection Cable Connector 5 T wis t e d p air ( 2 6 A W G) wit h f o il s h ie ld ing Dr ain wir e f o r c ab le s h ie ld ing Fo il and b r aid s h ie ld ing J ac k e t 5. Dr a in wir e f o r ind ivid ua l t wis t e d pa ir s Centi Line 2D from ITT/Cannon Proper pin assignment reduces the crosstalk 14
15 Trigger/Timing System Transmit data and timing information from Trigger/Timing units to/from Digitizers GLOBAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER LOCAL TRIGGER used to recover clock and data sent from Global Trigger Unit Single Pair: Clock and Data XTAL OSC FULL DUPLEX Differential Twisted Pair 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X 4 pairs DIGITIZER 4X FULL DUPLEX Differential Twisted Pair 15
16 Trigger/Timing System The following trigger algorithms are planned at this point (and are part of the requirements) Multiplicity: A programmable number of energy over threshold occurs inside some walking time window. Energy: Segment and/or central contact energy at lower resolution (which appears earlier in the digitizer ). It can use the energy of a segment or central contact or the sum of energies of segments and central contacts. When this energy falls within some pre set window (within some low and high energy limit) a Level 2 trigger is generated. 16
17 Trigger/Timing System Pattern distribution: GRETINA shall trigger if the Trigger System detects coincidence of gamma rays energy at lower resolution above threshold in any two pre programmed central contact of the crystals. Auxiliary detector trigger: GRETINA will receive an external trigger within the pipeline depth [presently at 20 µs, goal 100 µs]. 17
18 Trigger/Timing System Serial Data 100Mb/s FPGA Serializers Delay Line Phase Detector DCM BLOCK CLK0 DATA CLOCK CLK90 CLK180 CLK270 FREQ/PHASE CORRECTION Specifications Freq: 100MHz Pull: +/ 70ppm Jitter: 5ps RMS 100MHz LOOP FILTER UP DOWN 18
19 Grounding and Shielding Detector modules Isolated from support and from other modules Reduce capacitance to support structure One common safety ground for each module, no other connection to ground. Detector enclosure (iridite) provides Faraday cage Detector power supplies and bias Each crystal has its own set of floating supplies Power: twisted pair, shielded cable Bias: high voltage coaxial All electronics for one detector module is assembled close together Signals: optical or twisted shielded pairs Clean AC power 19
20 Grounding and Shielding Need to coordinate the grounding and shielding of the auxiliary detectors with GRETINA s grounding and shielding. We have documented GRETINA s grounding and shielding. 20
Nyquist filter FIFO. Amplifier. Impedance matching. 40 MHz sampling ADC. DACs for gain and offset FPGA. clock distribution (not yet implemented)
The Digital Gamma Finder (DGF) Firewire clock distribution (not yet implemented) DSP One of four channels Inputs Camac for 4 channels 2 cm System FPGA Digital part Analog part FIFO Amplifier Nyquist filter
More informationData Acquisition System for the Angra Project
Angra Neutrino Project AngraNote 012-2009 (Draft) Data Acquisition System for the Angra Project H. P. Lima Jr, A. F. Barbosa, R. G. Gama Centro Brasileiro de Pesquisas Físicas - CBPF L. F. G. Gonzalez
More informationMotivation Overview Grounding & Shielding L1 Trigger System Diagrams Front-End Electronics Modules
F.J. Barbosa, Jlab 1. 2. 3. 4. 5. 6. 7. 8. 9. Motivation Overview Grounding & Shielding L1 Trigger System Diagrams Front-End Electronics Modules Safety Summary 1 1. Motivation Hall D will begin operations
More informationMASE: Multiplexed Analog Shaped Electronics
MASE: Multiplexed Analog Shaped Electronics C. Metelko, A. Alexander, J. Poehlman, S. Hudan, R.T. desouza Outline 1. Needs 2. Problems with existing Technology 3. Design Specifications 4. Overview of the
More informationClock and control fast signal specification M.Postranecky, M.Warren and D.Wilson 02.Mar.2010
Clock and control fast signal specification M.Postranecky, M.Warren and D.Wilson 02.Mar.2010 1 Introduction...1 2 Fast signal connectors and cables...1 3 Timing interfaces...2 XFEL Timing Interfaces...2
More informationReal-Time Digital Signal Processors with radiation detectors produced by TechnoAP
Real-Time Digital Signal Processors with radiation detectors produced by TechnoAP Lunch time Exhibitor presentation 2976-15 Mawatari, Hitachinaka-city, Ibaraki 312-0012, Japan Phone: +81-29-350-8011, FAX:
More informationnanomca datasheet I. FEATURES
datasheet nanomca I. FEATURES Finger-sized, high performance digital MCA. 16k channels utilizing smart spectrum-size technology -- all spectra are recorded and stored as 16k spectra with instant, distortion-free
More informationnanomca 80 MHz HIGH PERFORMANCE, LOW POWER DIGITAL MCA Model Numbers: NM0530 and NM0530Z
datasheet nanomca 80 MHz HIGH PERFORMANCE, LOW POWER DIGITAL MCA Model Numbers: NM0530 and NM0530Z I. FEATURES Finger-sized, high performance digital MCA. 16k channels utilizing smart spectrum-size technology
More informationDAQ & Electronics for the CW Beam at Jefferson Lab
DAQ & Electronics for the CW Beam at Jefferson Lab Benjamin Raydo EIC Detector Workshop @ Jefferson Lab June 4-5, 2010 High Event and Data Rates Goals for EIC Trigger Trigger must be able to handle high
More informationOverview of talk AGATA at LNL Electronics needed for gamma ray tracking System overview Digitisers Pre-processing GTS Results Software Connecting othe
AGATA Electronics Overview of talk AGATA at LNL Electronics needed for gamma ray tracking System overview Digitisers Pre-processing GTS Results Software Connecting other experiments to AGATA International
More informationHighly Segmented Detector Arrays for. Studying Resonant Decay of Unstable Nuclei. Outline
Highly Segmented Detector Arrays for Studying Resonant Decay of Unstable Nuclei MASE: Multiplexed Analog Shaper Electronics C. Metelko, S. Hudan, R.T. desouza Outline 1. Resonant Decay 2. Detectors 3.
More informationGFT Channel Digital Delay Generator
Features 20 independent delay Channels 100 ps resolution 25 ps rms jitter 10 second range Output pulse up to 6 V/50 Ω Independent trigger for every channel Four triggers Three are repetitive from three
More informationGFT1504 4/8/10 channel Delay Generator
Features 4 independent Delay Channels (10 in option) 100 ps resolution (1ps in option) 25 ps RMS jitter (channel to channel) 10 second range Channel Output pulse 6 V/50 Ω, 3 ns rise time Independent control
More informationTraditional analog QDC chain and Digital Pulse Processing [1]
Giuliano Mini Viareggio April 22, 2010 Introduction The aim of this paper is to compare the energy resolution of two gamma ray spectroscopy setups based on two different acquisition chains; the first chain
More informationNIM INDEX. Attenuators. ADCs (Peak Sensing) Discriminators. Translators Analog Pulse Processors Amplifiers (Fast) Amplifiers (Spectroscopy)
NIM The NIM-Nuclear Instrumentation Module standard is a very popular form factor widely used in experimental Particle and Nuclear Physics setups. Defined the first time by the U.S. Atomic Energy Commission
More informationGFT1012 2/4 Channel Precise Slave Generator
Features Two Independent Delay Channels (Four channels available as an option) 1 ps Time Resolution < 5 ps RMS Jitter (Slave-to-Slave) < 6 ps / C Drift (Slave-to-slave) 1 Second Range Output Pulse Up to
More informationM.Pernicka Vienna. I would like to raise several issues:
M.Pernicka Vienna I would like to raise several issues: Why we want use more than one pulse height sample of the shaped signal. The APV25 offers this possibility. What is the production status of the FADC+proc.
More informationNoise Performance Evaluation of the Candidate Digitizers for the MAJORANA DEMONSTRATOR
PNNL-20268 Noise Performance Evaluation of the Candidate Digitizers for the MAJORANA DEMONSTRATOR E. Aguayo March 2011 DISCLAIMER This report was prepared as an account of work sponsored by an agency of
More informationRPG XFFTS. extended bandwidth Fast Fourier Transform Spectrometer. Technical Specification
RPG XFFTS extended bandwidth Fast Fourier Transform Spectrometer Technical Specification 19 XFFTS crate equiped with eight XFFTS boards and one XFFTS controller Fast Fourier Transform Spectrometer The
More informationnanodpp datasheet I. FEATURES
datasheet nanodpp I. FEATURES Ultra small size high-performance Digital Pulse Processor (DPP). 16k channels utilizing smart spectrum-size technology -- all spectra are recorded and stored as 16k spectra
More informationPACS codes: Qx, Nc, Kv, v Keywords: Digital data acquisition, segmented HPGe detectors, clock and trigger distribution
Clock and Trigger Synchronization between Several Chassis of Digital Data Acquisition Modules W. Hennig, H. Tan, M. Walby, P. Grudberg, A. Fallu-Labruyere, W.K. Warburton, XIA LLC, 31057 Genstar Road,
More informationAgilent CMM Fixture Electronics Clock/Crystal Measurement Module
Agilent CMM Fixture Electronics Clock/Crystal Measurement Module Slide # 1 Having problems with clock? Frequency too high, over 3070 spec > 20MHz for any hybrid receivers (rcva) > 60MHz for clock receivers
More informationnanomca-ii-sp datasheet
datasheet nanomca-ii-sp 125 MHz ULTRA-HIGH PERFORMANCE DIGITAL MCA WITH BUILT IN PREAMPLIFIER Model Numbers: SP8004 to SP8009 Standard Models: SP8006B and SP8006A I. FEATURES Finger-sized, ultra-high performance
More informationA Prototype Amplifier-Discriminator Chip for the GLAST Silicon-Strip Tracker
A Prototype Amplifier-Discriminator Chip for the GLAST Silicon-Strip Tracker Robert P. Johnson Pavel Poplevin Hartmut Sadrozinski Ned Spencer Santa Cruz Institute for Particle Physics The GLAST Project
More informationStudy of the ALICE Time of Flight Readout System - AFRO
Study of the ALICE Time of Flight Readout System - AFRO Abstract The ALICE Time of Flight Detector system comprises about 176.000 channels and covers an area of more than 100 m 2. The timing resolution
More informationnanomca-sp datasheet I. FEATURES
datasheet nanomca-sp 80 MHz HIGH PERFORMANCE, LOW POWER DIGITAL MCA WITH BUILT IN PREAMPLIFIER Model Numbers: SP0534A/B to SP0539A/B Standard Models: SP0536B and SP0536A I. FEATURES Built-in preamplifier
More informationCAMAC products. CAEN Short Form Catalog Function Model Description Page
products Function Model Description Page Controller C111C Ethernet Crate Controller 44 Discriminator C808 16 Channel Constant Fraction Discriminator 44 Discriminator C894 16 Channel Leading Edge Discriminator
More informationCoincidence Rates. QuarkNet. summer workshop June 24-28, 2013
Coincidence Rates QuarkNet summer workshop June 24-28, 2013 1 Example Pulse input Threshold level (-10 mv) Discriminator output Once you have a digital logic pulse, you can analyze it using digital electronics
More informationThis is by far the most ideal method, but poses some logistical problems:
NXU to Help Migrate to New Radio System Purpose This Application Note will describe a method at which NXU Network extension Units can aid in the migration from a legacy radio system to a new, or different
More informationHello, and welcome to this presentation of the STM32 Digital Filter for Sigma-Delta modulators interface. The features of this interface, which
Hello, and welcome to this presentation of the STM32 Digital Filter for Sigma-Delta modulators interface. The features of this interface, which behaves like ADC with external analog part and configurable
More informationNIM. ADCs (Peak Sensing) Analog Pulse Processors Amplifiers (Fast) Amplifiers (Spectroscopy) Attenuators Coincidence/Logic/Trigger Units
The NIM-Nuclear Instrumentation Module standard is a very popular form factor widely used in experimental Particle and Nuclear Physics setups. Defined the first time by the U.S. Atomic Energy Commission
More informationMB1503. LOW-POWER PLL FREQUENCY SYNTHESIZER WITH POWER SAVE FUNCTION (1.1GHz) Sept Edition 1.0a DATA SHEET. Features
Sept. 1995 Edition 1.0a MB1503 DATA SHEET LOW-POWER PLL FREQUENCY SYNTHESIZER WITH POWER SAVE FUNCTION (1.1GHz) The Fujitsu MB1503 is a serial input phase-locked loop (PLL) frequency synthesizer with a
More informationP. Branchini (INFN Roma 3) Involved Group: INFN-LNF G. Felici, INFN-NA A. Aloisio, INFN-Roma1 V. Bocci, INFN-Roma3
P. Branchini (INFN Roma 3) Involved Group: INFN-LNF G. Felici, INFN-NA A. Aloisio, INFN-Roma1 V. Bocci, INFN-Roma3 Let s remember the specs in SuperB Baseline: re-implement BaBar L1 trigger with some improvements
More informationVerification of a novel calorimeter concept for studies of charmonium states Guliyev, Elmaddin
University of Groningen Verification of a novel calorimeter concept for studies of charmonium states Guliyev, Elmaddin IMPORTANT NOTE: You are advised to consult the publisher's version (publisher's PDF)
More informationA Modular Readout System For A Small Liquid Argon TPC Carl Bromberg, Dan Edmunds Michigan State University
A Modular Readout System For A Small Liquid Argon TPC Carl Bromberg, Dan Edmunds Michigan State University Abstract A dual-fet preamplifier and a multi-channel waveform digitizer form the basis of a modular
More informationOverview 256 channel Silicon Photomultiplier large area using matrix readout system The SensL Matrix detector () is the largest area, highest channel
技股份有限公司 wwwrteo 公司 wwwrteo.com Page 1 Overview 256 channel Silicon Photomultiplier large area using matrix readout system The SensL Matrix detector () is the largest area, highest channel count, Silicon
More informationDATA SHEET. TDA8415 TV and VTR stereo/dual sound processor with integrated filters and I 2 C-bus control INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET TV and VTR stereo/dual sound processor with integrated filters and I 2 C-bus control File under Integrated Circuits, IC02 May 1989 with integrated filters and I 2 C-bus control
More information50 MHz Voltage-to-Frequency Converter
Journal of Physics: Conference Series OPEN ACCESS 50 MHz Voltage-to-Frequency Converter To cite this article: T Madden and J Baldwin 2014 J. Phys.: Conf. Ser. 493 012008 View the article online for updates
More informationElectronic Readout System for Belle II Imaging Time of Propagation Detector
Electronic Readout System for Belle II Imaging Time of Propagation Detector Dmitri Kotchetkov University of Hawaii at Manoa for Belle II itop Detector Group March 3, 2017 Barrel Particle Identification
More informationA Readout ASIC for CZT Detectors
A Readout ASIC for CZT Detectors L.L.Jones a, P.Seller a, I.Lazarus b, P.Coleman-Smith b a STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX, UK b STFC Daresbury Laboratory, Warrington WA4 4AD, UK
More informationHINP4 Progress Report
HINP4 Progress Report George Engel, D.Sc. Srikanth Thota (student) IC Design Research Laboratory Department of Electrical and Computer Engineering Southern Illinois University Edwardsville, IL, 62026-1801
More informationDigital Systems Design
Digital Systems Design Clock Networks and Phase Lock Loops on Altera Cyclone V Devices Dr. D. J. Jackson Lecture 9-1 Global Clock Network & Phase-Locked Loops Clock management is important within digital
More informationDevelopment of a 256-channel Time-of-flight Electronics System For Neutron Beam Profiling
JOURNAL OF L A TEX CLASS FILES, VOL. 14, NO. 8, AUGUST 2015 1 Development of a 256-channel Time-of-flight Electronics System For Neutron Beam Profiling Haolei Chen, Changqing Feng, Jiadong Hu, Laifu Luo,
More informationSPADIC 1.0. Tim Armbruster. FEE/DAQ Workshop Mannheim. January Visit
SPADIC 1.0 Tim Armbruster tim.armbruster@ziti.uni-heidelberg.de FEE/DAQ Workshop Mannheim Schaltungstechnik Schaltungstechnik und und January 2012 Visit http://www.spadic.uni-hd.de 1. SPADIC Architecture
More informationA 4 Channel Waveform Sampling ASIC in 130 nm CMOS
A 4 Channel Waveform Sampling ASIC in 130 nm CMOS E. Oberla, H. Grabas, J.F. Genat, H. Frisch Enrico Fermi Institute, University of Chicago K. Nishimura, G. Varner University of Hawai I Large Area Picosecond
More informationData acquisi*on and Trigger - Trigger -
Experimental Methods in Par3cle Physics (HS 2014) Data acquisi*on and Trigger - Trigger - Lea Caminada lea.caminada@physik.uzh.ch 1 Interlude: LHC opera3on Data rates at LHC Trigger overview Coincidence
More informationRP220 Trigger update & issues after the new baseline
RP220 Trigger update & issues after the new baseline By P. Le Dû pledu@cea.fr Cracow - P. Le Dû 1 New layout features Consequence of the meeting with RP420 in Paris last September Add 2 vertical detection
More informationHow different FPGA firmware options enable digitizer platforms to address and facilitate multiple applications
How different FPGA firmware options enable digitizer platforms to address and facilitate multiple applications 1 st of April 2019 Marc.Stackler@Teledyne.com March 19 1 Digitizer definition and application
More informationSilicon Photomultiplier Evaluation Kit. Quick Start Guide. Eval Kit SiPM. KETEK GmbH. Hofer Str Munich Germany.
KETEK GmbH Hofer Str. 3 81737 Munich Germany www.ketek.net info@ketek.net phone +49 89 673 467 70 fax +49 89 673 467 77 Silicon Photomultiplier Evaluation Kit Quick Start Guide Eval Kit Table of Contents
More informationCAEN. Electronic Instrumentation. CAEN Silicon Photomultiplier Kit
CAEN Tools for Discovery Electronic Instrumentation CAEN Silicon Photomultiplier Kit CAEN realized a modular development kit dedicated to Silicon Photomultipliers, representing the state-of-the art in
More informationINDEX. Firmware for DPP (Digital Pulse Processing) DPP-PSD Digital Pulse Processing for Pulse Shape Discrimination
Firmware for DPP (Digital Pulse Processing) Thanks to the powerful FPGAs available nowadays, it is possible to implement Digital Pulse Processing (DPP) algorithms directly on the acquisition boards and
More informationOPERATOR'S MANUAL MODEL 3420 CONSTANT FRACTION DISCRIMINATOR
OPERATOR'S MANUAL MODEL 3420 CONSTANT FRACTION DISCRIMINATOR 1 Innovators in Instrumentation Corporate Headquarters 700 Chestnut Ridge Road Chestnut Ridge, NY 10977-6499 Tel: (914) 578-6013 Fax: (914)
More informationarxiv: v1 [physics.ins-det] 26 Nov 2015
Preprint typeset in JINST style - HYPER VERSION arxiv:1511.08385v1 [physics.ins-det] 26 Nov 2015 The Data Acquisition System for LZ Eryk Druszkiewicz a, for the LZ Collaboration a Department of Physics
More informationHigh-Frequency Programmable PECL Clock Generator
High-Frequency Programmable PECL Clock Generator 1CY2213 Features Jitter peak-peak (TYPICAL) = 35 ps LVPECL output Default Select option Serially-configurable multiply ratios Output edge-rate control 16-pin
More informationVC-827 Differential (LVPECL, LVDS) Crystal Oscillator
C-827 Differential (LPECL, LDS) Crystal Oscillator C-827 Description ectron s C-827 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off a 2.5 or 3.3 volt power supply
More informationChoosing Loop Bandwidth for PLLs
Choosing Loop Bandwidth for PLLs Timothy Toroni SVA Signal Path Solutions April 2012 1 Phase Noise (dbc/hz) Choosing a PLL/VCO Optimized Loop Bandwidth Starting point for setting the loop bandwidth is
More information3 Definitions, symbols, abbreviations, and conventions
T10/02-358r2 1 Scope 2 Normative references 3 Definitions, symbols, abbreviations, and conventions 4 General 4.1 General overview 4.2 Cables, connectors, signals, transceivers 4.3 Physical architecture
More informationDevelopment and Test of a Demonstrator for a First-Level Muon Trigger based on the Precision Drift Tube Chambers for ATLAS at HL-LHC
Development and Test of a Demonstrator for a First-Level Muon Trigger based on the Precision Drift Tube Chambers for ATLAS at HL-LHC K. Schmidt-Sommerfeld Max-Planck-Institut für Physik, München K. Schmidt-Sommerfeld,
More informationUser Guide. SIB Channel MAPMT Interface Board Hamamatsu H7546 series
SIB164-1018 64 Channel MAPMT Interface Board Hamamatsu H7546 series Disclaimer Vertilon Corporation has made every attempt to ensure that the information in this document is accurate and complete. Vertilon
More informationSoftware Module MDPP-16-QDC V0003
Software Module MDPP-16-QDC V0003 16 channel VME pulse processor The software module MDPP-16-QDC provides the functionality of a fast charge integrating ADC, a CFD+TDC and a pulse shape discrimination
More informationEthernet Coax Transceiver Interface
1CY7B8392 Features Compliant with IEEE802.3 10BASE5 and 10BASE2 Pin compatible with the popular 8392 Internal squelch circuit to eliminate input noise Hybrid mode collision detect for extended distance
More informationICS1885. High-Performance Communications PHYceiver TM. Integrated Circuit Systems, Inc. General Description. Pin Configuration.
Integrated Circuit Systems, Inc. ICS1885 High-Performance Communications PHYceiver TM General Description The ICS1885 is designed to provide high performance clock recovery and generation for either 25.92
More informationADVANCED EMBEDDED MONITORING SYSTEM FOR ELECTROMAGNETIC RADIATION
98 Chapter-5 ADVANCED EMBEDDED MONITORING SYSTEM FOR ELECTROMAGNETIC RADIATION 99 CHAPTER-5 Chapter 5: ADVANCED EMBEDDED MONITORING SYSTEM FOR ELECTROMAGNETIC RADIATION S.No Name of the Sub-Title Page
More informationDSA-LX. Digital Signal Analyzer. Radiation Safety. Amplified.
Radiation Safety. Amplified. DSA-LX Digital Signal Analyzer Nuclear Healthcare Homeland Security & Defense Labs and Education Industrial and Manufacturing KEY FEATURES Integrated desktop MCA based on Digital
More informationTechnical Information Manual
Technical Information Manual Revision n. 6 7 July 2011 MOD. N842-N843 8-16 CHANNEL CONSTANT FRACTION DISCRIMINATOR NPO: 00103/00:842-3.MUTx/06 CAEN will repair or replace any product within the guarantee
More informationMulti-channel front-end board for SiPM readout
Preprint typeset in JINST style - HYPER VERSION Multi-channel front-end board for SiPM readout arxiv:1606.02290v1 [physics.ins-det] 7 Jun 2016 M. Auger, A. Ereditato, D. Goeldi, I. Kreslo, D. Lorca, M.
More informationIntegrating Analogue to Digital Converter (ADC)
Integrating Analogue to Digital Converter (ADC) Integrate signal during application of gate - another time variant filter convert charge to digital number = convolution of pulse shape with gate so w(t)
More informationCDR in Mercury Devices
CDR in Mercury Devices February 2001, ver. 1.0 Application Note 130 Introduction Preliminary Information High-speed serial data transmission allows designers to transmit highbandwidth data using differential,
More informationLCC-10 Product manual
LCC-10 Product manual Rev 1.0 Jan 2011 LCC-10 Product manual Copyright and trademarks Copyright 2010 INGENIA-CAT, S.L. / SMAC Corporation Scope This document applies to i116 motion controller in its hardware
More informationvxs fpga-based Time to Digital Converter (vftdc)
vxs fpga-based Time to Digital Converter (vftdc) 18Mbit RAM Generic 8 differential In 8 ECL out 32 differential in VME64x: Register, Data Readout 32 LVTTL in Trigger Interface Trg/Clk/Reset/Busy VXS P0:
More informationGetting started with OPENCORE NMR spectrometer. --- Installation and connection ---
Getting started with OPENCORE NMR spectrometer --- Installation and connection --- Assembly USB The USB module is bus-powered. That is, DC power is provided by the personal computer via the USB cable.
More informationPARIS-MB User Manual
PARIS-MB User Manual Serni Ribó Institut de Ciències de l Espai (CSIC/IEEC) January 7th, 2014 Version 1.0 1 Instrument Description The PARIS Multi-Band receiver is a GNSS reflection receiver capable of
More informationApplication Note 5044
HBCU-5710R 1000BASE-T Small Form Pluggable Low Voltage (3.3V) Electrical Transceiver over Category 5 Unshielded Twisted Pair Cable Characterization Report Application Note 5044 Summary The Physical Medium
More information19MHz to 250MHz Low Phase-Noise XO PAD CONFIGURATION
FEATURES < 0.6ps RMS phase jitter (12kHz to 20MHz) at 155.52MHz 30ps max peak to peak period jitter 8bit Switch Capacitor for ±50PPM crystal CLoad tuning о Load Capacitance Tuning Range: 8pF to 12pF Ultra
More informationPI6LC48P Output LVPECL Networking Clock Generator
Features ÎÎFour differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz
More informationFPGA BASED DATA AQUISITION SYSTEMS FOR PHYSICS EXPERIMENTS
INTERNATIONAL PHD PROJECTS IN APPLIED NUCLEAR PHYSICS AND INNOVATIVE TECHNOLOGIES This project is supported by the Foundation for Polish Science MPD program, co-financed by the European Union within the
More informationA NEW GENERATION PROGRAMMABLE PHASE/AMPLITUDE MEASUREMENT RECEIVER
GENERAL A NEW GENERATION PROGRAMMABLE PHASE/AMPLITUDE MEASUREMENT RECEIVER by Charles H. Currie Scientific-Atlanta, Inc. 3845 Pleasantdale Road Atlanta, Georgia 30340 A new generation programmable, phase-amplitude
More information4 x 10 bit Free Run A/D 4 x Hi Comparator 4 x Low Comparator IRQ on Compare MX839. C-BUS Interface & Control Logic
DATA BULLETIN MX839 Digitally Controlled Analog I/O Processor PRELIMINARY INFORMATION Features x 4 input intelligent 10 bit A/D monitoring subsystem 4 High and 4 Low Comparators External IRQ Generator
More information10 Mb/s Single Twisted Pair Ethernet Implementation Thoughts Proof of Concept Steffen Graber Pepperl+Fuchs
10 Mb/s Single Twisted Pair Ethernet Implementation Thoughts Proof of Concept Steffen Graber Pepperl+Fuchs IEEE802.3 10 Mb/s Single Twisted Pair Ethernet Study Group 9/8/2016 1 Overview Signal Coding Analog
More informationULTRASONIC TRANSMITTER & RECEIVER
ELECTRONIC WORKSHOP II Mini-Project Report on ULTRASONIC TRANSMITTER & RECEIVER Submitted by Basil George 200831005 Nikhil Soni 200830014 AIM: To build an ultrasonic transceiver to send and receive data
More informationSPADIC Status and plans
SPADIC Status and plans Michael Krieger TRD Strategy Meeting 29.11.2013 Michael Krieger SPADIC Status and plans 1 Reminder: SPADIC 1.0 architecture from detector pads single message stream: signal snapshot
More informationFinal Results from the APV25 Production Wafer Testing
Final Results from the APV Production Wafer Testing M.Raymond a, R.Bainbridge a, M.French b, G.Hall a, P. Barrillon a a Blackett Laboratory, Imperial College, London, UK b Rutherford Appleton Laboratory,
More informationEnhanced neutron diagnostics data acquisition system based on a time digitizer and transient recorder hybrid module
Fusion Engineering and Design 81 (2006) 1873 1877 Enhanced neutron diagnostics data acquisition system based on a time digitizer and transient recorder hybrid module R.C. Pereira a,, A. Combo a, N. Cruz
More informationWhere is CERN? Lake Geneva. Geneve The Alps. 29-Jan-07 Drew Baden 1
Where is CEN? Jura Mountains Lake Geneva Geneve he Alps 29-Jan-07 Drew Baden 1 29-Jan-07 Drew Baden 2 Angels and Demons? CEN s very own X-33 space plane! 29-Jan-07 Drew Baden 3 LC 27km proton-proton ring
More informationPicosecond time measurement using ultra fast analog memories.
Picosecond time measurement using ultra fast analog memories. Dominique Breton a, Eric Delagnes b, Jihane Maalmi a acnrs/in2p3/lal-orsay, bcea/dsm/irfu breton@lal.in2p3.fr Abstract The currently existing
More informationmesytec GmbH & Co. KG Wernher-von-Braun-Str Putzbrunn Germany Tel.: Fax: REPRESENTED BY:
short form catalogue nuclear physics 2006 Wernher-von-Braun-Str. 1 85640 Putzbrunn Germany Tel.: +49-89-456007-30 Fax: +49-89-456007-39 info@mesytec.com REPRESENTED BY: Overview Readout Electronics for
More informationLow-Jitter, Precision Clock Generator with Two Outputs
19-2456; Rev 0; 11/07 E V A L U A T I O N K I T A V A I L A B L E Low-Jitter, Precision Clock Generator Ethernet Networking Equipment General Description The is a low-jitter precision clock generator optimized
More informationMSCF-16-LN (Data sheet V5.0_01)
(Data sheet V5.0_01) 16 fold Spectroscopy Amplifier with active BLR, CFDs, and Multiplicity Trigger mesytec MSCF-16-LN is an ultra low noise spectroscopy amplifier with active baseline restorer. It provides
More informationDATASHEET 82C284. Features. Description. Part # Information. Pinout. Functional Diagram. Clock Generator and Ready Interface for 80C286 Processors
OBSOLETE PRODUCT NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc Clock Generator and Ready Interface for 80C286 Processors DATASHEET FN2966 Rev.2.00
More informationPI6C49X0208. High Performance 1:8 Multi-Voltage CMOS Buffer
Features 8 single-ended outputs Fanout Buffer Up to 200MHz output frequency Ultra low output additive jitter = 0.01ps (typ.) Selectable reference inputs support Xtal (10~50MHz), singleended and differential
More informationAgilent E4832A ParBERT 675 Mb/s Data Module Agilent E4838A ParBERT 675 Mb/s Generator Front-End Agilent E4835A ParBERT 675 Mb/s Analyzer Front-End
Agilent E4832A ParBERT 675 Mb/s Data Module Agilent E4838A ParBERT 675 Mb/s Generator Front-End Agilent E4835A ParBERT 675 Mb/s Analyzer Front-End Technical Specifications E4832A 675 Mb/s generator/analyzer
More informationLBI-30398N. MAINTENANCE MANUAL MHz PHASE LOCK LOOP EXCITER 19D423249G1 & G2 DESCRIPTION TABLE OF CONTENTS. Page. DESCRIPTION...
MAINTENANCE MANUAL 138-174 MHz PHASE LOCK LOOP EXCITER 19D423249G1 & G2 LBI-30398N TABLE OF CONTENTS DESCRIPTION...Front Cover CIRCUIT ANALYSIS... 1 MODIFICATION INSTRUCTIONS... 4 PARTS LIST AND PRODUCTION
More informationNJ88C Frequency Synthesiser with non-resettable counters
NJ88C Frequency Synthesiser with non-resettable counters DS8 -. The NJ88C is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise
More informationLow-Jitter, 8kHz Reference Clock Synthesizer Outputs MHz
19-3530; Rev 0; 1/05 Low-Jitter, 8kHz Reference General Description The low-cost, high-performance clock synthesizer with an 8kHz input reference clock provides six buffered LVTTL clock outputs at 35.328MHz.
More informationDigital Receiver Experiment or Reality. Harry Schultz AOC Aardvark Roost Conference Pretoria 13 November 2008
Digital Receiver Experiment or Reality Harry Schultz AOC Aardvark Roost Conference Pretoria 13 November 2008 Contents Definition of a Digital Receiver. Advantages of using digital receiver techniques.
More informationHMC1032LP6GE. Clock Generators - SMT. Features. Typical Applications. Functional Diagram. 1G/10G Ethernet Line Cards
Typical Applications Features 1G/10G Ethernet Line Cards otn and sonet/sdh Applications High Frequency Processor Clocks Any Frequency Clock Generation Low Jitter saw Oscillator Replacement Fiber Channel
More informationMX614 MX614. Telephone. Line Line. Interface PRELIMINARY INFORMATION
COMMUNICATION SEMICONDUCTORS DATA BULLETIN Features 1200bps - 1800bps half duplex Bell 202 Compatible Modem Optional 1200bps Data Retiming Facility can eliminate external UART Optional 5bps and 150bps
More informationHM9270C HM9270D HM 9270C/D DTMF RECEIVER. General Description. Features. Pin Configurations. * Connect to V SS. V DD St/GT ESt StD Q4 Q3 Q2 Q1 TOE
General Description The HM 9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high- and low-group
More informationStatus of the CSC Track-Finder
Status of the CSC Track-Finder Darin Acosta University of Florida May 2000 D. Acosta, University of Florida TriDAS Review May 2000 1 Outline Overview of the CSC trigger system Sector Receiver Sector Processor
More informationB. Equipment. Advanced Lab
Advanced Lab Measuring Periodic Signals Using a Digital Oscilloscope A. Introduction and Background We will use a digital oscilloscope to characterize several different periodic voltage signals. We will
More information