Exercise 1: DC Operation of a NOT and an OR-TIE
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1 Open Collector and Other TTL Gates Digital Logic Fundamentals Exercise 1: DC Operation of a NOT and an OR-TIE EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate the operation of NOT and OR- TIE functions. You will verify your results by measuring circuit logic states. DISCUSSION A NOT gate, or an inverter, generates a complement, as illustrated here. A high logic state at the gate input is converted to a low logic state at the gate output. A low logic state input is converted to a high logic state output. 108 FACET by Lab-Volt
2 Digital Logic Fundamentals Open Collector and Other TTL Gates An OR-TIE circuit is illustrated with two switches and an LED. The LED illuminates when either switch A or switch B is closed. Both switches must be open to prevent the LED from lighting. Closing either switch A or B provides a current path from V CC, through the resistor-led combination, to ground. Shown are two open collector buffers connected in an OR-TIE circuit to control an LED. OR-TIE functions can be generated only with open collector TTL gates. FACET by Lab-Volt 109
3 Open Collector and Other TTL Gates Digital Logic Fundamentals If input A is low, then output A is low; the LED is on, and the 7407 gate provides the current path to ground. If input B is low, then output B is low; the LED is on, and the 7407 gate provides the current path to ground. Is the LED on or off when inputs A or B are low? a. on b. off COLLECTOR circuit block. The open collector of the output transistor connects to an external pull-up resistor. 110 FACET by Lab-Volt
4 Digital Logic Fundamentals Open Collector and Other TTL Gates PROCEDURE Locate the OPEN COLLECTOR circuit block, and connect the circuit as shown. NOTE: Internally, A connects to A at the SCHMITT gate and B connects to B at the Standard gate. Set toggle switches A and B on the INPUT SIGNALS circuit block to LOW. Do not place a two-post connector in the OR-TIE terminals. FACET by Lab-Volt 111
5 Open Collector and Other TTL Gates Digital Logic Fundamentals Schmitt Inverter NOTE: A low logic state is 0.8 Vdc or less, and a high logic state is 2 Vdc or greater. With a voltmeter, measure the logic state of input A at the SCHMITT inverter. Input A is logic a. 1. b. 0. With a voltmeter, measure the logic state of the SCHMITT inverter output at A (after the buffer). The A output is a. 1. b. 0. Is the SCHMITT inverter output at A a complement of its input at A? a. yes b. no 112 FACET by Lab-Volt
6 Digital Logic Fundamentals Open Collector and Other TTL Gates Set toggle switch A to HIGH. With a voltmeter, measure the SCHMITT output at A (after the buffer). The A output is a. 1. b. 0. Standard Inverter With a voltmeter, measure the logic state of input B at the STANDARD inverter. Input B is a. 1. b. 0. FACET by Lab-Volt 113
7 Open Collector and Other TTL Gates Digital Logic Fundamentals With a voltmeter, measure the logic state of the STANDARD inverter output at B (after the buffer). The B output is a. 1. b. 0. OR-TIE Set toggle switch A to LOW. Place a two-post connector in the OR-TIE terminals to connect output A to B. 114 FACET by Lab-Volt
8 Digital Logic Fundamentals Open Collector and Other TTL Gates With a voltmeter, monitor the output at B as you set toggle switch B from LOW to HIGH to LOW. Does the pull-up connected at output A serve for output B as well? a. yes b. no Place CM switch 5 in the ON position to connect the LED to the output circuit. Set toggle switches A and B to LOW. Is the LED on or off? a. on b. off Set toggle switch A to HIGH. The LED comes on. Which gate conducts the LED current to ground? a. the STANDARD gate b. the SCHMITT gate FACET by Lab-Volt 115
9 Open Collector and Other TTL Gates Digital Logic Fundamentals Set both toggle switches to HIGH. Does the LED current increase? a. yes b. no Make sure all CMs are cleared (turned off) before proceeding to the next section. CONCLUSION A NOT gate complements a logic state. Open collector gates require a pull-up circuit. In its low state, the output of a gate conducts current to ground. Two or more open collector gates with their outputs connected together perform an OR-TIE operation. OR-TIE connections require the use of open collector gates. REVIEW QUESTIONS 1. A NOT gate a. buffers its input signal. b. c. complements its input signal. d. phase delays its input signal. 2. Based on the circuit conditions shown, a. the LED is on. b. the LED is off. c. each gate shares part of the LED current. d. the alarm is activated. 3. In the circuit shown, the output of each gate is high because a. each gate input is high. b. each gate input is low. c. the LED is off. d. the LED is on. 116 FACET by Lab-Volt
10 Digital Logic Fundamentals Open Collector and Other TTL Gates 4. Refer to the circuit shown. If input A is high, then outputs B, C, and D are, respectively, a. high, high, high. b. low, low, low. c. high, low, low. d. low, high, high. 5. Refer to the circuit shown. If input A is low, then outputs B, C, and D are, respectively, a. high, high, high. b. low, low, low. c. high, low, low. d. low, high, high. FACET by Lab-Volt 117
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