When you have completed this exercise, you will be able to determine ac operating characteristics of a
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1 When you have completed this exercise, you will be able to determine ac operating characteristics of a multimeter and an oscilloscope. A sine wave generator connected between the transistor base and ground produces the ac input signal. The ac output signal is taken between the emitter terminal and ground. 124 FACET by Lab-Volt
2 For ac signals, the collector terminal, which is common to the input and output, is grounded by the low internal resistance of the dc power supply. The ac output signal is taken between ground and the a. base terminal. b. emitter terminal. c. collector terminal. The voltage gain (Av) of the CC transistor circuit is the ratio of the ac output voltage (V o ) to the input voltage (V i ). A V = V o i FACET by Lab-Volt 125
3 The ac emitter resistance is r e'. As shown by the drawing and the following equations, the voltage gain is always less than 1.0. V o = I e x R3 V i = I e x (r e' + R3) Since: V o = I e x R3 and V i = I e x (r e' + R3) Then: A V Vo = Vi = Ie R3 + I e (re ' R3) R3 = re ' + R3 126 FACET by Lab-Volt
4 Which equation is correct for Av? a. b. c. A V Av = Av = Vo = Vi I e R3 I e ( re ' + R3) re ' R3 + R3 d. All of the above. Because the ac emitter resistance (r e' ) is very small compared to R3 (about 25 versus 6800 ), Av is slightly less than 1.0. The voltage drop across r e' is very small compared to the voltage drop across R3. FACET by Lab-Volt 127
5 Therefore, V o essentially equals V i in a CC circuit without a load resistor in parallel with R3. The output signal is in phase with the input signal because the emitter current increases and decreases with the input signal. Because the output signal follows the input signal, the CC transistor circuit is also known as the emitter follower transistor circuit. 128 FACET by Lab-Volt
6 As the base voltage (V i ) increases, the a. emitter current decreases with the input signal. b. emitter current increases with the input signal. c. output signal is out of phase with the input signal. When a very small resistor, such as R4, is placed in parallel with R3, the ac load line becomes very steep. The maximum, nondistorted peak-to-peak voltage of the output signal is greatly reduced because the cutoff point is moved near V CE (at the Q-point). Without a load in parallel with R3, the ac and dc load lines are the same. FACET by Lab-Volt 129
7 The input impedance (Z i ) equals the combined parallel resistance of R1, R2, and x (R3 + r e' ). Because x (R3 + r e' ) is more than 100 times as large as R1 R2, the input impedance (Z i ) equals R1 R2. In this circuit, Z i is 60 k. The following equation determines output impedance (Z o ). Z o = R3 (r e' + R GEN ) Because the emitter resistor (R3) is large, Z o essentially equals (r e' + R GEN ). You can measure output impedance (Z o ) by connecting potentiometer R4 in parallel with R3 and then adjusting R4 to obtain an output signal (V o ) half that of the original. With these conditions, the measured resistance of R4 approximately equals the output impedance (Z o ). You can measure output impedance (Z o ) by connecting R4 in parallel with R3 and adjusting R4 to obtain an output signal (V o ) that is a. equal to the input signal (V i ). b. twice the input signal (V i ). c. half the output signal (V o ). 130 FACET by Lab-Volt
8 Locate the COMMON COLLECTOR circuit block, and connect the circuit shown. In a common collector circuit, the collector voltage is the same as a. V A. b. V B. c. V E. Measure V C, referenced to ground. V C = Vdc (Recall Value 1) FACET by Lab-Volt 131
9 Measure V B, referenced to ground. V B = Vdc (Recall Value 2) Measure V E, referenced to ground. V E = Vdc (Recall Value 3) 132 FACET by Lab-Volt
10 Is NPN transistor Q1 properly biased for ac operation? a. yes b. no V C = Vdc (Step 3, Recall Value 1) V B = Vdc (Step 4, Recall Value 2) V E = Vdc (Step 5, Recall Value 3) While observing the signal on oscilloscope channel 1, adjust the sine wave generator for a 1 khz, 4.00 V pk-pk ac input signal (V i ) at the base of transistor Q1. Connect the channel 2 oscilloscope probe to the ac output of Q1, which is at the emitter terminal. FACET by Lab-Volt 133
11 What is the peak-to-peak voltage of the ac output signal (V o )? V o = V pk-pk (Recall Value 4) Is there any distortion or clipping of the sine wave signal between the ac input and output? a. yes b. no What is the phase relationship between the output and input signals? a. in phase b. 180º out of phase Calculate the voltage gain. V o = V pk-pk (Step 9, Recall Value 4) V i = 4.00 V pk-pk Av = V o i = (Recall Value 5) 134 FACET by Lab-Volt
12 Adjust the input signal (V i ) to 70 mv pk-pk. Observe the output signal (V o ) on channel 2 of the oscilloscope. What is the output signal? V o = mv pk-pk (Recall Value 6) Turn variable resistor R4 fully clockwise (CW). FACET by Lab-Volt 135
13 With a two-post connector, connect R4 to C2. Turn the knob on R4 counter-clockwise (CCW) until V o is exactly half of V i (35 mv pk-pk ). Without disturbing the R4 setting, disconnect R4 from C2 (remove the two-post connector). Measure the resistance of R4. R4 = (Recall Value 7) 136 FACET by Lab-Volt
14 The collector terminal is common to the ac input and output signals. When the transistor is properly biased, the maximum ac output signal is not distorted. The output signal is in phase with the ac input signal. The voltage gain is slightly less than 1.0. An ac load in parallel with R3 reduces the maximum, undistorted peak-to-peak voltage of the output signal. The input impedance is high. The output impedance is low. 1. Set the input (V i ) for a 1 khz, 4.0 V pk-pk signal. FACET by Lab-Volt 137
15 What is the ouput signal (V o )? V o = V pk-pk Place the CM switch 15 in the ON position to change the value of R3 from 6.8 k to 15 k. Observe the output signal (V o ). 138 FACET by Lab-Volt
16 The transistor is operating a. at the cutoff point. b. in the active region during the complete cycle. c. at the saturation point. d. with the base-emitter junction in reverse bias. 2. When R3 was changed from 6.8 k to 15 k, the a. slope of the load line became less steep. b. slope of the load line became steeper. c. Q-point did not change. d. base bias voltage changed. 3. In a CC transistor circuit, the ac output signal is a. in phase with the input signal. b. 180º out of phase with the input signal. c. half the peak-to-peak voltage of the input signal. d. in phase and greater than the input signal. 4. In a CC transistor circuit, the input a. and output impedances are low. b. impedance is low and the output impedance is high. c. and output impedances are high. d. impedance is high and the output impedance is low. FACET by Lab-Volt 139
17 5. A CC transistor circuit is also called a(n) a. collector follower circuit. b. base follower circuit. c. emitter follower circuit. d. low impedance transistor circuit. Make sure all CMs are cleared (turned off) before proceeding to the next section. 140 FACET by Lab-Volt
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