Digital Self Excited Loop Implementation and Experience. Trent Allison Curt Hovater John Musson Tomasz Plawski

Transcription

1 Digital Self Excited Loop Implementation and Experience Trent Allison Curt Hovater John Musson Tomasz Plawski

2 Overview Why Self Excited Loop? Algorithm Building Blocks Hardware and Sampling Digital Signal Processing Tools Cavity Emulators Digital SEL Algorithm Development & Testing Analog SEL Automatic Gain Control Normalizer Phase Pass Discriminator Control Algorithm Development & Testing Microphonic Compensator Magnitude and Phase Lock In-Phase and Quadrature Lock Field Control Architecture

3 Energy Content (normalized) Why Self Excited Loop? Lorentz force detuning Cavity frequency is a function of gradient High Q upgrade cavities Generator Driven Resonator Presently used in CEBAF Slowly ramp gradient while mechanical tuners compensate for cavity tune Self Excited Loop (SEL) Tolerant of cavity mistuning Quickly bring up cavity gradient without running the tuners Recover faulted cavities in milliseconds instead of minutes Gradient vs. Cavity Tune CEBAF 6 GeV CEBAF Upgrade , Detuning (Hz) It s hard to catch a greased pig

4 Algorithm Independent Hardware Reference 70 MHz 56 MHz PLL Field Control Module Legend Dig 56 MHz 70 MHz 1427 MHz 1497 MHz Probe 1497 MHz x LPF ADC FPGA DAC BPF x HPF LO 1427 MHz C a v i t y KLY Down convert 1497MHz to 70MHz Sample 70MHz IF with 56Msps ADC to get In-Phase and Quadrature () components Apply control algorithm in FPGA Produce 70MHz IF with DAC Up convert 70MHz to 1497MHz and send to klystron/cavity

5 Harmonic Sampling Sample 70 MHz IF at 56 Msps 56 Msps 70 MHz I+ Q+ I- Q- I+ Any odd multiple yields 1 / [(2n + 1) / (4 * 70MHz)] 280, 93.3, 56, 40, Msps Break into 28 Msps chains I+, -(I-), I+, -(I-), Q+, -(Q-), Q+, -(Q-), Create 70 MHz from 56 Msps I+ Q+ I- Q- I+ 56 Msps 14 MHz DAC Output Create 14MHz from 56Msps I, Q, -(I), -(Q), I, Q, -(I), Also has the effect of mixing 14MHz with 56MHz Spectrum includes translation products at 42MHz and 70MHz Filter and amplify the 70 MHz component

6 Field Control Hardware PC104 Digital Board RF Board

7 Field Control Hardware 1MHz ADCs & DACs PC104 Digital I/O Field Programmable Gate Array (under PC104) Digital Board ADCs DAC Ref & 56 MHz PLL RX Channels TX RF Board

8 Field Control Hardware

9 Digital Signal Processing Tools FIR (Finite Impulse Response) Stable and linear phase Symmetric coefficients allow for folding Add two delayed samples together then multiply by common coefficient Half as many multipliers

10 Digital Signal Processing Tools IIR (Infinite Impulse Response) Most like analog filter but can be unstable due to recursion Single pole embedded IIR Uses 1-2 -k as coefficient and 2 -k for bit growth scaling (bit shifts) Dynamically configurable k Cutoff goes as ~ factors of 2 k Value Bandwidth 0 (none) 4.7 MHz MHz MHz MHz khz khz khz 7 71 khz 8 35 khz 9 18 khz khz khz k Value Bandwidth khz khz Hz Hz Hz Hz Hz Hz 20 9 Hz 21 4 Hz 22 2 Hz 23 1 Hz

11 Digital Signal Processing Tools CIC (Cascaded Integrated Comb) Good for decimation Sign extend for bit growth, G = (R * M) ^N Pick a combination that gives a factor of 2 R=4, M=2, N=3, G=512 (shift 9 bits) R=8, M=1, N=2, G=64 (shift 6 bits) Normalized Output Sample Rate Normalized Output Sample Rate Decimating cascaded integrator-comb (CIC) filter; N stages, R decimation, M delays

12 Cartesian vs. Polar Coordinates Hard to control SEL in due to spinning phase (frequency detuning) Magnitude & Phase preferred More intuitive Simpler equations

13 Digital Signal Processing Tools Rotation Matrix Cartesian () phase shifter Look-up-tables for sin( ) & cos( ) LUT and multipliers can be reused if multiple clock cycles are available (sin( ) & cos( ) are 90 o apart) x y y X x x + x x', y' x, y cos sin sin cos X sin( ) LUT cos( ) LUT x' y' xcos ycos ysin xsin y X X - y

14 Digital Signal Processing Tools Y COordinate Rotation DIgital Computer Iterative binary search for finding magnitude and phase Angle Tan() Nearest 2 -n Atan() Resultant lies on X axis with residual gain of 1.6 due to approximations (K i ) i d i arctan( 2 ) i di Add the positive and negative angle rotations to calculate the vector angle X Divide accumulated X&Y values by 2 -i (right shift by i) then add or subtract to/from the opposing Y&X depending if the rotated vector was positive or negative for that iteration 1, 1, if if yi y i 0 0 x', y' x y i i 1 1 x, y K K i i x i y i cos sin y i x i d d i i sin cos 2 2 i i

15 Digital Signal Processing Tools PID Controller c( n) mes c( t) k P set k P e[ n] e( t) e[n] k f I S k m t I 0 n 0 e( e[ m] ) d f k S D k Proportional Integral - + Z -1 D d dt ( e[ n] / e( t) e[ n 1]) k P X k I X + Classic method works well Only P and I have been used but D is available Firmware Implementation can be more efficient c[n] Derivative f S k D Z -1 - X /

16 Analog Cavity Emulator Down and up convert to accommodate crystal frequency Change LO frequency to detune the cavity

17 Analog Cavity Emulator BW = 2.86 khz Qeff = 525,000 Unity Gain Non-symmetric due to crystal

18 Digital Cavity Emulator k ADC CIC CIC FIR FIR FIR FIR IIR IIR De DAC 56 Msps 28 Msps 7 Msps 700 ksps 37.2 ksps 56 Msps Legend I, Q I Q CIC: N stages=2, R decimation =4, M delays=1 FIR: 33 taps, ~0.05 normalized cutoff Sample rates are dynamically adjustable for each stage as well as IIR (k=8: normalized cutoff) Tweak the sample rate of the last section (37.2 ksps) to give exactly a 45 Hz filter (Q loaded =3.3x10 7 )

19 Digital Cavity Emulator BW = 45 Hz Qeff = 33,097,000

20 Digital SEL Algorithm Development Analog Self Excited Loop C a v i t y KLY Noise amplified by klystron then filtered by the cavity Limiter amplifies and clips the cavity tone Loop phase shifter provides positive feedback to build resonance Digitally implement what is in the dashed box Limiter (AGC, Normalizer, or Phase Pass) Loop phase shifter (Rotation Matrix or CORDICs)

21 Digital SEL Algorithm Development Automatic Gain Control M set P off ADC CIC CIC FIR FIR X X IIR PID To M&P Rotation Matrix De DAC Limiter Loop Phase Legend I, Q I Q Mag Phs PID Control to stabilize output magnitude Tuning the PID control loop was problematic Worked as a proof of concept Slow lock time

22 Digital SEL Algorithm Development Normalizer P off ADC CIC CIC FIR FIR To M&P / / M set X X Rotation Matrix De DAC Limiter Loop Phase Legend I, Q I Q Mag Phs Divide by the magnitude to normalize to 1 Multiply by the magnitude set point Fixed point division causes errors and noise Limited operating range, setup dependent

23 Digital SEL Algorithm Development < Phase Pass < M set ADC CIC CIC FIR FIR To M&P + M&P To De DAC P off Legend I, Q I Q Mag Phs 2 nd CORDIC converts Mag & Phase to Set Magnitude directly Pass frequency info (phase) w/ loop delay Fast, stable, intuitive, and simple

24 Digital SEL Algorithm Development < Phase Pass < M set ADC CIC CIC FIR FIR To M&P + M&P To De DAC P off Legend I, Q I Q Mag Phs 2 nd CORDIC converts Mag & Phase to Set Magnitude directly Pass frequency info (phase) w/ loop delay Fast, stable, intuitive, and simple

25 Digital SEL Steady State Digital SEL SRF Cavity Testing Measured magnitude, phase, I, and Q sent to diagnostic DACs and plotted on scope When SELin, phase rolls and magnitude is constant I & Q are sinusoidal with a 90 o phase shift Detuned cavity +/-50 khz and tracked it with the SEL Gmes I mes vs. Q mes Spinning vector at fixed magnitude Speed and direction of spin dependent on detuning Phase, I, and Q all flatten out if the cavity is tuned to 1497 MHz Can excite other pi modes by changing LO frequency

26 Power (W) Digital SEL SRF Cavity Testing CMTF Tests on Renascence Turn-on of detuned cavity Bringing RF up is only limited by cavity fill time No excessive power needed 0 to 21 MV/m in 7 ms! RF On External Diode Detector Ptrans Waveform Renascence Cavity Internal Gradient Signal ms/div time (ms) ~7 ms

27 -45 o / 3dB +45 o / 3dB Digital SEL SRF Cavity Testing Map cavity using loop phase +/-45 o shift corresponds to 3dB points Cavity BW ~45Hz (Q=3.3x10 7 ) Easy way to measure cavity Q

28 Digital SEL Firmware Tornado M set ADC FIR FIR CORDIC To M&P and M&P To De DAC Legend I, Q I Q Mag Phs Pipeline implementation to increase clock rate Interleave CORDICs Reuse adds and subtracts, different decisions 56 MHz clock ( to M&P on even clock cycles and M&P to on odd clock cycles) + P off

29 Frequency Discriminator Algorithm Carrier Sweep to MHz Probe Phase P mes Z -1 Frequency is the derivative of phase F err [n] = P mes [n] - P mes [n-1] Probe Phase Discriminator (PZT Drive) Swept-Sine 1 to 1000 Hz 100 ms/div - Z -1 F err Register update rate is adjustable (dt) Probe Phase Discriminator (PZT Drive) Discriminator (PZT Drive) 10 ms/div 500 us/div Measure the phase difference over time Configurable via EPICS +/-40Hz to +/-2.5MHz Stepper Motor Channel +/-150 khz range PZT Channel +/-1.5 khz range

30 Microphonic Compensator I mes + I drv Q Measured Compensation P set -1 X X I P mes - X I Q P gain X Q Result Q mes + Q drv I Legend I Q Phs Based on the phase error Rotate the vector to compensate for detune Add magnitude correction I drv = Q mes * [P gain * (P set P mes )] Q drv = -I mes * [P gain * (P set P mes )]

31 Control Algorithm Development Microphonic Compensation & Magnitude Lock k M set M max P gain ADC IIR IIR To M&P PID Clamp + M&P To Microphonic Comp De DAC P off Legend I, Q I Q Mag Phs Microphonic Compensator locks phase (~.5 o ) PID control of Magnitude needed Fought magnitude regulation issues (~.1%) Need clamp, yields up to 2 1/2 magnitude

32 Control Algorithm Cavity Testing G mes P mes Cavity Probe Cavity Drive Vector Q I Microphonic Compensation P mes & G mes are flat and drive is compensating for microphonics Measured Compensation I Q I Q Result 0.49 o RMS Phase Noise I

33 Control Algorithm Development Magnitude & Phase Lock k M set M max ADC IIR IIR To M&P PID PID Clamp + M&P To De DAC P set P off Legend I, Q I Q Mag Phs PID control of Magnitude and Phase Phase rollover requires PID to be centered Logarithmic magnitude control needed to decouple performance from signal strength

34 Control Algorithm Development < In-Phase & Quadrature Lock < k I set M max ADC IIR IIR PID PID To M&P Clamp + M&P To De DAC Q set P off Legend I, Q I Q Mag Phs PID control of In-Phase & Quadrature No phase rollover or logarithmic magnitude control issues Stable and meets specs (0.5 o, 0.04%)

35 Lock Testing Renascence Q L =8.6x10 6 microphonics microphonics Open loop 1.1 o phase noise Unregulated vs. Open loop 13.6% amplitude noise Closed loop % amplitude noise Closed loop o phase noise Regulated

36 Lock Testing Renascence Testing Expect 4 Hz rms microphonics for C100 upgrade cavity Worst case six sigma (24 Hz rms) corresponds to 45 o detuning for upgrade cavity Piezo induced 45 o microphonics on Renascence System latency measured as 1.3 us Hardware: 600 ns Firmware: 700 ns Suppressed 45 o detuning 45 o rms phase noise reduced to o rms

37 Other Features M set Tone Mode Cavity Emulator k Legend M&P To De DAC I, Q I Q Mag Phs ADC IIR IIR De DAC P set Output 1497 MHz tone at a given magnitude and phase Need to add phase spin so the output frequency can be adjusted, 1497 MHz +/-14 MHz Turn any LLRF module into a cavity for testing Loopback or test another module k = 18, BW = 34 Hz (Q = 4.4x10 7 ) Need to add Lorentz Force detuning effects

38 Put It All Together k=8 ADC CIC CIC FIR FIR FIR FIR IIR IIR De DAC 56 Msps 28 Msps 7 Msps 700 ksps 37.2 ksps 56 Msps

39 Field Control Architecture k I set IQ lock M set M loop M max ADC IIR IIR PID PID To M&P Clamp + M&P To De DAC Q set P set P loop P off Legend I, Q I Q Mag Phs Cavity Emulator Cavity Lock Self Excited Loop Tone Generator Not shown Discriminator Detune Angle Quench Detect More

40 Digital SEL to Lock Transition G mes SEL Mode Lock Mode I mes Forward Power Q mes Spinning phase (sinusoidal ) while in SEL mode Forward power spikes and G mes droops as lock pulls the arbitrary I mes & Q mes to the set points Firmware SELs until the spinning phase aligns with desired set points then switches to lock Eliminates forward power spike and G mes droop 1 ms/div

41 Field Control Firmware

42 Any Questions?