P. Bruschi: Notes on Mixed Signal Design Chap 3, Part.3A

Transcription

1 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 Fully differetial systems: motiatios. Figure illustrate the differece betwee a uipolar ad fully differetial architecture. I a uipolar system, sigals cosists i oltages betwee sigle odes ad groud. Groud is a special ode of the circuit, whh coides with oe of the power rails (i.e. oe of the termials of the power supply). Each iput ad output of the arious blocks coides with a sigle termial. I a fully differetial circuit, sigals coides with potetial differeces betwee couples of odes, oe of whh is groud. learly, a groud is still ecessary, se it coeys supply currets of all blocks. Thus, as usual, for each ode pair we ca defie a differetial oltage (whh carries the iformatio) ad a commo mode oltage. I sigle supply systems, a o-zero d.c. compoet is geerally required for the commo mode oltage, i order to meet the iput commo mode rage of the blocks ad maximize the sigal swigs. Figure. Uipolar (top) ad fully differetial (bottom) architectures. I a fully differetial architecture, all iputs ad outputs cosists of a couple of termials. For example, a amplifier will hae two iput termials ad two output termials. The adatages of fully differetial architectures ca be diided ito three categories: ) Excellet immuity to iterfereces ) Double output rages 3) Improed liearity. Immuity to iterfereces. We will aalyze four differet causes of iterferece: a) No-uiform groud oltage b) No-uiform dd oltage

2 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 c) apacitie couplig d) Substrate oise The problem deriig from o-uiform groud oltage is illustrated by Figure (a), showig a uipolar system. Impedace ZG is due to uaoidable distributed iductaces ad resistaces of the groud lie. The supply curret of block B ad other blocks, ot show i the pture for simplity, flows i the groud lie, producig the oltage drop ZGIG across the groud lie impedace. Figure. No-uiform groud oltage for a uipolar (a) ad differetial (b) architecture. s a result, block B receie a iput oltage gie by: ib Z I () o while, it was expected to receie oly o. I other words, the groud assumes differet potetials across the system due to the curret that flows through it. The blocks that forms the system are coected to groud lie at differet poits, so that they seses differet groud potetials. I a uipolar system, these potetial differeces are summed up to the sigal, as () clearly shows. This problem ca be partularly serious whe the groud curret ludes high frequecy compoets. Examples of blocks that iject high frequecy compoets ito the groud lie are oscillators ad digital sub-systems, whh, due to cotiuous commutatios, absorb a impulsie curret trough the power rails. This is always the case i mixed sigal itegrated circuits. I a differetial system, the potetial differeces preset o the groud lie affect i the same way the two oltages that form the sigal, so that they produces oly a commo mode disturbace. O the other had, the oltage differece is ot altered, se o curret flows through the lies that carry the sigal ad thus o oltage drop is produced across them. learly, all blocks should be marked by a good MM, whh meas that the magitude of the trasfer fuctio from the iput commo mode, to the output differetial mode should be as small as possible. It should be oted that, thaks to their symmetry, fully differetial blocks ca be easily desiged to hae a much higher MM tha their uipolar aalogue. G G

3 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 Se the supply curret flows also i the dd lie, the supply oltage will also be o-uiform across the chip ad subjected to impulsie ariatios. The extet by whh a o-uiform dd affects the arious blocks depeds o their PSS. gai, thak to symmetry, a dd ariatio produces mostly commo mode errors i the output termials of a fully differetial block. s a result, the PS of fully differetial systems is much better tha the MM of uipolar systems. ery importat aspect is that symmetry is maitaied at high frequecy with the exceptio of mismatches of parasit compoets. Therefore, the M ad PS of fully differetial circuits stays high up to relatiely high frequecies. I a mixed sigal itegrated circuit, a method to reduce iterfereces from o-uiform groud ad dd potetials ca be usig differet groud ad dd coductors for the aalog (sesitie) ad digital (oisy) sub-systems, as show i Fig.3. oectio betwee the two power-lie distributios ca be made i a sigle poit of the chip, so that the supply curret of the digital system does ot flows ito the rails of the aalog oes. further improemet ca be usig ee differet pads for the aalog ad digital rails make the coectios out of the chip, i a coeiet place of the prited circuit board (PB) that hosts the itegrated circuit. Ideed, most itegrated circuits hae distt pis for both the aalog ad digital groud ad dd, as show i the figure. This approach is useful to further reduce the digital-to-aalog iterferece also i fully differetial architectures. Figure 3. Typal architecture of a mixed sigal itegrated circuit, with separate groud ad dd rails ad pads. The case of iterfereces deriig from capacitie couplig is show i Fig.4 (a) for the uipolar architecture. The disturbig sigal D, typally with high frequecy compoets, is applied to a lie (i red i the figure), whh is coupled with the sigal lie through capacitace. The sigal lie has path to groud through the output impedace (Zo) of the trasmittig block () ad the iput impedace (ZiB) of the receiig block (B). The iterferece pked-up by the sigal lie is gie by: 3

4 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 ib D Z Z o o Z ib Z ib Z a D Za Z Z o ib with Z a j where Za is the impedace of capacitor a at the frequecy of the iterferece source D. learly, for a gie couplig impedace Za, the iterferece will be smaller if the parallel of Zo ad ZiB is much smaller tha Za. I may cases it is ot possible to guaratee that this occurs. O the other had, due to its symmetry property, a fully-differetial circuit is much more immue also to this type of iterfereces, se the odes of the pair that carries the differetial sigal are affected i a similar way, so that the disturbace is maily a commo mode sigal. learly, the two wires of the pairs caot be coidet, so that they will exhibit differet couplig capacitaces towards the iterferig lie. Thus, a small differetial compoet ca be produced. To aoid this, it is possible to improe the symmetry by replatig the iterferig lie o both sides of the circuit, as show i Fig.4 (b). a () Figure 4. Equialet circuit showig the mechaism of capacitie iterferece couplig (a); Duplatio of the disturbig lie i order to improe symmetry ad ehace iterferece rejectio. Fially, let us cosider substrate oise. This expressio is used to idate the presece of fluctuatios i the substrate potetial, iduced by iterferig sigals. The mechaism is illustrated i Fig.5. Figure 5. ross-sectio illustratig geeratio ad propagatio of the substrate oise. 4

5 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 The dee idated with digital mosfet represets a electro dee that is subjected to large ad fast oltage swig. Typal examples are trasistors belogig to logal gates that perform frequet commutatios or ee to aalog oscillators. The square wae represet a possible sigal preset o the drai (or source) of the digital mosfet. This disturbig sigal propagates ito the substrate through the drai/body (or source/body) juctio capacitace p. Se ay poit of the substrate has a resistie path tor groud (represeted by the substrate tap i the figure), the effect, i the proximity of the drai (source) diffusio, is high pass filterig, producig the impulsie sigal show i the figure. This sigal propagates alog the resistie substrate, represeted as a resistor mesh. Propagatio is accompaied by strog atteuatio, but oltage oscillatios of seeral milliolts ca be obsered at relatiely high distace from the digital mosfet. These oscillatios ca reach sesitie dees, represeted by the aalog mosfet. The disturbace affects the aalog mosfet i two ways: first, it ca be ijected ito the drai/source through the juctio capacitace p. Secod, se the substrate forms the body of all - type mosfets, substrate potetial fluctuatios produces ariatios of the threshold oltage, causig drai curret fluctuatios. possible remedy is eclosig the digital subsectio ito a rig of substrate taps, all tied to groud. This reduces the propagatio of the disturbig sigals produced by the umerous digital gates formig the digital circuit, se the cotact rig short-circuits the currets ijected ito the substrate, makig them flow to groud. further improemet is obtaied by eclosig also the aalog circuits ito a cotact rig, as schematally show i Fig.6. Figure 6. Substrate oise mitigatio by meas of substrate cotact rigs. Fully-differetial systems are also less proe to substrate oise. The reaso is that, at a suffiet distace from the digital (oisy) dees, substrate oise is almost uiform oer relatiely large die portios, so that it produces practally oly commo mode effects, leaig differetial sigals almost ualtered. 5

6 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3. Double sigal rages. osider a uipolar sigal that ca ary betwee two oltages, amely MIN ad MX, with MIN<MX. The total full scale excursio will be FS=( MXMIN). I a sigle supply cofiguratio (i.e. whe the power supply is a sigle oltage source = dd), clearly FS<dd. For a differetial sigal, we ca cosider that each ode of the pair has the same rage of a uipolar sigal. Therefore, idatig with op ad o the oltages of the odes of the pair, we will hae the followig situatios, summarized i table I: oltage Maximum positie sigal Maximum egatie sigal FS op MX MIN (MXMIN) o MIN MX (MXMIN) od= op o (MXMIN) (MXMIN) (MXMIN) Table : Excursio of o, op ad od It ca be easily see that the differetial sigal has a double rage with respect to the idiidual oltages that represet it. Thaks to this property, i the case of sigle supply operatio, a differetial sigal ca achiee a full-scale rage of at early dd. 3. Improed liearity. If we cosider a d.c tras-characterist out (i), i the case of a fully-differetial circuit we will hae the followig coditio: out(i)=od(i)=o(i)-op(i). For the symmetry property of a fully differetial circuit, iertig the iput sigal is equialet to swappig the positie ad the egatie hales, so that op ad o are simply swapped. Thus: out( i op i o i o i op i out i ) ( ) ( ) ( ) ( ) ( ) (3) Therefore, a iersio of the iput sigal produce the iersio of the output sigal (odd symmetry). This property is alid i the geeral case, i.e. also if the characterist caot be cosidered liear. This meas that a Taylor expasio ludes oly odd terms, ad the the characterist is geerally more liear tha the two uipolar compoets op(i) ad o(i) that form it, whh, o the cotrary, ca lude both odd ad ee terms. I terms of harmo distortio, if i(t) is a siusoidal waeform, the output differetial oltage out will lude oly odd harmos, ad this is aother idatio of lower distortio, i.e. improed liearity. These argumets are illustrated by Fig.7, showig the possible depedece of the output uipolar oltages o ad op o the iput sigal i, together with their differece od. Note that the idiidual sigal o ad op are geerally ot symmetral with respect to the axis i=0, while, due to the symmetry of the fully-differetial circuit, o(i)=op(i). This property is used i (3) to demostrate the symmetry of od. Furthermore, Fig.7 well shows how the differetial sigal achiees a double rage with respect to the idiidual uipolar sigals o ad op that form it. 6

7 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 Figure 7. Possible d.c. trasfer characterists of a fully differetial block, ludig both the differetial sigal od ad the two uipolar sigals o ad op that form it. equisites for a correct fully differetial trasfer characterist. I a fully differetial architecture, it is importat that all the sigals (i.e oltage pairs) preset i the circuit hae a costat commo mode oltage. This is ecessary to guaratee that the iput commo mode rage of all blocks that receie those sigals is ot iolated. s a result, the output commo mode oltage of all block should be stabilized to a gie alue. This alue ca ary from block to block, but should be costat agaist process ad temperature ariatios as well as iput sigal Figure 8. Ideal characterist (a), misplaced output commo mode oltage (b), presece of a iput offset (c). 7

8 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 Figure 8 shows three possible d.c. trasfer characterists. The ideal characterist is show i Fig.8 (a) the output commo mode oltage has bee placed i the middle of the output rage of the sigle sigals op ad o. I this way, the output rage where both outputs are i a liear regio is maximized, i.e. the output liear rage is maximized. I Fig. 8 (b) the output commo mode oltage is set to a alue that is too close to omx. The cosequece is that the outputs has little room to rease ad saturate too early to omx. Whe oe of the two outputs saturates, the differetial-to-differetial gai (dd) is haled ad the output commo mode oltage caot be kept costat ay loger. The third example shows a characterist where the output commo mode oltage has bee set to a ideal alue, but a offset io is preset. This is a perfectly acceptable characterist, se the maximum output swig is maitaied. Se the presece of a offset is uaoidable, characterist (c) is what we geerally could aspire to obtai i practe. To summarize, what is importat is to guaratee that the output commo mode oltage ca be reliably set to a precise alue, whh is geerally placed i the middle of the output rage. I most fully differetial blocks, this result is obtaied by meas of a proper feedback loop luded iside the block itself (deomiated MFB: commo mode feedback). Fully differetial operatioal amplifier: fuctioal properties ad simple cofiguratios The symbol of a fully differetial amplifier is show i Fig.9. The ideal equatio that ties the output ad iput differetial mode oltages is: od with (4) id more realist relatioship that takes ito accout also the presece of a offset-oise iput equialet source () ad of the fiite gai is the followig: with od (5) We hae to add a equatio that says that the output commo mode oltage is costat: id costat (6) oc This characterist is idated i the symbol by a small reersed triagle placed close to the tip of the mai triagle. Figure 9. Symbol of the fully differetial amplifier 8

9 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 The first cofiguratio that we will aalyze is the geer closed loop coectio show i Fig.0 (a). We cosider that the trasfer characterist of etwork is the followig: id (7) od We hae already see (see the chapter o sesor iterface, switched capacitor sectio) that a equatio of this kid, combied with (5) leads to the followig approximatio, proided that >> ad the system is stable: id k ' (8) where is the iput referred oise filtered by the /(-) trasfer fuctio (geerally of low pass type). I the followig discussio, we will use the symbol to idate also, for simplity, but it must be remembered that we are actually dealig with a filtered ersio of the iput referred oise. I other words, we will assume that i the frequecy bad of iterest. ' (9) Figure 0. Geer feedback coectio (a) ad uity gai coectio (b). s a partular case we cosider the uity gai cofiguratio show i Fig.0(b). This is ot properly a uity gai system, se there are o termial remaiig to apply a iput sigal. Neertheless, it is a importat cofiguratio for switched capacitors circuits, where it represets a reset situatio, where oltages across all capacitors assume a kow alue. This cofiguratio is characterized by the followig equatios: id ; (0) od The first equatio regards the differetial oltages ad is equialet to (7) with = - ad k=0. The: Usig the secod of (0) ad (6), we easily fid: id od oc () 9

10 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 0 ; i i () ad: ; o o (3) Note that without (6) oly the differetial oltages would hae bee determied, while the idiidual oltages at the iput ad output termials would hae bee ucertai. This highlights oce more the ecessity of stabilizig the output commo mode oltage to a kow alue. Let us ow cosider the amplifier of Fig., obtaied applyig a resistie feedback etwork to the fully differetial op-amp. Figure. Fully differetial amplifier with resistie feedback (a). Network used to calculate i (b) Nomially =B ad =B. I practe, mismatches are preset ad eed to be take ito accout. osiderig the etwork of Fig.(b), we ca calculate i as a fuctio of s ad o. S o S o i (4) With the same priple, we ca calculate i: B B B S B B B o i (5) We ca itroduce the followig ariables: B B B ; (6) learly, i the omial circuit = =/(+). The we ca decompose ad ito a mea compoet, m ad a mismatch error :

11 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 The, we ca re-write (4) ad (5) usig (6) ad (7): Subtractig (9) from (8) we obtai. m ; m (7) i o m Sm (8) i om S m (9) (0) i i od m where Sd ad Sc are the differetial ad commo mode oltages of the source S, defied as: Sd oc Sd m Sc S S S S ; Sc () I this aalysis we will eglect the iput oise / offset, so that (8) becomes, id=i-i=0. Thus: od Sd m m Sc oc From () we fid that the differetial-to-differetial gai dd is: m () m dd (3) m omial Due to mismatch betwee the upper (,) ad lower (B, B) part of the feedback etwork, the output differetial oltage ludes also a term that depeds o the differece betwee the source commo mode oltage (sc) ad the output commo mode oltage (oc). Se oc is fixed to the costat, this meas that the output differetial oltage is sesitie to the source commo mode oltage. Therefore, the commo-to-differetial mode gai (cd) will be gie by /m ad the M turs out to be []: M cd dd m m m dd m (4) Sem is goig to be idepedet of the resistace alues (it is a matchig error that depeds oly o relatie resistace mismatches), the higher dd, the higher the M. Equatios (3) ad (4) describe the behaior of the amplifier with respect to the output differetial oltage. I a fully differetial circuit, it is importat also to study the behaior of the commo mode compoet. learly, the output commo mode oltage is kow, se it is fixed to by the iteral MFB circuit. The, the quatity that has to be determied is the iput commo mode oltage of the operatioal amplifier,. I geeral, the reaso of aalyzig the commo mode compoets is erifyig that they do ot exceed the correspodig rages. Therefore, whe aalyzig the commo

12 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 mode compoets, the required degree of precisio is usually much lower tha for differetial compoets. The we will eglect the matchig error, ad we will use the aerage compoets m that we will cosider equal to the omial alue. Summig up (8) ad (9) ad diidig the result by, we obtai: Sc (5) where Sc is the commo mode oltage of the sigal source, gie i (). For amplifatios dd>>, <<(), so that is early equal to Sc. It is the importat to check that for eery possible alue of Sc (that depeds o the type of sigal sources), stays iside the iput commo mode rage of the amplifier. limitatio of the amplifier of Fig.(a) is its low iput resistace. The differetial mode iput resistace is equal to, whh caot be made larger tha a few M, due to limitatio o the feasible resistace alues. ery ofte, oise ad badwidth cosideratios impose much smaller alues for, resultig i iput resistaces of a few k. These alues are defiitely too small for a istrumetatio amplifier. possible solutio is usig the two-stage architecture show i Fig., represetig the fully differetial ersio of the well kow three-opmp architecture. Figure. three-opmp fully differetial istrumetatio amplifier. The first stage, formed by the two sigle/eded opmps, amplifies the iput differetial sigal by (+G/G) but leaes the iput commo mode oltage uchaged. I ideal coditios (=0), the secod stage, formed by the fully differetial amplifier, amplifies oly the differetial sigal ad reject the commo mode oe. The output commo mode oltage is fixed to ad it does ot deped o the iput commo mode oltage. It ca be easily show that this stage offers also a ery high iput resistace. Note that we hae obtaied this result by addig two additioal Opmps of sigle-eded type. possible questio is whether it is possible to obtai a high resistace fully differetial amplifier with precise gai usig oly a sigle fully differetial amplifier. Note that i uipolar systems, a sigleeded Opmp ca be used to build the o-iertig cofiguratio, whh has a high iput resistace. Such a possibility does ot exist for the i the fully differetial domai, se the fully differetial Opmp does ot perform the same fuctio that the sigle-eded Opmp does i the uipolar domai. s Fig. 3 shows, i the uipolar domai, the sigle-eded Opmp accepts two distt iput sigals, amely the iertig ad o-iertig iputs. O the other had, i the fully differetial domai, each sigal requires two coectios, thus the Opmp accepts oly oe iput sigal. If we use that iput for

13 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 the feedback etwork, the there is ot a free high resistace isertio poit for coectig the amplifier to the sigal source. Figure 3. Equialet block diagrams of the sigle eded (left) ad fully differetial (right) amplifier i the uipolar ad fully differetial domai, respectiely. I the fully differetial domai, the equialet of a differetial amplifier is the DD (Differetial- Differece mplifier) show i Fig.4. Figure 4. Symbol of the differetial differece amplifier. The amplifier sums up sigals ad B or, if the differet coetio of B is used, subtracts B from. The DD is characterized by the followig iput/output ideal characterist: od (6) B DD with a ery high gai (ideally ifiite) costitutes the DD-Opmp. It ca be easily show that, i terms of iput ad output sigal, the DD-Opmp is the direct equialet of the sigle-eded Opmp: it is capable of amplifyig the differece of two distt sigals ( ad B ), ad the iput resistace at the two iputs ca be made high by desig (i.e. usig a MOSFEF differetial pair). example of use of the DD-Opamp is show i Fig.5, where the architecture of a istrumetatio amplifier is show. osiderig that o curret flows ito the iput termials, due to the ery high resistace, the: B ' Substitutig (7) ito (6) we get: ; S B (7) od 3

14 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 od od S od S (8) / S Figure 5. DD-based istrumetatio amplifier Se >>, the gai of this istrumetatio amplifier is the +/. This architecture is frequetly used i moder fully-differetial itegrated istrumetatio amplifiers. switched capacitor, fully differetial amplifier. The switched capacitor approach ca be used to obtai a fully differetial amplifier capable of performig offset cacellatio ad flker oise reductio by meas of correlated double samplig (DS). The schemat iew of the amplifier is show i Fig. 6. Figure 6. fully differetial switched capacitors amplifier. The operatig cycle is diided ito two phases. Positio of the switches i phase ad is idated by the umbers close to the termials. O ad I are costat oltages. I the followig aalysis we will assume that =B, =B. We will aalyze the amplifier by first cosiderig the situatio i phase, show i Fig. 7. 4

15 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 Figure 7. Switch cofiguratio i phase. It is a closed loop cofiguratio already aalyzed, for whh: () i () () () ; i (9) oltages of the arious capacitors ca be easily foud: () () B () () B O O I phase, the output differetial oltage is gie by: () () I I () () (30) od (3) ob The, oly iput referred oise oltage (ludig also the offset compoet) is preset at the iput. o t the ed of phase, all the switches are first ope, so that the oltage across all capacitors are sampled (samplig istat). The samplig operatio iole the additio of kt/ oise cotributios to all the capacitors. We will eglect these errors i the followig aalysis for simplity. To see how kt/ oise affects the output oltage of a switched capacitor circuit, refer to the charge amplifier (iterface for capacitie sesors) discussed i hap.. The, we will assume that the oltages i (30) are sampled. Whe the amplifier get ito phase, the situatio show i Fig. 8 occurs. First, ote that the iput commo mode oltage of the amplifier is ot immediately kow as i phase. Its alue will be calculated later; ow, we will simply idate it as. The: 5 ()

16 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 () i () () () () () ; i (3) The oltage across capacitors ad B is gie by: () () B () () () () S SB (33) Figure 8. Switch cofiguratio ad charge trasfer i phase. I phase, it is ot possible to directly write the oltage across capacitors ad B, se they hae oe termial coected to the output oltage, whh is a ukow as well. We hae to cosider the charges Q ad QB trasferred ito capacitors ad B, respectiely ad write: () () B () () B Q Q B where Due to the extremely high iput resistace of the amplifier, the charges ito ad B are the sum of the charges that flows ito the correspodig amplifier iput termials. These charges come maily from capacitors ad B, due to the oltage chage they experiece i the trasitio from phase to phase. dditioal charges, whh we hae represeted i Fig.8 by QJ ad QJB, derie from charge ijectio pheomea that will aalyzed later. The, we ca write: 6 B (34)

17 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 Q Q B Q Q Usig (30) ad (34), we fid: B Q Q J JB () () QJ where () () B Q J (35) () () B O O () () Fially, we ca calculate the output oltages as: () () () () S SB () () I I Q Q J JB (36) () o () ob The, usig (36) ad (3) we fially get the complete expressio of the output oltages: () o () ob () () () () O O () () () i () ib () () () () () () S SB () () I I Q Q Output differetial oltage. Subtractig ob from o, with simple algebra passages, we fid the followig expressio for the output differetial oltage: () QJ QJB () SD S SB () od () SD J JB (37) (38) (39) The ideal behaior is that of a amplifier with gai =/. programmable gai ca be easily obtaied by usig digitally programmable capacitors for ad. example of programmable capacitor is show i Fig. 9. apacitor is always coected se a cofiguratio with zero capacitace is meaigless. The other capacitors, amely 00, 0 ad 0 ca be added to the total capacitace by closig the correspodig switches, cotrolled by digital lies b0. Figure 9. digitally programmable capacitor. 7

18 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 I additio to the ideal output sigal, we hae two error cotributios. Oe is due to the oise / offset oltage of the amplifier,, whh appears as the differece betwee two samples take at two differet istats, ad the udergoes correlated double samplig (DS). The other error term, is due to charge ijectio. It is useful to refer both cotributio to the amplifier iput, by simply diidig the output error by gai. The result is summarized i the followig table: ) () mplifier oise Output cotributio eferred to the iput ( () () harge ijectio Q Q Q J JB Q J JB Table. Output ad iput referred error cotributio for the switched capacitors amplifier It is importat to state two poits: -) For large alues of, the iput referred oise of the amplifier coides with the iput referred oise of the Opmp, after applatio of correlated double samplig. -) The charge ijectio cotributio depeds o the differece of the charges ijected o the egatie ad positie side of the differetial structure. Due to symmetry, the two charge compoets ted to compesate each other ad the residual compoet will be oly a matchig error of the charges. Iput commo mode oltage. I a fully differetial system, it is importat to aalyze also the commo mode alue of eery ode pair that represets the sigals. This aalysis is aimed to check that the commo mode oltages do ot experiece ariatios that could exceed the iput or output rages of the block ioled i the system. Therefore, o partular precisio is required ad broad approximatios ca be used I the case of the switched capacitor amplifier, the output commo mode oltage is fixed to, while the source commo mode oltage, S, is fixed by the characterists of the source itself. Therefore, the oly ukow is the commo mode oltage of the operatioal amplifier iputs, i.e.. Summig up the expressios of o ad ob gie i (38) ad diidig the result by two, we obtai: () () J JB O S I (40) Neglectig the charge ijectio term, whh is ot importat due the low precisio requiremets, ad solig (40), we get: () O 8 Note that i phase, was equal to. It is desirable that this alue is maitaied also phase, or, at least, small ariatios with respect to are produced by the trasitio. To obtai this result O is set equal to ad I as close as possible to S. I the case that it is ot possible to predt the S I Q Q (4)

19 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 commo mode oltage of the sigal source, it is importat to guaratee that, for oe of the possible S alues, goes out of the iput commo mode rage of the Op-mp. The origi of charges Qj ad QjB. harges Qj ad QjB hae two ami origis: harge ijectio from the switches harge iduced by ariatio of the iput commo mode oltage of the amplifier (). I this sectio, we will simply describe the secod of the two causes, se the first oe, amely charge ijectio from the switches, is a much more geeral problem for switched capacitor circuits ad will be discussed i ext sectio. The effect of a chage of the iput commo mode oltage i the trasitio betwee phase ad phase is depted i Fig.0. The figure represet the amplifier with the parasit capacitaces betwee the iput termials ad groud (commo mode iput capacitaces). The other elemets of the circuit, ad, i partular, the feedback etwork hae bee omitted for the sake of simplity. Figure 0. Iput charges deriig from iput commo mode ariatio across phase ad If the commo mode udergoes a ariatio, the the followig charges flows through the parasit capacitors p ad p: Q ; Q (4) p Se there will be a uaoidable mismatch betwee p ad p, charges Q ad QB will be slightly differet ad the effect of this differece will itroduce a cotributio to the charge ijectio error reported i table. To miimize this effect it is importat to keep ariatio across phase ad phase trasitio as small as possible. B pb The switch charge-ijectio pheomeo. The pheomeo of charge ijectio is geerally related to switches. I a ideal switch, the cotrol sigal simply opes ad close the coectio, with o side effects. I itegrated circuits, switches are implemeted with MOSFETs: the switch termials are the source ad drai, while the cotrol sigal is applied to the gate. Se parasit capacitaces exist betwee the gate ad both the drai ad source, a parasit iteractio betwee the cotrol sigal ad the switch termials occurs. Figure shows the equialece betwee a ideal switch ad the MOSFET-switch. Note that i a MOSFET-switch, as i a ideal switch, the curret betwee the termials ca flow i both directios, thus it is ot possible to 9

20 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 decide a priori whh termial operates as the source ad whh as the drai. Thus, we hae geerally idated with N ad N the two termials of the switch. apacitie couplig betwee the cotrol sigal (ck) ad termials N ad N is due to two differet kid of capacitaces: The itris capacitace, due to modulatio of the mobile charge i chael, represeted by the blue symbols i Fig.. The extris capacitace due to the oerlap betwee the gate ad the drai / source diffusios, represeted by the two capacitors O ad O i Fig.. Figure. The MOSFET switch, with the oerlap capacitors ad the charge accumulated ito the chael i the o state. t ay trasitio of the cotrol sigal, the charge accumulated i both types of capacitaces udergoes a massie ariatio, so that a charge flows from the cotrol termial to the switch termials N ad N. The portio of this charge that origiates from the chael is geerally referred to as charge ijectio, while the portio due to the oerlap capacitaces is geerally idated as clock feedthrough. The differece betwee the two pheomea is that the clock feedthrough, beig due to almost ideal capacitors, is maily liear, while the charge accumulated i the chael is a oliear fuctio of the oltages. Se the effects are similar, we will simply use the term charge ijectio for both. Fig. gies a simple represetatio of what happes whe a switch, iitially o, is tured off. Figure. harge trasfer durig occurrig whe a -MOSFET-switch is tured off The mobile charge accumulated ito the chael is ejected ito the switch termials (charges QJ ad QJ). t the same time, the trasitio of cotrol oltage ck ijects the charges Qcf ad Qcf through the oerlap capacitors. The et result, show o the right side of the figure, is the ijectio of charges Q ad Q. For a -MOSFET, these charges are egatie. Whe the switch is tured o agai, we hae a similar pheomeo but the ijected charges are positie. The effect of charge ijectio ca be easily uderstood cosiderig the simple track ad hold circuit of Fig. 3. s the diagram o the right shows, the cotrol sigal passes from the high to the low alue at istat tc. s a cosequece, the switch is tured off ad the circuit passes from the track phase, where the output oltage is equal to the iput oltage S, to the hold phase where the alue of S sampled at tc is maitaied. The two charges Q ad Q are ijected ito the switch termial at the samplig istat. Note that oly Q produces a effect, se it is accumulated ito capacitor, alterig the sampled alue. O the cotrary, Q flows ito the source S producig o effects o the output sigal. The effect of charge ijectio Q o the output oltage is represeted i the plot with the ariatio 0

21 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 that, i track ad hold circuits is called pedestal oltage. The charge ijected by MOSFET-switches of miimum size are of the order of a few f (femto-oulomb). The error = Q/ is the of the order of a few m whe is pf. Figure 3. harge trasfer durig occurrig whe a -MOSFET-switch is tured off I a more complex circuit, such that of Fig.6, it is ot simple to study the role of all the switches i determiig charges Qj ad QjB. but the cocept is just the same. For example, the switches that, i phase, close the amplifier i uity gai cofiguratio, iject charges directly ito the amplifier iput odes. harge ijectio ca be reduced by usig switches of miimum area ad choosig ery large capacitors (e.g. i Fig.3, ad i Fig.6). Ufortuately, this make the chargig trasiets loger, thus reducig the maximum clock frequecy. Furthermore, large capacitaces are ofte ot allowed by area occupatio costraits. method that is ofte used to compesate charge ijectio is the use of dummy switches [3] as show i Fig. 4. The dummy switches are clocked with the ierse of the cotrol sigal, so that they iject a charge that is opposed to that of the mai switch. Their termials are shortcircuited as show i the figure, to preet them from affectig the switchig fuctio (they hae o effect i terms of coectio). Note that the two charges ijected by a dummy switches ito its termials are collected together oto the same termial of the mai switch. Therefore, to obtai charge compesatio, their width has to be half of the mai switch width. Note that charge compesatio occurs oly if the charges ijected by the mai switch ito its two termials are idetal, i.e. Q=Q i Fig. 3. This geerally does ot happe, se the ratio betwee Q ad Q depeds o seeral parameters, such as the impedaces see from the two termials ad the clock rise ad fall times. harge ijectio is diffult to model [4] ad empiral recipes are ofte adopted. Furthermore, mismatches betwee the mai switch ad the dummy-switches cotribute to preet a perfect charge compesatio. Howeer, the dummy switch approach may cotribute to reduce charge ijectio of at least oe order of magitude. I may cases, as that of Fig. 3, the circuit is sesitie to the charge ijected oly ito oe of the two switch termials so that oly oe dummy switch is required [3]. Figure 4. Use of dummy switches to compesate charge ijectio

22 P. Bruschi: Notes o Mixed Sigal Desig hap 3, Part.3 The MOSFET-switch should be replaced by a complemetary pass-gate (show i Fig.5), wheeer the sigals to be passed hae a rage that may get close to each rail. The pass-gate has the further adatage that its series resistace i the o state is more idepedet of the oltages applied to the switch termials. The pass gate produces also a partial compesatio of the charge ijectio, se the -MOSFET ad p-mosfet that form it are drie by opposite cotrol sigals. Ufortuately, the charge preset i the chael of the two trasistors shows also a opposite depedece o the termial oltage. For example, if the oltages applied to the termials are close to groud, the charge i the - MOSFET will be maximum, while the charge i the p-mosfet aishes. Therefore, charge compesatio i a pass-gate caot be based oly o the p- complemetarity ad dummy switch should be added to both the ad p compoets. Figure 5. harge ijectio i a complemetary pass-gate: charges Q ad Q geerally do ot compesate. efereces []..Kusha, M. Nagata, N.K. erghese, D.J.llstot, Substrate Noise ouplig i So Desig: Modelig, oidace, ad alidatio, Proceedigs of the IEEE, ol. 94, No., December 006, pp [] P.M. apeteghem, J.F.Duque-arrillo, geeral descriptio of commo-mode feedback i fully-differetial amplifiers, proc.of ISS 990, New Orleas, L, -3 May 990, pp [3] K.. Stafford,.. Blachard, ad P.. Gray, completely moolith sample/hold amplifier usig compatible bipolar ad silo-gate FET dees, IEEE J. Solid-State ircuits, ol. S-9,pp , Dec. 974 [4] G. Wegma, E.. ittoz, F. ahali, harge ijectio i aalog MOS Switches, IEEE Joural of Solid State ircuits, ol. S-, No.6, December 987, pp