A Low-Power Design Methodology for High-Resolution Pipelined Analog-to-Digital Converters

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1 A Low-Power Desig Methodology for High-Resolutio Pipelied Aalog-to-Digital Coerters Reza Lotfi Mohammad Taherzadeh-Sai M.Yaser Azizi Omid Shoaei IC-Desig Lab., ECE Dept., Uiersity of Tehra, North Kargar Ae., Tehra, I.R.Ira ABSTRACT I this paper a geeral method to desig a pipelied ADC with miimum power cosumptio is preseted. By expressig the total static power cosumptio ad the total iput-referred oise of the coerter as fuctios of the capacitor alues ad the resolutios of the coerter stages, a simple optimizatio algorithm is employed to calculate the optimum alues of these parameters, which lead to miimum power cosumptio while a specified oise requiremet is satisfied. To determie the bias curret alues of operatioal amplifiers, a oel optimal choice for settlig ad slewig time parameters is proposed applicable to both sigle-stage ad two-stage Miller-compesated opamp structures. Usig the proposed methodology, the optimum alues for capacitors, the resolutios ad the opamp deice sizes of all stages are determied i order to miimize the total power cosumptio. Desig examples are preseted ad compared with coetioal approaches to show the effectieess of the proposed methodology. Categories ad Subect Descriptors B.7. [Itegrated circuits] Types ad Desig Styles VLSI (ery large scale itegratio) Geeral Terms Desig Keywords Low-Power Desig, Pipelied Aalog-to-Digital Coerters, Operatioal Amplifiers. INTRODUCTION Pipeliig is oe of the best approaches to implemet high-speed low-power aalog-to-digital coerters. Desig approaches to reduce the power cosumptio of pipelied ADCs are therefore of great importace to realize medium-to-high resolutio high-speed A/D coerters with the least possible power cosumptio. Seeral approaches hae bee proposed i literature for systematic desig of pipelied A/D coerters. I [] it has bee cocluded that to miimize the power cosumptio of a pipelied Permissio to make digital or hard copies of all or part of this work for persoal or classroom use is grated without fee proided that copies are ot made or distributed for profit or commercial adatage ad that copies bear this otice ad the full citatio o the first page. To copy otherwise, or republish, to post o serers or to redistribute to lists, requires prior specific permissio ad/or a fee. ISLPED 03, August 5-7, 003, Seoul, Korea. Copyright 003 ACM X/03/0008 $5.00. ANALOG INPUT scalig factor: s 0 s s s 3 S/H m bits m bits m 3 bits bits m m m 3 DIGITAL ERROR CORRECTION N bits Figure. The pipelie ADC structure ADC, the resolutio of all the stages ca be chose equal to.5 ust i coerters with resolutios of less tha 0 bits. I [] a systematic desig methodology has bee proposed where resolutios higher tha.5 hae bee proposed for the frot-ed stages of the high-resolutio coerters but the capacitor alues of the stages are ot optimized ad a predefied oise distributio is assumed. I [3] the effects of the capacitor scalig, parallelism, ad o-idetical resolutios per stages o the pipelied ADC power cosumptio are iestigated separately. I the latest reported automatic desig tool for pipelied ADCs [4] the coerter is optimized to miimize the power cosumptio ad area usig geometric programmig. Howeer, the latter algorithm is applied to a coerter with idetical resolutio per stages. As far as we uderstood it appears that either of the proposed approaches are as geeral yet simple as the approach proposed i our work. I this paper with o specific costrait, arbitrary capacitor scalig as well as o-idetical resolutio per each stage is utilized i the desig of the coerter as show i Fig.. Effectie equatios are preseted to optimally determie the capacitor alue ad the resolutio of each stage, i order to miimize the power cosumptio of the coerter, which makes use of operatioal tras-coductace amplifiers (OTAs) with optimized settlig ad slewig times. First, a closed-form equatio for the bias curret alue of a siglestage or two-stage Miller-compesated opamp is deried employig a ioatie dyamic allocatio of the small- ad large-sigal settlig time parameters. The the total static power dissipatio of the pipelied ADC is calculated. I sectio 3, the total iput-referred oise of the coerter is deried. The a desig methodology is preseted to miimize the power cosumptio with a defied sigal-to-oise ratio (SNR). The iput parameters of the optimizatio CAD tool ad related cosideratios are addressed. Fially optimizatio examples cofirmig the efficiecy of the proposed methodology are preseted ad the depedecy of the power cosumptio o the specificatios of the coerter is iestigated. 334

2 . OPTIMUM CURRENT OF THE OTA S. Optimized bias curret of a sigle OTA I a switched-capacitor circuit, the outputs of the operatioal trascoductace amplifiers hae to settle to withi a ery small fractio of their fial alues (e ss ), depedig o the required accuracy of the OTA, i a defiite iteral called the settlig time. The total settlig time icludig the small-sigal (t ss ) ad the large-sigal (t ls ) settlig times should be less tha half of the clock period, i.e. ts tss tls Tclk / tother () where t other is the rest of the half-period for o-oerlappig of two clock pulses. While t ls is due to the limited op-amp slew rate, t ss depeds o the fiite op-amp badwidth. These two parameters both affect the alue of the op-amp curret cosumptio. Coetioally, these time parameters are predefied statically, e.g. oe third of the total settlig time is resered for slewig [5]. Usig such a approach oe of the settlig regimes is domiat i determiig the curret cosumptio. Howeer it is show here that the small- ad large-sigal settlig times ca be chose dyamically so as to hae the miimum possible curret cosumptio. The utilized algorithm ca be applied to siglestage ad two-stage miller-compesated architectures as follows. For a sigle-pole op-amp or a two-pole op-amp where the secod pole is sufficietly larger tha the uity-gai badwidth, the small- ad large-sigal settlig times are related to the op-amp characteristics as: VFS tls SR ad tss. τ.. (,3) πf 3dB π. β. fu where V FS is the full-scale sigal rage, f -3dB the -3-dB badwidth, β the feedback factor, f u the uity-gai badwidth of the op-amp ad the umber of the time costats to be spet to achiee a desired accuracy, equal to l(/e ss ). For a sigle-stage fullydifferetial telescopic- or folded-cascode op-amp (Fig. ), the aboe-metioed parameters ca be related to the curret of the iput deices by [6]: tls Vo CL VDD VSS VFS VFS SR I i / Ii Vi (a) (b) Figure. The (a) telescopic- ad (b) folded-cascode cofiguratios ad t ss. (4,5) β g / C mi load where SR is the op-amp slew rate, I i is the curret of the iput trasistors, g mi is the tras-coductace of the iput deices, ad C load is the load capacitor at each output ode. With the equatio expressed aboe, V FS is the sigle-eded oltage swig, half of the differetial full-scale oltage. Vo CL VDD VSS M Ii M M5 Vi M4 M3 Vi- Vo- CL- Vi- Vo- CL- The required curret of the iput deices required to satisfy the large- ad small-sigal settlig criteria is therefore obtaied from: VFS. Veff, i. Ii ad Ii. (6,7) tls β. tss where g mi I i /V effi ad V effi is chose as the smallest effectie oltage that keeps the iput trasistors i the strog iersio regio ad satisfies the other op-amp specificatios such as gai. If t ls ad t ss are predefied statically [5], I i should be chose as the maximum alue of the aboe two, i.e. VFS. C V load eff, i. I i max,. (8) tls β. t ss leadig to some power beig wasted. Howeer, if the two settlig cotributios are determied dyamically such that the two aboe terms for the curret are equal, some power ca be saed. Therefore the optimum alue for the bias curret of the OTA becomes: V FS. C l( ess ). V load eff, i I OTA, opt Ii, opt. t S β. V FS where t ls t ss t S (the total settlig time). This equatio shows the depedecy of the optimized curret of a telescopic-cascode OTA (or a folded-cascode OTA where the curret alue of the folded brach is assumed proportioal to that of the iput brach) o the load capacitor, the settlig time ad settlig error, the full-scale oltage ad the feedback factor of the operatioal amplifier.. Expasio of the approach to other structures This relatio will be still true ee if gai-boostig amplifiers are utilized [7] proided that the curret cosumptio of those amplifiers is proportioal to the curret of the mai OTA. A proportioal closed-form formula ca also be extracted if twostage Miller-compesated OTAs are used assumig that the compesatio capacitors are chose equal to the load capacitors ad the curret alues i the secod stages of the amplifier are proportioal to the currets of the iput stages. Such a assumptio will be true whe either the secod stages currets are high eough to satisfy the slewig requiremets of the output odes, or class-a/ab amplifiers are used as the output stages [8]. The curret alues obtaied with this relatio are always smaller tha what obtaied by the coetioal methods. This power saig ca be sometimes cosiderably large compared to coetioal techiques where settlig ad slewig times are ot optimized..3 The total curret of the ADC OTAs I order to express the total curret of the OTAs i the etire ADC ersus the ADC parameters, the load capacitors see by each OTA should be calculated. Fig. 3 shows the m-bit residue amplifier i a pipelied ADC. For a OTA used i the residue stage show i Fig. 3, the total capacitie load see by the opamp i the amplifyig phase ca be obtaied from: (9) 335

3 C load ( CS Cop ) CF Cext stage Ccomp Cout _ op CS Cop CF (0) where C F ad C S are the feedback ad samplig capacitors of the amplifier ad C op is the iput parasitic capacitace of the opamp. C ext-stage,c comp ad C out_op are the iput capacitace of the followig stage, the iput capacitace of the comparators of the followig stage sub-adc, ad the output capacitace of the OTA, respectiely. It is istructie to ote that whe the th residue stage is i its hold mode, the ()th stage is i samplig phase; thus the iput capacitor of that stage is obtaied from: m ext stage, CS C F C F C () remidig that the ratio of the C S to the C F of each stage is m -. V r V r V rp Vi C C C m- Decoder m-bit word V r C F C S ( m -)C F Aalog MUX V rp Figure 3. The schematic of the residue stage Cosiderig the fact that the umber of required comparators for a m-bit residue stage is m - ad for a m -effectie-bit residue stage with oe redudat bit is at least m -, the total load capacitor of the th OTA assumig bit redudacy is calculated from: m m ( γ ) m CF C m F ( ) Ccu C out_ op () ( γ ) where C cu is the iput capacitor of each comparator ad γ represets the ratio of C op to C F. If the output capacitace cotributio is regarded as a excess alue represeted by the excess coefficiet ε, the load capacitace ca be rewritte as: m m γ m CF s ( ) ( ) C m ε cu (3) γ where the scalig factor of the th stage, s, is the ratio of the capacitors of the th stage ad those of the th stage ; i.e. s C /C. I this switched-capacitor amplifier, the feedback factor of the OTA i the amplificatio phase, ca be writte as: C F β (4) C C C m γ S F op Therefore the total curret cosumptio of the OTAs i the - stage pipelied coerter, usig (9) for sigle-stage amplifiers ca be obtaied from: Vout * m l( e ). V ( αv ss eff FS IOTAs { t S V FS m.[ CF * ( ). I OTA s ( ) ( m ε * m γ γ γ ). m ) Ccu]} (5) where α is the correctio factor due to the extra curret cosumptio of the peripheral circuits such as the bias circuit. I this equatio, * is the umber of the stages i which the capacitor scalig is performed remidig the fact that the scalig stops as soo as the capacitors are determied by the miimum required capacitor matchig or the output parasitic capacitaces become domiat. The total cotributio of the OTAs i the curret cosumptio of the coerter is expressed ersus the fullscale oltage of the coerter, the total settlig time (a little smaller tha the samplig half-period), the miimum allowed oerdrie oltage of the iput deices, the uit capacitor of the first stage (C F ), the stage resolutios, scalig factors ad fially the iput capacitor of the comparators. I the aboe equatio it has bee assumed that the comparators used i differet stages are all similar. The problem ca be easily geeralized to a case where differet comparators are used for differet stages. Aother importat cosideratio is the sample-ad-hold (S/H) stage. The curret cosumptio of this stage ca be calculated i a similar fashio with a resolutio of m equal to zero. Just the feedback factor of the OTA i the S/H amplifier should be corrected due to the architecture utilized. For example for a fliparoud SHA architecture the feedback factor is smaller tha uity calculated form (4). The total power cosumptio of the coerter excludig the power dissipated i the referece buffers ad the digital error correctio ad calibratio blocks, ca thus be obtaied from (5) plus the curret cosumptio of the comparators, i.e. m ( ).Icu where I cu is the curret cosumptio of a sigle comparator ad m is the umber of effectie bits resoled by the th stage. Note that the power dissipated i the OTAs ad the comparators is the maor part of the total power cosumptio of the ADC []. 3. NOISE CALCULATIONS 3. Iput-referred oise of a residue stage The iput-referred thermal oise of a switched-capacitor amplifier has two mai sources, the o-resistace of the switches ad the operatioal amplifiers. It ca be show that the iput-referred oise due to switches i the switched-capacitor amplifier of Fig. 3 is obtaied from [8]: CS CF Cop i, sw kt (6) ) ( C C S F Remidig that i a m-effectie-bit residue stage (C S C F )/C F m ad the ratio of C op to C F is represeted by γ the (6) ca be rewritte as: 336

4 kt m.( m i, sw γ ) (7) CF Besides, the iput-referred thermal oise of a switched-capacitor amplifier due to the operatioal amplifiers thermal oise is depedet o the OTA architecture. With a fully-differetial sigle-stage OTA, the iput-referred thermal oise of the residueamplifier due to the OTA oise ca be obtaied from [9]: C, 4 F i op kt Roise F BWeq (8) β CS CF I this equatio F is the architecture-depedet excess oise factor due to the o-iput deices of the OTA. As a istace, i the folded-cascode cofiguratio of Fig. -b this factor is g m g m5 calculated from: F (9) g g For a sigle-pole OTA or a two-pole structure where the secod pole is sufficietly larger tha the uity-gai frequecy, the equialet badwidth ca be obiously obtaied from: π g m BWeq β (0) πc load ad R oise /3g m. Therefore the iput-referred thermal oise of the residue amplifier due to the OTA oise, ca be expressed as: kt m m i, op F.( γ ) () 3 Hece, the total iput-referred oise of the switched-capacitor residue amplifier ca be calculated from: m m 4 m m ( ) kt kt 4 i, residue F 3 C F γ () The same equatio ca be deried for a two-stage millercompesated OTA if the compesatio capacitor is chose equal to the load capacitor. 3. Iput-referred oise of the total ADC I a pipelied A/D coerter, the oise power of ay stage whe referred to the iput is diided by the power gais of the precedig stages. Sice the oltage gai of the ith residue amplifier, G i, is equal to mi, the total iput referred oise of the coerter ca be expressed as: 3 4 i, t... G G. G G. G. G3 (3) m m i i Gi i i i The total iput-referred oise of the coerter will be therefore calculated as: 4 F m, m, ( γ ) 3 C, F, i, t kt (4) mi i Makig use of the relatio deried for the load capacitor of the th stage, the aboe equatio ca be simply expressed ersus the alues of the capacitors ad the resolutios of stages whe the OTA cofiguratio ad therefore a estimatio for the excess oise factor F is kow. Whe optimizig, the modificatio parameters of ε ad γ are primitiely defied ad the corrected i a few iteratios. 4. OPTIMIZATION METHODOLOGY 4. Desig procedure I the preious sectios, closed-form equatios for the total iputreferred oise ad the optimized curret cosumptio were extracted as fuctios of the ADC capacitors ad the resolutios of the stages. Usig MATLAB, a simple optimizatio CAD tool has bee deeloped by the authors to implemet a optimizatio problem of the form: Fid the optimum alues of the capacitors ad the resolutios of differet stages, i order to miimize the total power cosumptio of the ADC, while the total iput-referred oise requiremet is satisfied. The mai parameters of the sub-blocks of the coerter icludig the capacitor alues ad the resolutios of differet stages are simultaeously optimized while o limitig assumptio is imposed. It is oly assumed here that the frot-ed stages are all calibrated i order to meet the required accuracy of highresolutio coerters. Note that the calibratio circuitry has usually a egligible effect o the total power dissipatio of the coerter. For the rms alue of the required iput-referred thermal oise oltage oe choice, employed here, is a equal alue with the quatizatio oise oltage calculated from iq V V LSB ref (5) N This choice will lead to 3dB degradatio i the alue of SNR of the ideal ADC. Note that the sigal-to-oise ratio is obtaied from: V ref / SNR 0 log0 (6) i q i th where V ref, the referece oltage, is equal to the sigle-eded fullscale oltage swig. By usig bit redudacy the maximum comparator offset is permitted to be: V V (7) offset ref m where m is agai the effectie umber of bits resoled by the stage. Sice the comparator offset must always meet the aboe relatio, after choosig a specific architecture for the comparators, depedig o the maximum iput offset, the maximum allowed resolutio of the residue stages is determied. The iput parameters for tha CAD tool icludig N (the resolutio of the coerter), V ref, C mi (the miimum required alue to satisfy a specified matchig behaior depedet o the fabricatio process), C cu (the iput capacitace of a sigle comparator), I cu (the curret dissipatio of a sigle comparator), m max (the maximum permitted alue for the resolutio of a residue stage 337

5 determied due to the maximum offset of the comparator), γ r (the ector of γ i s), ε r (the ector of ε i s), F (the excess oise factor depedet o the opamp architecture), ad V eff (the miimum alue for the oerdrie oltage of the iput deices) should be iitially determied for the optimizatio tool. The optimizatio tool will determie the optimum alues for all capacitors, C F s, ad the stage resolutios ad also the optimum alues for the bias currets of the stages. The iput trasistors are the optimally sized usig the optimum alues for the currets ad the oerdrie oltages (V eff ). It should be metioed that some of the iput parameters such as the parameters of the comparators ad if permitted the referece oltage ca be ee optimally chose usig the methodology preseted here. Sice the alues of γ r, ε r ad F were ust the iitial estimatios, a few iteratios accompaied with circuit simulatios are required to modify the optimized alues of the parameters. 4. Desig Examples I order to illustrate the effectieess of this methodology, a few high-resolutio examples are preseted ad compared with coetioal desigs here. Cosider a -bit 3.3-V 50M-Samples/sec pipelie ADC. With a full-scale oltage swig of V p-p,diff (i.e. V ref V) that ca be coeietly realized usig sigle-stage telescopic-cascode opamps, the least-sigificat-bit (LSB) alue is / 488µV ad the optimizatio program suggests a resolutio distributio of [3 ]. Note that the metioed resolutios are the effectie umber of bits ad oe redudat bit is geerated i all stages. The last stage oly cosists of three comparators to form a -bit flash ADC [9]. It is assumed here that the required DC gai of more tha 7dB for the first residue-stage operatioal amplifier ca be realized with such opamp cofiguratio which is erified by HSPICE simulatio results usig BSIM33 model parameters of a 0.5µm CMOS process. Circuit simulatios also erified the settlig behaior of the opamps. Assumig that the miimum allowed capacitace to meet the matchig requiremets is equal to 0.pF, the feedback capacitors of differet stages are suggested as [0.5p 0.p 0.p 0.p]. The samplig capacitors are chose accordig to the required resolutios. I this problem the curret cosumptio of a sigle comparator with a dyamic structure is assumed equal to 00uA. Usig the proposed approach, the total curret cosumptio of the opamps (icludig the curret cosumptio of their bias circuits) ad the comparators of the coerter is estimated to be 4mA. If the coerter was coetioally desiged usig.5-bit residue stages such that the oise cotributio allocated to each stage is half of the preious oe while the cotributio of the first stage is half of the total iput-referred oise [0], the the scalig factors of all stages should be chose equal to 0.5 usig idetical comparators, ad to achiee similar SNR with the preious example, the feedback capacitors of the stages would be [0p, 5p,.5p,.5p, 0.65p,, 0.p] ad the total curret cosumptio of the OTAs ad the comparators would be larger tha 35mA! If the resolutio of the first stage is chose equal to effectie bits ad all the followig stages resole.5 bits, the total curret cosumptio with the same scalig factors (i.e. 0.5) will become 5mA, agai much larger tha the optimized alue. These specificatios were deried assumig o dedicated S/H stages used i the frot-ed proided that the iput sigal chages less tha oe LSB oltage of the first stage betwee the samplig istace of the residue amplifier ad the decisio time of the sub- ADC comparators. Howeer, if a dedicated S/H stage is to be used, the resolutios of the stages for the preious example chages to [0 3 ] while the capacitor alues will be as what depicted i Fig. 4 chagig from 4.pF for the S/H stage to 0.5pF for the secod stage ad 0.pF for the remaiig stages. Fig. 4 shows the curret cosumptio of the OTA ad the comparators of differet stages for two cases with ad without the S/H frot-ed stage. It ca be see that if the frot-ed S/H amplifier is allowed to be omitted [], cosiderable amout of power will be saed. For coerters with resolutios of ot larger tha 0, the optimizatio CAD tool suggests a resolutio of effectie bit (i.e..5 bits) for all stages. This is exactly the same as what proposed by Lewis [] eertheless the capacitor alues are optimized here. The deeloped tool ca be used ot oly to optimize a ADC but also to calculate the power cosumptio of arbitrary desig cases with specific alues for the resolutios, the capacitor alues, the full-scale oltages, the comparator power dissipatios or the OTA oise excess factors. For example cosider a -bit coerter with a supply oltage of.5v. The desiger ca choose the maximum allowed umber of bits per stages, m max, equal to 5 proided that low-offset power-hugry comparators are utilized istead of dyamic structures with usually higher offset oltages but with m max of 3. As aother example, cosider a ADC where the full-scale (referece) oltage ca be chose by the desiger (ad is ot goered by the total system specificatios). With a specific supply oltage the optimizatio program ca easily help the desiger to choose a two-stage opamp architecture (with higher power ad probably higher excess oise factor (F)) with a larger full-scale oltage swig or a sigle-stage cofiguratio with smaller power dissipatio for the opamps but with a smaller V FS (of course proided that both opamps are able to meet the required speed). Curret Cosumptio (ma) with S&H w/o S&H Stage Number Figure 4. The alues of the curret cosumptios ad the capacitors of the stages (with ad without the dedicated SHA) 4.3 Power depedecy o the ADC specificatios Usig the deeloped CAD tool the depedecy of the total curret cosumptio of the ADC o the oerall resolutio ad also the full-scale oltage swig ca be coeietly iestigated. Fig. 5 shows the curret cosumptio of the 50M-Samples/s coerter erses its resolutio whe dedicated sample-ad-hold frot-ed 338

6 stages are used. It ca be obsered that by addig oe bit to the oerall resolutio, the curret cosumptio is icreased with a higher rate i higher resolutios. This is maily due to the fact that i low resolutios the capacitor alues are maily determied by the required matchig rather tha the kt/c oise. Howeer at higher resolutios the thermal oise determies the capacitor alues. Whe the resolutio is icreased by a sigle bit, the magitude of the LSB oltage is haled ad the thermal oise power should become oe fourth. Thus the capacitor alues are to become four times larger. From (5) it ca be cocluded that the OTA cotributios i the total curret cosumptio becomes approximately four times larger howeer the umber of comparators is ot multiplied by four. Hece the total curret is icreased by a factor less tha four. The depedecy of the power dissipatio o the full-scale oltage ca be also iestigated as show i Fig. 6 for a -bit 50MS/s example. It ca be see that if the full-scale oltage is haled, the curret cosumptio is icreased by a factor of more tha two. This behaior ca be clearly predicted from the optimized alue for the curret cosumptio gie by (9) keepig i mid the depedecy of C load o the full-scale oltage. Therefore the power cosumptio of the ADC icreases by scalig dow the oltage. 4.4 The o-ideal frequecy respose The optimized alue for the curret cosumptio of a sigle-stage OTA or a two-stage Miller-compesated OTA, was obtaied assumig that the secod pole frequecy is larger tha the uitygai frequecy of the amplifier ot to degrade the frequecy respose. Howeer it is obious that this assumptio is ot always the case whe the o-domiat poles are ot large eough to be eglected. This fact affects ot oly the settlig behaior but also the thermal oise equialet badwidth of the OTA. This oideal settlig time ca be show to be smaller tha what predicted by (3), therefore the problem has bee oerestimated here. The oise behaior is oerestimated as well sice the oise equialet badwidth of the OTA is smaller tha what predicted by (0) if the secod pole is ot located much higher tha the uity-gai frequecy. 5. CONCLUSIONS I this paper based o a oel approach to desig the operatioal amplifier i a switched-capacitor circuit, a closed-form equatio for the total optimized curret of a pipelied ADC is preseted. Besides, cosiderig the oise sources i a residue-amplifier, a closed-form relatio for the total iput-referred thermal oise of the ADC is deried as well. Based o the deeloped equatios a efficiet desig methodology for pipelied A/D coerters is deeloped. The proposed approach ca simultaeously determie the capacitor alues ad the resolutios of the residue stages of the coerters with o limitig assumptio. Desig examples are preseted to erify the effectieess ad the geerality of the proposed methodology. It has bee show that the deeloped CAD tool ca be ee employed to decide about the architecture of the comparators or the optimum alue for the referece oltage. The depedecy of the curret dissipatio of the ADC o some of the coerter specificatios has bee iestigated as well to illustrate the usefuless of the preseted equatios. Total Curret Cosumptio (ma) The coerter Resolutio (bits) Figure 5. Depedecy of the optimized curret cosumptio of the 50MS/s coerter o the resolutio Total curret cosumptio (ma) Referece oltage (V) Figure 6. Depedecy of the optimized curret cosumptio of the -bit 50MS/s coerter o the full-scale oltage swig 6. REFERENCES: [] S.H. Lewis, Optimizig the stage resolutio i pipelied, multistage, aalog-to-digital coerters for ideo-rate applicatios, IEEE Tras. Circuits &Systems-II, Vol.39, No.8, pp.56-53, Aug. 99. [] J.Goes, et.al, Systematic desig for optimizatio of highspeed self-calibrated pipelied A/D coerters, IEEE Tras. Circuits & Systems-II, ol.45, pp.53-6, Dec. 98. [3] P.T.F. Kwok, H.C.Leug, Power optimizatio for pipelie aalog-to-digital coerters, IEEE Tras. O Circuits & Systems-II, ol.46, pp , May 999. [4] M. Hersheso, Desig of pipelie aalog-to-digital coerters ia geometric programmig, Proc. of IEEE Itl. Cof. o Computer Aided Desig, 00. [5] M. Waltari, Circuit techiques for low-oltage ad highspeed A/D coerters, PhD. Dissertatio, Helsiki Ui. of Tech., 00. [6] B. Razai, Desig of Aalog CMOS Itegrated Circuits, Mc.Graw-Hill, 00. [7] K. Bult, G. Geele, A fast-settlig CMOS opamp for SC circuits with 90-dB DC gai i IEEE Joural of Solid-State Circuits, ol.5, pp , Dec [8] S.Rabii, B.Wooley, A.8-V digital-audio sigma-delta modulator i 0.8-um CMOS, i IEEE Joural of Solid- State Circuits, ol.3, pp , Ju.997. [9] T. Cho, Low-power low-oltage aalog-to-digital coersio techiques usig pipelied architectures, PhD. Thesis, Uiersity of Califoria, Berkeley, 995. [0] A. Abo, P. R. Gray, A.5-V, 0-bit, 4.3-MS/s CMOS pipelie aalog-to-digital coerter, i IEEE Joural of Solid-State Circuits, ol.30, pp.66-7, Mar.995. [] I. Mehr, L. Siger, A 55-mW, 0-bit, 40-MSample/s yquist-rate CMOS ADC, i IEEE Joural of Solid-State Circuits, ol.30, pp , Mar