Tutorial 2 X-treme Efficiency Power Electronics

Transcription

1 1/114 Tutorial 2 X-treme Efficiency Power Electronics J. W. Kolar Swiss Federal Institute of Technology (ETH) Zurich Power Electronic Systems Laboratory

2 2/114 Deep Green Power Electronics J. W. Kolar Swiss Federal Institute of Technology (ETH) Zurich Power Electronic Systems Laboratory

3 3/114 Outline Trends of Efficiency Improvement Converter Loss Components Efficiency Improvement by * Design * Control * Topology & Control Highly Accurate Efficiency Measurement η > 99% Converter Demonstrators Conclusions

4 4/114 Power Electronics Performance Trends Performance Indices Power Density [kw/dm 3 ] Power per Unit Weight [kw/kg] Relative Costs [kw/$] Relative Losses [%] Failure Rate [h -1 ]

5 5/114 Drivers for High Efficiency < 2000 Increase of Power Density / Thermal Limitation / Max. Full Load Efficiency > 2000 Mostly Voluntary Efficiency Requirements for Entire Power Range (100%, 50%, 20%)

6 6/114 Efficiency / Power Factor Limits (5%) 20%...100% Load

7 7/114 General Efficiency Trends Inefficiency (Losses) PV Inverters: Typ. Loss Reduction of Factor 2 over 5 Years

8 8/114 Efficiency Basics Converter Loss Components Efficiency Maximum Efficiency vs. Power Factor

9 9/114 Non-Idealities of Converter Circuits P ( P C U f ) ( U k f ) I (1 D) ( R DR D(1 D) ESR) I V aux 2 E, eq 2 P F P P 2 L DS( on) 2

10 10/114 Non-Idealities of Converter Circuits P P P P k k P k P 2 V V,0 V, I V, II 0 I 2 II 2

11 11/114 Influence of Loss Components on Efficiency Characteristic P 1 2 V 1 P P 1 V P2 1 P 2 P P P P P k k P k P 2 V V,0 V, I V, II 0 I 2 II 2

12 12/114 Influence of Loss Components on Efficiency Characteristic P 1 2 V 1 P P 1 V P2 1 P 2 P P P P P k k P k P 2 V V,0 V, I V, II 0 I 2 II 2 Only Constant Losses 1 1 k 0 1 P k P 1 1 P P V,

13 13/114 Influence of Loss Components on Efficiency Characteristic P 1 2 V 1 P P 1 V P2 1 P 2 P P P P P k k P k P 2 V V,0 V, I V, II 0 I 2 II 2 Only Power Proportional Losses 1 1 I 1 k I const. PV, I 1 k I 1 P 2

14 14/114 Influence of Loss Components on Efficiency Characteristic P 1 2 V 1 P P 1 V P2 1 P 2 P P P P P k k P k P 2 V V,0 V, I V, II 0 I 2 II 2 Quadratically Power Dependent Losses 1 1 II 1 kii P PV, II 1 kii P2 1 P 2 2

15 15/114 Efficiency Maximum P 1 2 V 1 P P 1 V P2 1 P 2 Maximum: Equal Constant and Quadratic Losses V, II, max V,0 P P

16 16/114 Efficiency vs. Power Factor i 2 PV, Ri I1 Ri 1 1 P U I cos 1 1 1,(1) 2 1 THDi ri (1 ) cos Sensible Compromise e.g. for Three-Phase Systems

17 17/114 Measures for Efficiency Improvement Design - Power Semiconductors - Inductive Components / EMI-Filter - Auxiliaries

18 Power Semiconductors 18/114

19 19/114 Power Semiconductors On-State Losses Capacitive Switching Losses C C C C GS iss rss GD C rss C C C DS oss rss

20 20/114 Power Semiconductors On-State Losses Capacitive Switching Losses 1 P I R C ( U ) U f V, T DS, rms DS( on) E, eq 2 2 P

21 21/114 Power Semiconductors R DS( on) R * DS( on) A Si V, T C P Si P Si C C A * E, eq E, eq Si P 1 A A f Silicon Area Related Resistance / Capacitance

22 22/114 Power Semiconductors R DS( on) R * DS( on) A Si C C A * E, eq E, eq Si Optimum Silicon Area - Minimum Losses

23 23/114 Power Semiconductors - Efficiency Barrier R DS( on) R * DS( on) A Si C C A * E, eq E, eq Si P 2 f 2I U f R C * * V, T,min C P P rms 2 P DS( on) E, eq 1 FOM

24 24/114 Power Semiconductors Selection of A Si > A Si,opt Leads to Lower Efficiency in Whole Operating Range

25 Inductive Components / EMI Filter 25/114

26 26/114 Inductive Components Efficiency vs. Volume - Iron Losses L i Ud 1 1 B NA f A A l 2 E P E E PV, E fp B VE ( ) l 24 l l - Copper Losses l l 1 P I R A l l 2 V, W rms W 2 W Iron and Copper Losses are Decreasing with Increasing Linear Dimensions

27 27/114 Selection of the Switching Frequency Example of Single-Phase PFC Rectifier Systems

28 28/114 Selection of the Switching Frequency - Consider Boost Inductor as Part of EMI Filter - Calculate Equivalent Noise Switching Frequency M ˆ N U U d Uˆ U Uˆ U Uˆ U U U 2 2 T,( n) T,( n) 1 ˆ T,(2 n) 2 T,(2 n) 4 Limited Influence of Higher Order Harmonics

29 29/114 Selection of the Switching Frequency - Consider Boost Inductor as Part of EMI Filter - Calculate Equivalent Noise Switching Frequency M ˆ N U U d M U fp, eq, rms UT, rms UN, rms U,, M( ) U P 2 f eq rms d

30 30/114 Selection of the Switching Frequency Equivalent Noise Switching Frequency

31 31/114 Required EMI Filter Attenuation Higher Switching Frequency Increases Required Attenuation

32 32/114 Required EMI Filter Attenuation Higher Switching Frequency Increases Required Attenuation

33 33/114 Minimize Required EMI Filter Attenuation Distribute Harmonic Power Equal over Frequency Range

34 34/114 EMI Filter Optimization G F 1 k(1 k ) L C k opt 0.5 Equal Partitioning of Total Inductance Provides Max. Attenuation

35 35/114 EMI Filter Optimization 1 2 VC C 2 CU k CC VC rv 1 2 VL L 2 LI k L L V (1 r) V L (1 r) k 2 LC V Max L r k C ropt 0.5 Equal Partitioning of Total Volume between L & C Provides Max. Attenuation

36 36/114 EMI Filter Optimization Impact of Switching Frequency and Ripple Ratio on Volume

37 37/114 EMI Filter Optimization Impact of Switching Frequency and Ripple Ratio on Volume (P N =1.5kW)

38 38/114 EMI Filter Optimization Optimization for Minimum Losses at Given Maximum Filter Volume Optimum Values k i and f P are Close to Volume Optimal Design

39 39/114 Measures for Efficiency Improvement Control - Intermittent Operation - Interleaving

40 Intermittent Operation 40/114

41 41/114 Intermittent Operation Operate Converter ONLY at Maximum Efficiency Power Level Adjust Delivered Power by Proper Selection of the Duty Cycle T T on rep P P 2, avg 2, max max Energy Storage Requirement!

42 Parallel Interleaving 42/114

43 Mechanical Version of Parallel Interleaving 43/114

44 44/114 Parallel Operation of Multiple Sub-Systems Features Phase-Shedding (Equivalent to Adjustable Silicon Area!) Features Cancellation of Harmonics

45 45/114 Parallel Operation of Multiple Sub-Systems P P ap 2, a 2 (1 a) P 2, b 2 aopt 0.5 Equal Sharing of Total Power for Minimal Losses

46 46/114 Efficiency Optimum Phase-Shedding Maximization of Part-Load Efficiency 1 1 N P2, sw N 1 P2, sw

47 47/114 Efficiency Optimum Phase-Shedding Deactivation of Cylinders

48 48/114 Ripple Cancellation Operation of n =2 Systems 180 Out of Phase

49 49/114 Ripple Cancellation ˆ i max, n 1 U d 8 f L P ˆ i max, n 2 U d 32 f L P Doubling of Effective Switching Same Switching Losses Possible Red. of Input Capacitance C C/8 or Inductance 2L L/4

50 Scaling Laws of Parallel Interleaving 50/114

51 51/114 Parallel Interleaving (Homogeneous Power) Characteristics Breaks the Frequency Barrier Breaks the Impedance Barrier Breaks Cost Barrier - Standardization High Part Load Efficiency H. Ertl, 2003 Fully Benefits from Digital IC Technology (Improving in Future) Redundancy Allows Large Number of Units without Impairing Reliability

52 52/114 Parallel Interleaving (Homogeneous Power) Multiplies Frequ. / Red. Same (!) Switching Losses & Incr. Control Dynamics H. Ertl, 2003!! Fully Benefits from Digital IC Technology (Improving in Future) Redundancy Allows Large Number of Units without Impairing Reliability N = 3

53 53/114 Remark #1 Volume of Cell-Inductors Harmonics Cancellation Allows Large ripple of Cell Currents Minimum Volume for 100% Current Ripple (DCM)

54 54/114 Remark #2 Impedance Matching Allowed L s Directly Related to Switching Time t s L s U i ts I L t s U I Z i L Parallel Interl. Allows to Split-Up Large Currents Increase of Z / Allows Faster Swtchg

55 55/114 Remark #3 Efficiency/Power Density (Pareto) Limit Parallel Interleaving - Shift of the Pareto Limit Higher Power Densities

56 EMI Reduction due to Parallel Interleaving 56/114

57 57/114 Reduction of EMI Filter Volume Symm. Interleaving 180 Asymm. Interleaving 90

58 58/114 Measures for Efficiency Improvement Topology & Control - Single-Stage vs. Two-Stage Conversion - Synchronous Rectification - Resonant Transition Mode Switching - Interleaving

59 Single-Stage vs. Two-Stage Conversion 59/114

60 60/114 Single-Stage Integration of Functions Examples: * Matrix Converters * Multi-Functional Utilization (Machine as Inductor of DC/DC Conv.) * etc. Integration Restricts Controllability / Overall Functionality (!) Typ. Lower Efficiency / Higher Control Compl. of Integr. Solution Basic Physical Properties remain Unchanged (e.g. Filtering Effort)

61 61/114 Two-Stage Optimal Splitting of Functionality Highly Optimized Specific Functionality High Performance for Specific Task Restriction of Functionality Lower Costs Example of Wide Input Voltage Range Isolated DC/DC Converter

62 62/114 Two-Stage Optimal Splitting of Functionality Example: DC-Transformer Constant (Load Ind.) Voltage Transfer Ratio E.g. adopted by VICOR Sine Amplitude Converter for Fact. Power Architecture Very High Efficiency Resonant Frequ. Switching Frequ. Input/Output Voltage Ratio = N 1 /N 2

63 Resonant Transition Mode 63/114

64 64/114 Technological Limits of Hard-Switched CCM Converters On-State Voltage of Freewheeling Diodes (U F ) Capacitive Switching Losses of MOSFETs (A Si,opt )

65 65/114 Zero Voltage Switching Triangular Current Mode (TCM) Operation Synchronous Rectification Negative Current Ensures ZVS

66 66/114 Zero Voltage Switching Triangular Current Mode (TCM) Operation Synchronous Rectification Negative Current Ensures ZVS

67 67/114 12kW TCM Buck+Boost DC/DC Converter Overlapping Input and Output Voltage Ranges U 1 = V U 2 = V Max. Eff. = 30kW/l

68 68/114 Snubbers vs. TCM Non-Isolated Buck+Boost DC-DC Converter for Automotive Applications 99.3% Efficiency 30 kw/dm 3 Instead of Adding Aux. Circuits Change Operation of BASIC (!) Structure Natural Performance Limit

69 69/114 Measures for Efficiency Improvement Further Concepts - Partial Power Conversion - Ride-Through Boost Converter - Series/Parallel Rearrangement

70 Partial Power 70/114

71 71/114 Partial Power Converter U U U 2 1 c Reduces Rated Power of PPC p c Uc Pc,1 U2 U P1 1 U c 2 Limited Influence of PPC Efficiency on Total Efficiency P P 2 1 Uc (1 ) U 2 Uc (1 ) U 2 c

72 Voltage / Topology Preconditioning 72/114

73 73/114 Voltage / Topology Preconditioning Ride-Through Boost Converter Series-Parallel Reconfiguration (Voltage:2 AND Current x2 Advantage Comp. to Multi-Level Conv.) S/P Reconfiguration also Applicable for 3-Phase System (Star Delta Rearrangement)

74 74/114 Mixed Interleaving Numerous Combinations (ISOP, ISIS, IPOS, IPOP, etc.) * Conventional * Input Series * ISOP = Input Series / Output Parallel Topology Low Inp. Voltage / Output Curr. Harmonics Low Input / Output Filter Requirement Impedance Matching

75 75/114 Highly Accurate Efficiency Measurement Concepts - Power Analyzer - Calorimeter

76 Power Analyzer 76/114

77 77/114 Maximum Admissible Power Measurement Error Admissible Error of Loss Determination NOT Efficiency Determination P P 2 1 V 2 (1 ) P 2 P P V (1 ) P1 (1 ) V

78 Calorimeter 78/114

79 79/114 Two-Chamber Calorimeter Measurements up to 85 C Ambient Temp. Relative Error of Loss Measurements < 3.5%@10W < 1.0%@100W < 0.5%@200W

80 80/114 Ultra-High Efficiency Converters 3.3kW - 2x Interleaved CCM Bridgeless PFC Rectifier - 6x Interleaved TCM PFC Rectifier - Telecom Rectifier Module Research Projects of ETH Zurich Partly Supported by the European Center for Power Electronics

81 3.3kW CCM PFC Rectifier System 81/114

82 82/ kW TCM PFC Rectifier System 1.2kW/dm 3 Bidirectional Supports V2G Concepts Employs NO SiC Power Semiconductors -- Si SJ MOSFETs only

83 3.3kW TCM PFC Rectifier System 83/114

84 84/ kW TCM PFC Rectifier System Measurement Results

85 85/ kW TCM PFC Rectifier System 1.2kW/dm V rms Employs NO SiC Power Semiconductors -- Si SJ MOSFETs only

86 86/114 Ultra-Compact/Efficient TCM PFC Rectifier System Input Voltage Output Voltage Rated Power V AC 420V DC 3.3kW /% V V V 97.4 Limit kW/dm 3 P O /W

87 87/114 Converter Performance Evaluation Based on η-ρ-pareto Front Triple-Interleaved TCM Rectifier (33kHz) Triple-Interleaved TCM Rectifier (56kHz) Double-Interleaved Double-Boost CCM Rectifier (33kHz) Double-Interleaved Double-Boost CCM Rectifier (450kHz)

88 88/114 KEYS for Achieving the Performance Improvement despite Using Old Si Technology Only Basic Topology Employed ZVS Achieved by Only Modifying Operation Mode Active ZVS Triangular Current Mode (TCM) Variable Switching Frequency No Diode On-State Voltage Drop Continuously Guided u, i Waveforms Interleaving Utilization of Low Superjunct. R DS,(on) Utilization of Digital Signal Processing Low Complexity No Aux. Circuits No (Low) Switching Losses No Direct Limit of # of Parallel Trans. Simple Symm. of Loading of Modules No Current Sensor (only i=0 Detection) Spread & Lower Ampl. EMI Noise Synchr. Rectification No Free Ringing Low EMI Filter Vol. Low EMI Filter Vol. & Cap. Curr. Stress Low Cond. Losses despite TCM Low Control Effort despite 6x Interl. the Basic Concept is Known since 1989 (!)

89 89/114 Alternative Converter Concepts (?) Indication for a Natural Performance Limit Source: Dr. Gerald Deboy Plenary IECON 2013, Vienna Minimum Performance Difference for Best Matching of Topology/Semicond./Modulation Only Use BASIC Topologies - Costs are THE Deciding Criteria (!)

90 90/114 Is Another Step of Massive Improvement Possible? Triple-Interleaved TCM Rectifier (33kHz) 6kW/dm 3 Triple-Interleaved TCM Rectifier (56kHz) Double-Interleaved Double-Boost CCM Rectifier (33kHz) Double-Interleaved Double-Boost CCM Rectifier (450kHz)

91 Multi-Cell Approach Series Interleaving 91/114

92 92/114 Telecom Rectifier Employing Series Multi-Cell Approach Specifications Input Voltage 230 V rms (180 V rms 270 V rms ) Nominal Output Voltage 48 V DC Output Voltage Range V DC Rated Power 3.3 kw Target Efficiency 98.5% Target Power Density 3 kw/dm 3 Hold-Up Time 10ms at Rated Power Switching Frequency 20 khz (per Module) EMI Standard CISPR Class A and Class B Input Series Output Parallel (ISOP) Connection

93 93/114 First Optimization Results Calculation of Opt. Maximum Admissible DC-Link Voltage Drop during Hold-Up Time (10ms) Pareto-Optimal for N = 6 Cells (PFC Rectifier + Phase-Shift Full-Bridge) 20% 3kW/dm 3 10% 30% 40% Optimal Performance for 20% Hold-up DC-Link Voltage Drop

94 94/114 Conventional 3.3kW Telecom Rectifier Module 3x Interleaved TCM PFC Rectifier Stages Full-Bridge Phase-Shift DC/DC Converter / Full Bridge Synchr. Rectifier 2.5kW/dm 3

95 95/114 Next Gen. Conventional 3.3kW Telecom Rectifier Module 3x Interleaved TCM PFC Rectifier Stages 2x Interleaved Full-Bridge Phase-Shift DC/DC Conv. / Full-Bridge Synchr. Rectifier 3.3kW/dm 3

96 Scaling Laws of Series Interleaving 96/114

97 97/114 Series Interleaving of Converter Cells Characteristics Breaks the Frequency Barrier Breaks the Silicon Limit 1+1=2 NOT 4 (!) Breaks Cost Barrier - Standardization Extends LV Technology to HV H. Ertl, 2003

98 98/114 Series Interleaving of Converter Cells Series Interleaving of LV MOSFETs (LV Cells) Effectively SHIFTS the Si-Limit (!) Assumption: Chip Area of each LV Chip Equal to the Chip Area of the HV Chip Scaling of Specific On-State Resistance 1 ( RDS,on A) eff ( R 15 DS,on A). N Excellent Opportunity for Extreme Efficiency Ultra-Compact Converters

99 99/114 Series Interleaving of Converter Cells Interleaved Series Connection Dramatically Reduces Switching Losses (or Harmonics) N 1 t t t t t p S t t t Scaling of Switching Losses for Equal Δi/I and dv/dt 1 1 PS,N P S,N= 1 (... ) 2 3 2N N Converter Cells Could Operate at VERY Low Switching Frequency (e.g. 5kHz) Minimization of Passives (Filter Components)

100 Remarks on Performance Indices Couplings & Limits 100/114

101 101/114 Power Electronics Converters Performance Indices [kg Fe /kw] [kg Cu /kw] [kg Al /kw] [cm 2 Si /kw] Performance Indices Power Density [kw/dm 3 ] Power per Unit Weight [kw/kg] Relative Costs [kw/$] Relative Losses [%] Failure Rate [h -1 ]

102 102/114 Design Challenge Mutual Couplings of Performance Indices Trade-Offs For Optimized System Several Performance Indices Cannot be Improved Simultaneously

103 103/114 Abstraction of Power Converter Design Performance Space Design Space Mapping of Design Space into System Performance Space

104 Mathematical Modeling and Optimization of Converter Design 104/114

105 105/114 Multi-Objective Optimization Identifies Performance Limits Pareto Front Sensitivities to Technology Advancements (Example: η-ρ-pareto Front) Trade-off Analysis

106 106/114 Analysis of Performance Limits Pareto Front Clarifies Influence of Main Components and Operating Parameters

107 107/114 η-ρ-σ-pareto Surface σ: kw/$

108 108/114 Efficiency vs. Power Density FOM = Ratio of Relative Losses and Power Density

109 109/114 Observation Very Limited Room for Further Performance Improvement!

110 110/114 Observation Very Limited Room for Further Performance Improvement! Efficiency Power Density General Challenge in Power Electronics Cost Models are Becoming Mandatory Even for University Research(!)

111 111/114 Conclusions No Magic New Topology Technological Limits (Magnetics!) Light-Load Efficiency Ohmic Characteristics / ZVS / Interleaving! Modern Semiconductor Technology Modern Digital Control Technology System Oriented Analysis Architecture & Energy Management Adv. Packaging & Thermal Manag. for High Eff. AND Power Density

112 Questions 112/114

113 113/114 References J. W. Kolar, F. Krismer, Y. Lobsiger, J. Mühlethaler, T. Nussbaumer, J. Miniböck, Extreme Efficiency Power Electronics, Proc. of International Conf. of Integrated Power Electronics Systems (CIPS), Nuremberg, Germany, March 6-8, U. Badstuebner, J. Miniböck, J. W. Kolar, Experimental Verification of the Efficiency/Power-Density (n-p) Pareto Front of Single-Phase Double-Boost and TCM PFC Rectifier Systems, Proc. of 28 th IEEE Applied Power Electronics Conf. (APEC), Long Beach, California, USA, March 17-21, Acknowledgement F. Krismer Y. Lobsiger J. Mühlethaler Th. Nussbaumer J. Miniböck M. Kasper

114 114/114 About the Instructor Johann W. Kolar (F 10) received his M.Sc. and Ph.D. degree (summa cum laude / promotio sub auspiciis praesidentis rei publicae) from the University of Technology Vienna, Austria. Since 1984 he has been working as an independent international consultant in close collaboration with the University of Technology Vienna, in the fields of power electronics, industrial electronics and high performance drives. He has proposed numerous novel converter topologies and modulation/control concepts, e.g., the VIENNA Rectifier, the SWISS Rectifier, the Delta-Switch Rectifier, the isolated Y-Matrix AC/DC Converter and the three-phase AC-AC Sparse Matrix Converter. Dr. Kolar has published over 450 scientific papers at main international conferences, over 180 papers in international journals, and 2 book chapters. Furthermore, he has filed more than 110 patents. He was appointed Assoc. Professor and Head of the Power Electronic Systems Laboratory at the Swiss Federal Institute of Technology (ETH) Zurich on Feb. 1, 2001, and was promoted to the rank of Full Prof. in Since 2001 he has supervised over 60 Ph.D. students and PostDocs. The focus of his current research is on AC-AC and AC-DC converter topologies with low effects on the mains, e.g. for data centers, More-Electric-Aircraft and distributed renewable energy systems, and on Solid-State Transformers for Smart Microgrid Systems. Further main research areas are the realization of ultra-compact and ultra-efficient converter modules employing latest power semiconductor technology (SiC and GaN), micro power electronics and/or Power Supplies on Chip, multi-domain/scale modeling/simulation and multi-objective optimization, physical model-based lifetime prediction, pulsed power, and ultra-high speed and bearingless motors. He has been appointed an IEEE Distinguished Lecturer by the IEEE Power Electronics Society in He received 9 IEEE Transactions Prize Paper Awards, 8 IEEE Conference Prize Paper Awards, the PCIM Europe Conference Prize Paper Award 2013 and the SEMIKRON Innovation Award Furthermore, he received the ETH Zurich Golden Owl Award 2011 for Excellence in Teaching and an Erskine Fellowship from the University of Canterbury, New Zealand, in He initiated and/or is the founder/co-founder of 4 spin-off companies targeting ultra-high speed drives, multidomain/level simulation, ultra-compact/efficient converter systems and pulsed power/electronic energy processing. In 2006, the European Power Supplies Manufacturers Association (EPSMA) awarded the Power Electronics Systems Laboratory of ETH Zurich as the leading academic research institution in Power Electronics in Europe. Dr. Kolar is a Fellow of the IEEE and a Member of the IEEJ and of International Steering Committees and Technical Program Committees of numerous international conferences in the field (e.g. Director of the Power Quality Branch of the International Conference on Power Conversion and Intelligent Motion). He is the founding Chairman of the IEEE PELS Austria and Switzerland Chapter and Chairman of the Education Chapter of the EPE Association. From 1997 through 2000 he has been serving as an Associate Editor of the IEEE Transactions on Industrial Electronics and from 2001 through 2013 as an Associate Editor of the IEEE Transactions on Power Electronics. Since 2002 he also is an Associate Editor of the Journal of Power Electronics of the Korean Institute of Power Electronics and a member of the Editorial Advisory Board of the IEEJ Transactions on Electrical and Electronic Engineering.