Advanced Silicon Devices Applications and Technology Trends

Transcription

1 Advanced Silicon Devices Applications and Technology Trends Gerald Deboy Winfried Kaindl, Uwe Kirchner, Matteo Kutschak, Eric Persson, Michael Treu APEC 2015

2 Content Silicon devices versus GaN devices: An unbiased view on key performance indicators Applications: Comparison of devices in hard-switching and resonant circuits Summary Page 2

3 Content Silicon devices versus GaN devices: An unbiased view on key performance indicators Applications: Comparison of devices in hard-switching and resonant circuits Summary Page 3

4 Comparing competing device concepts Si Superjunction S n+ p+ G SiC vertical drift zone S G S GaN lateral HEMT G D p D R ON A scales with cell pitch Inherently fast switching dv/dt scales inversely with cell pitch Reverse recovery charge and snappyness of body diode as major drawbacks n D Pitch influences R ON A by improved utillization of the semiconductor volume Normally-on; turns into normally-off by Cascode or direct-driven concept Good body diode; Q rr close to SiC Schottky diodes p-implantation p+-implantation n+-implantation Oxide 2DEG n-epitaxy D Good starting point for low R ON A and Q OSS due to high electron mobility Device capacitances are strongly influenced by the metal re-routing Excellent reverse behavior Metal/Poly-Si AlN/AlGaN Barrier Si Substrate Buffer layer Page 4

5 R DSON, max A [Ωmm 2 ] How far can the Superjunction concept be exploited in terms of R DSon *A? S G n p + 1,00 CoolMOS TM C3 CoolMOS TM CP Si Superjunction MOSFET Other 1 Other 2 Other Ωmm 2 CoolMOS TM C7 1.0 Ωmm 2 p - p n + s ub n epi D SiC FET GaN HEMT 0,10 Si Superjunction limit D. Disney, G. Dolny ISPSD 2008 SiC and GaN devices 0, Still a long way until the limit is reached with Si Superjunction. Si limit potentially lower than 0.5 Ωmm 2 Page 5

6 The output capacitance of SJ devices gets more nonlinear with every generation! 190 mohm, 600V / 650V devices longer delay times lower switching losses Stronger non-linearity lower E oss higher dv/dt Page 6

7 The Q oss characteristic will become more and more flat! 190 mohm, 600V / 650V devices longer delay times in resonant applications more rectangular voltage waveforms trend reversed for next gen CoolMOS GaN significantly better in absolute FoM and linearity Page 7

8 E oss scales with cell pitch and can be brought below the level of 1st gen GaN devices 190 mohm, 600V / 650V devices FoM R on *E oss scales with pitch of SJ device next gen CoolMOS Page 8

9 Turn-off 5.3A [mj] 40% E oss reduction versus earlier SJ generation fully translates into lower turn-off losses! 190 mohm / 600V 0,013 0,012 BoxPlot Eoff2 [mj] (Subset:Iset2 [A] ('5,3')) grouped by GRP lo -- hi -- qty 36/36 mean sigma cp -- cpk -- Eoff2 [mj] 0,011 0,01 0,009 0,008 0,007 0,006 0,005 0,004 0,003 0,002 0,001 0 CoolMOS CP 600V next gen CoolMOS 40% reduction of switching losses (CoolMOS CP vs next gen CoolMOS ) Fully relieved switching up to around 10 Ohm gate resistor Rg [Ohm] LEGEND GRP G1 G2 G3 Page 9

10 Turn-on 5.3A [mj] Turn-on losses are mainly determined by package and no longer benefit from silicon improvements! 190 mohm / 600V 0,035 BoxPlot Eon [mj] (Subset:Iset2 [A] ('5,3')) grouped by GRP lo -- hi -- qty 36/36 mean sigma cp -- cpk -- 0,03 0,025 Eon [mj] 0,02 0,015 0,01 0,005 0 CoolMOS CP next gen CoolMOS Turn-on losses mainly limited by parasitic package inductances Significant improvement potential for 4pin & SMD packages Rg [Ohm] LEGEND GRP G1 G2 G3 Page 10

11 Package and switching cell optimization are mandatory to fully benefit from fast switching devices! Package level - Source inductance most critical - Solved by Kelvin contact - however inductance still in the commutation loop TO-247 4pin Kelvin contact to source, decoupling of gate drive, E on improvement Switching cell level - True SMD solution allows compact, low-inductive switching cell - Symmetric coupling capacitances to heatsink are important from EMI point of view - Top side cooling optional in DSO-20 Heatsink ThinPAK, TOLL, DSO-20 Page 11

12 SMD packages will be important for SJ devices and mandatory for GaN! PCB top view: T_LS Losses T_HS VAC d1 d2 s1 s2 C heatsink TO = ~20 pf 400V E Cpar = 1.6 µj E dev = 3 µj Voltage overshoot Power loop caps Current flow: C T_HS T_LS Top Layer Mid Layer VAC d1 d2 s1 s2 L par TO = ~20 nh E lpar_10a = 1 µj 400V V overshoot = 5kA/µs L par = 3-6 nh heatsink Commutation loop 3.2 nh Page 12

13 Rg int Example 190mΩ Cparasitic = 5pF Vgs [V] Turn Off dv/dt [V/ns] In case of layout constraints Possible Ringing Circuit L parasitic Layout C parasitic Layout Package Oscillation circuit triggered by Damping Element dv/ dt di/ dt dv/ dt Current ID [A] Example 190 mω Low switching losses are inevitably coupled to high dv/dt and di/dt values both at turn-on and turn-off. C7 CP P6 E6 C6 C3 η Layout Sensitivity With C6 a integrated Gate Resistor was introduced to damp Oscillations Optimization tradeoff efficiency and Layout with each new technology Layout sensitiviity + high efficiency How Damping to use behavior fast switching of Rg Internal SJ devices Avoid 30 a coupling capacitance between G,D C7 Place 20 the gate resistor close to the gate CP Avoid 10 Stray inductance in the Power Loop 0 P6 Use the mutual inductance effect (opposite current flow, 20 forced 40 current) in the 100 power E6 loop -20 current C6-30 Ids [A] C3 η 0 CP C7 CM1 ng P6 E6 CFD II CFD I C3 C6 Less Add layout ferrite dependencies beads if necessary can be achieved by choosing a technology with higher values of the damping resistor. Best performance Cost/performance segment Ease of Use optimized Page 13

14 Content Silicon devices versus GaN devices: An unbiased view on key performance indicators Applications: Comparison of devices in hard-switching and resonant circuits Summary Page 14

15 SJ devices will prevail in classic and dual boost GaN offers significant value in Totem Pole PFC Classic PFC Dual Boost PFC Totem Pole PFC Less System Cost Less Efficiency High Power Density High System Cost High Efficiency Less Power Density Less System Cost High Efficiency High Power Density GaN enables hard commutation on internal diode Superjunction (S1) SiC (D1) Superjunction (S1, S2) SiC (D1, D2) Superjunction (S1, S2) GaN, SJ, IGBT (S3, S4) Page 15

16 Best competing silicon alternative in terms of power density and efficiency: TCM PFC 3 kw, 4.5 kw/l (74W/in³) Source: U. Badstübner, J. Miniböck, J. Kolar, Experimental Verification of the Efficiency/Power-Density (n-p) Pareto Front of Single-Phase Double-Boost and TCM PFC Rectifier Systems, Proc. APEC Page 16

17 Efficiency Advantage of GaN: very high frequency operation with R on *Q oss and Q g as key parameters Input Caps RF Inductor Output Caps 99% GaN Switches Gate Driver High efficiency possible by frequency control 97% 95% 93% 91% 89% 87% 2.5 MHz 85% Po [W] Page 17

18 Comparison of hard-switching PFC stages: Reference: CoolMOS C7 / SiC G5 Reference: CCM PFC 100 khz; CoolMOS C7 65 mohm, 4pin; SiC G5 SBD 16A diode rectification bridge Page 18

19 Advantage of GaN: CCM modulation in Totem Pole PFC, close to 99% efficiency with simple half bridge solution 0.5% better efficiency half bridge Totem Pole, 65 khz; GaN 70 mohm return path: bridge rectifier (one diode only) Reference: CCM PFC 100 khz; CoolMOS C7 65 mohm, 4 pin; SiC G5 SBD 16A Page 19

20 Advantage of GaN: > 99% efficiency with combination of SJ and GaN in Totem Pole full bridge 0.2% better than half bridge 0.4% better than IGBT solution full bridge Totem Pole, 65 khz; Reference: CCM PFC 100 khz; GaN 70 mohm / IGBT F5 40A + 16A SiC SBD CoolMOS C7 65 mohm, 4 pin; return path: CoolMOS C7 35 mohm SiC G5 SBD 16A Page 20

21 Advantage of GaN: > 99% efficiency across wide low range with low frequency Totem Pole PFC >99% efficiency from % load 0.1% better than 65 khz solution full bridge Totem Pole, 45 khz; Reference: CCM PFC 100 khz; GaN 70 mohm CoolMOS C7 65 mohm, 4 pin; return path: CoolMOS C7 35 mohm SiC G5 SBD 16A Page 21

22 Expected performance of GaN versus latest SJ devices Resonant LLC DC/DC Converter (750 W, 400 khz) Q 1 D 1 V IN A C r L r n:1:1 S 1 Q 2 D 2 L m V O R L 0 S 2 GaN expected to be 0.7% better in partial load range GaN, 70 mohm GaN, 190 mohm P6, 190 mohm 350V 410 V to 12 V Power density > 200W/in³ Pure convection cooled Page 22

23 Latest SJ devices will benefit from parallel cap to counterbalance non-linearity Same dv/dt at 1/5th of magnetizing current Potential path to further efficiency increase for narrow range V in applications Page 23

24 Last but not least! Recent improvements in key Figure-of-Merits for low voltage MOSFETs n G n + n - sub sub S p D n 5 4,5 4 3,5 3 2,5 2 1,5 1 0,5 0 RDSon / SSO8 [mohm] Gen 3 Gen 4 RDSon*Qoss [mohm*nc *100] 100 V MOSFET: smaller area-specific on-resistance and charges through further optimization of trench structure Page 24

25 Allow new solutions by using cascaded multi-cell architectures! 3 kw AC/DC converter, 48V out Cascaded converter topology, Totem Pole + phase shift ZVS Efficiency target > 98% 100 V OptiMOS BSC034N10NS5 FinSix 65 W Adapter, 19V out Switching frequency > 10 MHz 200 V OptiMOS BSZ22DN20NS3 Page 25

26 Content Silicon devices versus GaN devices: An unbiased view on key performance indicators Applications: Comparison of devices in hard-switching and resonant circuits Summary Page 26

27 Summary Superjunction devices will continue to deliver better Best-in- Class R DSon devices with further improved FoM R on *E oss Recent improvements in low voltage devices FoMs allow to rethink classic architectures and consider the use of LV devices in HV applications The use of good layout practice, transition to 4pin packages and finally to SMD packages will become more and more important and is mandatory for GaN GaN offers specifically advantages both in terms of power density and efficiency at hard switching topologies with continuous use of the reverse characteristic and at very high switching frequencies in resonant converters Page 27

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