Bi-Directional N-Channel 20-V (D-S) MOSFET

Transcription

1 Bi-Dirctional N-Channl -V (D-S) MOSFET Si89EDB PRODUCT SUMMARY V SS (V) R SS(on) (Ω) I SS (A).45 at V GS = 4.5 V at V GS = 3.7 V at V GS =.5 V at V GS =.8 V 3.9 FEATURES Halogn-fr According to IEC TrnchFET Powr MOSFET Ultra-Low R SS(on) ESD Protctd: 4 V MICRO FOOT Chipscal Packaging Rducs Footprint Ara Profil (.6 mm) and On-Rsistanc Pr Footprint Ara APPLICATIONS Battry Protction Circuit - - Cll Li+/LiP Battry Pack for Portabl Dvics MICRO FOOT S Bump Sid Viw Backsid Viw S 5 4 S Pin Idntifir G 4 kω G 6 3 G 89E xxx Dvic Marking: 89E = P/N Cod xxx = Dat/Lot Tracability Cod G 4 kω S S Ordring Information: Si89EDB-T-E (Lad (Pb)-fr and Halogn-fr) N-Channl S ABSOLUTE MAXIMUM RATINGS T A = 5 C, unlss othrwis notd Paramtr Symbol 5 s Stady Stat Unit Sourc- Sourc Voltag V SS V Gat-Sourc Voltag V GS ± Continuous Sourc- Sourc Currnt (T J = 5 C) a T A = 5 C I SS T A = 85 C A Pulsd Sourc- Sourc Currnt I SM 4 T A = 5 C Maximum Powr Dissipation a.7 P D W T A = 85 C.8.5 Oprating Junction and Storag Tmpratur Rang T J, T stg - 55 to 5 C Packag Rflow Conditions c IR/Convction 6 THERMAL RESISTANCE RATINGS Paramtr Symbol Typical Maximum Unit Maximum Junction-to-Ambint a t 5 s 6 75 R thja Stady Stat 95 C/W Maximum Junction-to-Foot b Stady Stat R thjf 8 Nots: a. Surfac Mountd on " x " FR4 board. b. Th foot is dfind as th top surfac of th packag. c. Rfr to IPC/JEDEC (J-STD-C), no manual or hand soldring. Documnt Numbr: 786 S-8349-Rv. I, -Dc-8

2 Si89EDB SPECIFICATIONS T J = 5 C, unlss othrwis notd Paramtr Symbol Tst Conditions Min. Typ. Max. Unit Static Gat Thrshold Voltag V GS(th) V SS = V GS, I D = 98 µa.45. V V SS = V, V GS = ± 4.5 V ± 4 µa Gat-Body Lakag I GSS V SS = V, V GS = ± V ± ma V SS = V, V GS = V Zro Gat Voltag Sourc Currnt I SS V SS = V, V GS = V, T J = 85 C 5 µa On-Stat Sourc Currnt a I S(on) V SS = 5 V, V GS = 4.5 V 5 A V GS = 4.5 V, I SS = A Sourc-Sourc On Stat Rsistanc a R SS(on) V GS = 3.7 V, I SS = A.4.48 V GS =.5 V, I SS = A Ω V GS =.8 V, I SS = A.6.7 Forward Transconductanc a g fs V SS = V, I SS = A S Dynamic b Turn-On Dlay Tim t d(on).5 Ris Tim t r V SS = V, R L = Ω Turn-Off Dlay Tim t d(off) I SS A, V GEN = 4.5 V, R g = 6 Ω 7 6 µs Fall Tim t f 5 Nots: a. Puls tst; puls width 3 µs, duty cycl %. b. Guarantd by dsign, not subjct to production tsting. Strsss byond thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. Ths ar strss ratings only, and functional opration of th dvic at ths or any othr conditions byond thos indicatd in th oprational sctions of th spcifications is not implid. Exposur to absolut maximum rating conditions for xtndd priods may affct dvic rliability. TYPICAL CHARACTERISTICS 5 C, unlss othrwis notd - Gat Currnt (ma) I GSS I GSS at 5 C (ma) I GSS - Gat Currnt ( µa) T J = 5 C T J = 5 C V GS - Gat-to-Sourc Voltag (V) Gat-Currnt vs. Gat-Sourc Voltag V GS - Gat-to-Sourc V oltag (V) Gat Currnt vs. Gat-Sourc Voltag Documnt Numbr: 786 S-8349-Rv. I, -Dc-8

3 Si89EDB TYPICAL CHARACTERISTICS 5 C, unlss othrwis notd 8 V GS = 5 thru.5 V 8 ID - Drain Currnt (A) 6 4 I D - Drain Currnt (A) 6 4 T C = 5 C V 5 C - 55 C V DS - Drain-to-Sourc Voltag (V) Output Charactristics V GS - Gat-to-Sourc Voltag (V) Transfr Charactristics.6 - On-Rsistanc (Ω) R DS(on) V GS =.8 V V GS = 3.7 V V GS =.5 V V GS = 4.5 V R DS(on) - On-Rsistanc (Normalizd) V GS = 4.5 V I SS = A I D - Drain Currnt (A) On-Rsistanc vs. Drain Currnt T J - Junction Tmpratur ( C) On-Rsistanc vs. Junction Tmpratur. R DS(on) - On-Rsistanc ( Ω) I SS = A I SS = 5 A Varianc (V) V GS(th) I SS = 98 µa V GS - Gat-to-Sourc Voltag (V) On-Rsistanc vs. Gat-to-Sourc Voltag T J - Tmpratur ( C) Thrshold Voltag Documnt Numbr: 786 S-8349-Rv. I, -Dc-8 3

4 Si89EDB TYPICAL CHARACTERISTICS 5 C, unlss othrwis notd 3 I DM Limitd 5 Limitd by R DS(on) *. s Powr (W) Drain Currnt (A) I D I D(on) Limitd T A = 5 C Singl Puls. s. s s s s DC. Tim (s) Singl Puls Powr, Junction-to-Ambint BVDSS Limitd. V DS - Drain-to-Sourc Voltag (V) * V GS > minimum V GS at which R DS(on) is spcifid Saf Oprating Ara Normalizd Effctiv Transint Thrmal Impdanc Duty Cycl =.5. Nots: P DM.5 t t t.. Duty Cycl, D = t. PER UNIT BASE = R THJA = 95 C/W 3. T JM - T A = P DM Z (t) thja Singl Puls 4. Surfac Mountd Squar Wav Puls Duration (s) Normalizd Thrmal Transint Impdanc, Junction-to-Ambint Normalizd Effctiv Transint Thrmal Impdanc Duty Cycl = Singl Puls -3 - Squar Wav Puls Duration (s) Normalizd Thrmal Transint Impdanc, Junction-to-Foot - 4 Documnt Numbr: 786 S-8349-Rv. I, -Dc-8

5 Si89EDB PACKAGE OUTLINE MICRO FOOT: 6 BUMP ( x 3,.8 mm PITCH) 6 x.3.3 Not 3 Soldr Mask -.4 Not A A A b Diamtr Bump Not Rcommndd Land 89E XXX D s Mark on Backsid of Di s E Nots (Unlss Othrwis Spcifid):. 6 soldr bumps ar 95.5/3.8/.7 Sn/Ag/Cu.. Backsid surfac is coatd with a Ag/Ni/Ti layr. 3. Non-soldr mask dfind coppr landing pad. 4. Lasr marks on th silicon di back. Dim. Millimtrs a Inchs Min. Max. Min. Max. A A A b D E s Nots: a. Us millimtrs as th primary masurmnt. maintains worldwid manufacturing capability. Products may b manufacturd at on of svral qualifid locations. Rliability data for Silicon Tchnology and Packag Rliability rprsnt a composit of all qualifid locations. For rlatd documnts such as packag/tap drawings, part marking, and rliability data, s /ppg?786. Documnt Numbr: 786 S-8349-Rv. I, -Dc-8 5

6 PCB Dsign and Assmbly Guidlins For MICRO FOOT Products AN84 Johnson Zhao INTRODUCTION s MICRO FOOT product family is basd on a wafr-lvl chip-scal packaging (WL-CSP) tchnology that implmnts a soldr bump procss to liminat th nd for an outr packag to ncas th silicon di. MICRO FOOT products includ powr MOSFETs, analog switchs, and powr ICs. For battry powrd compact dvics, this nw packaging tchnology rducs board spac rquirmnts, improvs thrmal prformanc, and mitigats th parasitic ffct typical of ladd packagd products. For xampl, th 6 bump MICRO FOOT Si89EDB common drain powr MOSFET, which masurs just.6 mm x.4 mm, achivs th sam prformanc as TSSOP 8 dvics in a footprint that is 8% smallr and with a 5% lowr hight profil (Figur ). A MICRO FOOT analog switch, th 6 bump DG3DB, offrs low charg injction and.4 W on rsistanc in a footprint masuring just.8 mm x.58 mm (Figur ). MICRO FOOT products can b handld with th sam procss tchniqus usd for high-volum assmbly of packagd surfac-mount dvics. With propr attntion to PCB and stncil dsign, th dvic will achiv rliabl prformanc without undrfill. Th advantag of th dvic s small footprint and short thrmal path mak it an idal option for spac-constraind applications in portabl dvics such as battry packs, PDAs, cllular phons, and notbook computrs. FIGURE. 3D Viw of MICRO FOOT Products Si89DB and Si89EDB 8 ~ A.8 This application not discusss th mchanical dsign and rliability of MICRO FOOT, and thn provids guidlins for board layout, th assmbly procss, and th PCB rwork procss B FIGURE. Outlin of MICRO FOOT CSP & Analog Switch DG3DB Documnt Numbr: Jan-3

7 AN84 TABLE Main Paramtrs of Soldr Bumps in MICRO FOOT Dsigns ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ MICRO FOOT CSP Bump Matrial Bump Pitch* Bump Diamtr* Bump Hight* ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MICRO FOOT CSP MOSFET.8 ÁÁÁÁÁÁÁÁÁÁ MICRO FOOT CSP Analog Switch ÁÁÁÁÁÁ Eutctic Soldr: ÁÁÁÁÁÁÁ.5 ÁÁÁÁÁÁ 63Sm/37Pb ÁÁÁÁÁÁÁÁÁÁ MICRO FOOT UCSP Analog Switch ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ.5 ÁÁÁÁÁÁ * All masurmnts in millimtrs ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ.-.4 MICRO FOOT S DESIGN AND RELIABILITY As a mchanical, lctrical, and thrmal connction btwn th dvic and PCB, th soldr bumps of MICRO FOOT products ar mountd on th top activ surfac of th di. Tabl shows th main paramtrs for soldr bumps usd in MICRO FOOT products. A silicon nitrid passivation layr is applid to th activ ara as th last masking procss in fabrication,nsuring that th dvic passs th prssur pot tst. A grn lasr is usd to mark th backsid of th di without damaging it. Rliability rsults for MICRO FOOT products mountd on a FR-4 board without undrfill ar shown in Tabl. TABLE MICRO FOOT Rliability Rsults Tst Condition C: 65 to 5 C ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ >5 Cycls Tst condition B: 4 to 5 C > Cycls ÁÁÁÁÁÁÁÁÁ 5PSI % Humidity TstÁÁÁÁÁÁÁ 96 Hours Th main failur mchanism associatd with wafr-lvl chip-scal packaging is fatigu of th soldr joint. Th rsults shown in Tabl dmonstrat that a high lvl of rliability can b achivd with propr board dsign and assmbly tchniqus. BOARD LAYOUT GUIDELINES Board matrials. MICRO FOOT products ar dsignd to b rliabl on most board typs, including organic boards such as FR-4 or polyamid boards. Th packag qualification information is basd on th tst on.5-oz. FR-4 and polyamid boards with NSMD pad dsign. Land pattrns. Two typs of land pattrns ar usd for surfac-mount packags. Soldr mask dfind (SMD) pads hav a soldr mask opning smallr than th mtal pad (Figur 3), whras on-soldr mask dfind (NSMD) pads hav a mtal pad smallr than th soldr-mask opning (Figur 4). NSMD is rcommndd for coppr tch procsss, sinc it provids a highr lvl of control compard to SMD tch procsss. A small-siz NSMD pad dfinition provids mor ara (both latral and vrtical) for soldring and mor room for scap routing on th PCB. By contrast, SMD pad dfinition introducs a strss concntration point nar th soldr mask on th PCB sid that may rsult in soldr joint cracking undr xtrm fatigu conditions. Coppr pads should b finishd with an organic soldrability prsrvativ (OSP) coating. For lctroplatd nickl-immrsion gold finish pads, th gold thicknss must b lss than.5 m to avoid soldr joint mbrittlmnt. Coppr Soldr Mask Coppr Soldr Mask FIGURE 3. SMD FIGURE 4. NSMD Documnt Numbr: Jan-3

8 AN84 Board pad dsign. Th landing-pad siz for MICRO FOOT products is dtrmind by th bump pitch as shown in Tabl 3. Th pad pattrn is circular to nsur a symmtric, barrl-shapd soldr bump. TABLE 3 Dimnsions of Coppr Pad and Soldr Mask Opning in PCB and Stncil Aprtur ÁÁÁÁÁÁÁÁÁÁÁ Soldr MaskÁÁÁÁÁ Stncil ÁÁÁ PitchÁÁÁÁÁ Coppr Pad Opning Aprtur ÁÁÁÁÁ ÁÁÁÁÁ.33. ÁÁÁ.8 mmááááá.3. mmááááá.4. mmááááá in ciircl aprtur ÁÁÁ.3..5 mmááááá 7. mmááááá.7. mmááááá in squar aprtur Chip pick-and-placmnt. MICRO FOOT products can b pickd and placd with standard pick-and-plac quipmnt. Th rcommndd pick-and-plac forc is 5 g. Though th part will slf-cntr during soldr rflow, th maximum placmnt offst is. mm. Rflow Procss. MICRO FOOT products can b assmbld using standard SMT rflow procsss. Similar to any othr packag, th thrmal profil at spcific board locations must b dtrmind. Nitrogn purg is rcommndd during rflow opration. Figur 6 shows a typical rflow profil. 5 Thrmal Profil ASSEMBLY PROCESS MICRO FOOT products surfac-mount-assmbly oprations includ soldr past printing, componnt placmnt, and soldr rflow as shown in th procss flow chart (Figur 5). Stncil Dsign IIncoming Tap and Rl Inspction Soldr Past Printing Chip Placmnt Rflow Tmpratur ( C) Tim (Sconds FIGURE 6. Rflow Profil Documnt Numbr: Jan-3 Soldr Joint Inspction Pack and Ship FIGURE 5. SMT Assmbly Procss Flow Stncil dsign. Stncil dsign is th ky to nsuring maximum soldr past dposition without compromising th assmbly yild from soldr joint dfcts (such as bridging and xtranous soldr sphrs). Th stncil aprtur is dpndnt on th coppr pad siz, th soldr mask opning, and th quantity of soldr past. In MICRO FOOT products, th stncil is 5-mm (5-mils) thick. Th rcommndd aprturs ar shown in Tabl 3 and ar fabricatd by lasr cut. Soldr-past printing. Th soldr-past printing procss involvs transfrring soldr past through pr-dfind aprturs via application of prssur. In MICRO FOOT products, th soldr past usd is UP78 No-clan utctic 63 Sn/37Pb typ3 or finr soldr past. PCB REWORK To rplac MICRO FOOT products on PCB, th rwork procdur is much lik th rwork procss for a standard BGA or CSP, as long as th rwork procss duplicats th original rflow profil. Th ky stps ar as follows:. Rmov th MICRO FOOT dvic using a convction nozzl to crat localizd hating similar to th original rflow profil. Prhat from th bottom.. Onc th nozzl tmpratur is +9 C, us twzrs to rmov th part to b rplacd. 3. Rsurfac th pads using a tmpratur-controlld soldring iron. 4. Apply gl flux to th pad. 5. Us a vacuum ndl pick-up tip to pick up th rplacmnt part, and us a placmnt jig to placd it accuratly. 6. Rflow th part using th sam convction nozzl, and prhat from th bottom, matching th original rflow profil. 3

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