Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip

Transcription

1 Network-on-Chip Symposium, April 2008 Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang and Wei Hwang Department of Electronics Engineering & Institute of Electronics, and Microelectronics and Information Systems Research Center, National Chiao-Tung University, HsinChu 300, Taiwan

2 Outline Introduction Low power joint bus/error correction coding concept Self-corrected green coding scheme Triplication error correction coding stage Green bus coding stage Simulation Results Conclusions National Chiao-Tung University 2

3 Motivation Network-on-chip : an effective solution to integrate multi-core system and a process independent interconnection architecture. Physical design of NoC switch Link wires network interface National Chiao-Tung University 3

4 Introduction Three critical issues for on-chip communication Delay coupling capacitances Power parasitic and coupling capacitances Reliability degrading due to noises Novel design techniques are proposed to overcome the crosstalk effect and further provides a reliability bound for on-chip interconnection. Joint bus and error correction coding schemes National Chiao-Tung University 4

5 Outline Introduction Low power joint bus/error correction coding concept Self-corrected green coding scheme Triplication error correction coding stage Green bus coding stage Simulation Results Conclusions National Chiao-Tung University 5

6 A unified framework of coding in SoC k l Crosstalk Avoidance Code(CAC) Error Control Code (ECC) m Linear Crosstalk Code(LXC) m c Crosstalk avoidance codes (CAC) Avoid specific code patterns or code transitions to reduce delay and power dissipation. Error control codes (ECC) Detect and correct the error bits Linear crosstalk code (LXC) Shielding link wires, duplicated bits National Chiao-Tung University 6

7 Serialization technique for link wires K-to-N serialization K bits K/N bits physical transfer unit (phit) the data which is divided and transmitted through micro-network Area Cost (1/N 2 ) Switch delay Crosstalk, signal-to signal skew Signaling Rate -> predefined well-structured link National Chiao-Tung University 7

8 Self-corrected green coding scheme Self-corrected green coding scheme triplication error correction coding stage, green bus coding stage Shorter delay for ECC, more energy reduction and smaller area Switch Fabric Processor Element Processor Element interface interface Bus Encoder Serializer Joint bus and error correction coding with serializer/deserializer Bus Decoder Deserializer ECC encoder Channels through Multi switch fabrics ECC decoder ECC decoder ECC encoder ECC encoder ECC decoder National Chiao-Tung University 8

9 Outline Introduction Low power joint bus/error correction coding concept Self-corrected green coding scheme Triplication error correction coding stage Green bus coding stage Simulation Results Conclusions National Chiao-Tung University 9

10 Triplication error correction coding stage triplication set The hamming distance of each set is equal to 3. A constant delay of a majority gate and much smaller than others Rapid correction ability by self-corrected mechanism in bit-level. National Chiao-Tung University 10

11 Word error probability of triplication Error correction mechanisms Reducing supply voltage of channels without compromising the reliability of system. A Gaussian distributed noise voltage V N with variance is added to the signal waveform. 2 y V dd 1 ε = Q ( ) 2 2σ, Q x = e dy n 2π Word-error probability : where k : the size of bit-width : bit-error probability ε x 2 3 Ptriplication 3kε 2kε 2 σ N National Chiao-Tung University 11

12 Green Bus Coding Stage Green bus coding stage Reducing coupling effect Design Flow Establish triplication capacitance matrix Ct by RLC cyclic model Approximate Cyclic model C 1,2 C 2,3 C 3,4 Transition definition Derive power formula with the coefficient α C1,1 C 2, 2 C 3,3 C 4,4 Find the codeword to minimize the value, α Triplication capacitance matrix λ = C C X L, 3+ λ λ 0 0 t λ 3+ λ λ 0 C = C L 0 λ 3+ λ λ 0 0 λ 3+ λ Map the codeword to data-word Circuit Implementation National Chiao-Tung University 12

13 Five types of signal transitions Static transitions Type1 Type2 H Type3 L L L Cx Cx Cx L H Dynamic transitions Type4 Type5 L H L H H L L Type3 (no switching or switching in the same direction) Cx Cx L H L H signal aliasing National Chiao-Tung University 13

14 Triplication Power formula The power consumption can be derived as follow. P= f C V α L 2 DD ( d d d d ) ( ) α = 3( r + r + r + r + r ) + λ r r + r r + r r + r r λ ( ) Type 2,5 Type 1 α is a modified switching activity with considering coupling capacitances. The meaning of ri rj is that only one line is changing between two lines as type 1. For the term of ( d ) ij, it is about the two lines change in the opposite direction as type2 and type5 transitions. National Chiao-Tung University 14

15 Codeword of green bus coding National Chiao-Tung University 15

16 Encoder/decoder for green bus coding More simple and effective Avoid forbidden overlap condition (FOC) and forbidden pattern condition (FPC) and reduce forbidden transition condition (FTC) Encoder Decoder National Chiao-Tung University 16

17 Outline Introduction Low power joint bus/error correction coding concept Self-corrected green coding scheme Triplication error correction coding stage Green bus coding stage Simulation Results Conclusions National Chiao-Tung University 17

18 Energy reduction to un-coded code Simulation Condition : UMC 90nm CMOS technology The length of wires is set as 0.8mm of metal-4 with minimum width and spacing of 0.2um. Energy Reduction to uncoded bus (%) λ = C C X L National Chiao-Tung University 18

19 Voltage of specific error correction coding (k=8) 2 3 Ptriplication 3kε 2kε Voltage (V) National Chiao-Tung University 19

20 Voltage of specific error correction coding (k=32) 2 3 Ptriplication 3kε 2kε Voltage (V) National Chiao-Tung University 20

21 Summaries of different joint coding codec The proposed self-corrected green coding scheme has the smallest area overhead of codec. For the smallest delay, it is more suitable for the networkon-chip architecture. National Chiao-Tung University 21

22 Summaries of different joint coding schemes Except for s-c green coding, DAP and DSAP, the critical delay of codec depends on the decoder, others are not appropriate for integrating into switch fabrics because of long critical delay. National Chiao-Tung University 22

23 Outline Introduction Low power joint bus/error correction coding concept Self-corrected green coding scheme Triplication error correction coding stage Green bus coding stage Simulation Results Conclusions National Chiao-Tung University 23

24 Conclusions Self-corrected green coding scheme is presented to construct reliable and low power interconnection for NoC. Triplication error correction stage Rapid correction ability to reduce the physical transfer unit size Self-corrected in bit level Green bus coding stage More energy reduction by a joint triplication bus power model Based on UMC 90um CMOS technology, compared to uncoded code, self-corrected green coding can achieve 34.4% and 67.3% energy saving at voltage 1.2v and 0.84v, respectively. National Chiao-Tung University 24

25 Network-on-Chip Symposium, April 2008 Thanks for your attention!!