Design and Analysis of 1-Bit Full Adder and Logic Gates

Transcription

1 Design and Analysis of 1-Bit Full Adde and Logic Gates M. K. Musale, P.G. Student, Depatment of Electonics & Telecommunication Engineeing,Pavaa Rual Engineeing College, Loni, Mahaashta, India Pof. S. M. Tukane Associate Pofesso, Depatment of Electonics & Telecommunication Engineeing,Pavaa Rual Engineeing College, Loni, Mahaashta, India Abstact:The scaling of Metal-Oxide-Semiconducto Field Effect Tansisto (MOSFET) ae commonly used in high speed integated cicuits, yield smalle and faste moe functions at lowe cost. Vaious poblems exist with scaling of MOSFET devices i.e. shot channel effects (SCE), dain induced baie loweing, velocity satuation which limits the pefomance of MOSFETs. Scaling limitations of MOSFET devices leads to lowe ON to OFF cuent atio limited by 60mV/dec sub theshold slope.a new type of device called Tunnel FET is used to ovecome these difficulties. TFET can beat 60mV/dec sub-theshold swing of MOSFETs. In Tunnel FET the caie ae geneated by band-to-band tunneling and OFF cuent is low. Tunnel FET have enegy baie in OFF state, which avoids application whee leakage is concen of inteest. In this Poject sub-theshold swing and low OFF cuent is simulated and its powe is analyzed.basically in VLSI cicuit like design of IC we have to simulate all the paametes of the devices & cicuit egading of that IC o any devices like FET, MOSFET, CMOS etc. In device simulation we ae most widely use softwae named as HSPICE. We ae doing analysis of full bit adde. We ae going to compae diffeent chaacteistics. Keywods :MOSFET,TFET, HSPICE. ***** I. INTRODUCTION The Tunnel Field Effect Tansistos (TFET) ae one of the most pomising successos of Metal Oxide Semiconducto Field Effect Tansistos (MOSFET) due to thei potential fo sub- 60mV/decade sub-theshold swing. Such a educed swing is a necessay equiement fo ulta low powe, ulta low voltage and high speed opeation of next geneation VLSI cicuits. Accoding to the scientific epot- of IMEC, TFET is the most pomising device due to its stong similaity with the MOSFET configuation, which allows significant use of the existing MOSFET expetise in fabication of VLSI chips using TFETs. TFET can be a 3-teminal o a 4-teminal device built in silicon. The gate-contolled band to band tunneling is the woking pinciple of this tansisto [] and its basic stuctue is a gated P-I-N diode. Compaed to MOSFET, TFET has seveal advantages [, 3]: i) suitable fo low powe applications due to lowe leakage cuent, ii) bette immunity to shot channel effects, iii) subtheshold swing (SS) is not limited to 60mV/decade, iv) enhanced opeating speed due totunneling, v) much smalle theshold voltage (VTH) oll-off, vi) low off cuent and vii) highe on/off cuent atio. Thus TFET can be thought as a pomising altenative to the MOSFET fo low powe and high-speed applications. The Tunnel Field Effect Tansisto (TFET) had been chosen befoe as the most pomising device to espond to the demanding equiements of futue technology nodes. Tunnel FET use electic field contol of band to band tunnelling as the cuent gating mechanism [1,2]. The benefits of the TFET ae especially linked to its potential fo sub-60mv/decade subtheshold swings [4], a pe-equisite fo scaling the supply voltage well below 1V. Futhemoe, the TFET has educed shot-channel effects compaed to the MOSFET. Tunnelling is a quantum mechanical phenomenon with no analog in classical physics. It occus when an electon passes to a potential baie without having enegy to do. Tunneling is so geat i.e., lowe sub-theshold swing can allow lowe opeating voltages to be used [5]. It leads to chips that consume less powe. Electons tunnel fom valence band to conduction band to conduction band whee they eadily tanspot to dain teminal. Holes on dain side will tunnel into valence band and tanspot into floating body. In scaling, TFET do not suffe fom shot channel effects. Powe dissipation of TFETs can beat 60mV/dec sub-theshold swing of MOSFETs [4,9]. In most of the liteatue published so fa, the expeimentally shown ON-cuents ae unacceptably low fo a technology that would like to eplace the MOSFET. While OFF-cuents ae in the ange of femtoampees o micoampees, ON-cuents fo applied dain and gate voltages of 2 V ae still limited to the nanoampees ange. Futhemoe, in ode to have a CMOScompatible technology, voltages should be limited even moe, to about 1.2 V [9]. II. RELATED WORK Ove the last five decades, tansisto scaling has diven the temendous gains seen in the pefomance and powe of integated cicuits.the scaling of Metal-Oxide-Semiconducto Field Effect Tansisto (MOSFET) ae commonly used in high speed integated cicuits, yield smalle and faste moe functions at lowe cost. Vaious poblems exist with scaling of MOSFET devices i.e. shot channel effects(sce), dain induced baie loweing, velocity satuation which limits the pefomance of MOSFETs. Scaling limitations of MOSFET devices leads to lowe ON to OFF cuent atio limited by 60mV/dec sub theshold slope. IJRITCC Febuay, 73

2 A new type of device called Tunnel FET is used to ovecome these difficulties. TFET can beat 60mV/dec sub-theshold swing of MOSFETs. In Tunnel FET the caie ae geneated by band-to-band tunneling and OFF cuent is low. Tunnel FET have enegy baie in OFF state, which avoids application whee leakage is concen of inteest. In this Poject subtheshold swing and low OFF cuent is simulated and its powe is analyzed. Due to the technology scaling CMOS size is shinking, pefomance is impoved but new poblems aoused that is shot channel length effects which causes moe leakage Figue1. Basic stuctue of PTFET cuents and hence moe powe dissipation. To avoid this Souce and dain ae heavily doped p and n typeegions poblem eseache have found new device stuctue o espectively. In case of PTFET, the substate is lightly doped p- technology which is Tunnel FET. They both ae designed to type while souce and dain ae heavily doped with ntype and ovecome the shot channel length effects of CMOS. And these p-type dopants espectively. The doping concentation of devices ae now becoming moe advanced and bette than souce and dain ae about cm-3 and fo substate and CMOS. channel, the doping concentation is 15 cm-3 so that the 1. To study the diffeent chaacteistics of TFET. channel behaviou is intinsic. Channel doping concentation 2. Design TFET efeing latest IEEE pape in HSPICE. (NCH) is vaied late to study the effect of channel concentation on device pefomance. 3. Optimize TFET fo best pefomance in HSPICE. 4. Design diffeent enegy efficient cicuit using CMOS, IV. GATE VOLTAGE VS DRAIN CURRENT (IDS-VGS) TFET and Optimized Tunnel-FET fo nm CHARACTERISTICS: technology in HSPICE. Invete. Ripple Cay Adde. Gates. Full adde. 5. Compae diffeent paametes of CMOS, TFET and Optimized Tunnel-FET to impove the pefomance of diffeent enegy efficient cicuits. 6. To study the compaative chaacteistics of CMOS, TFET & Optimized TFET. III. OVERVIEW OF TFET The simulated cosssection of a p-type TFET is shown in fig. 1. The channel widthand length of the device is taken as 60nm and nmespectively. The device stuctue of TFET esembles that ofthe MOSFET with one exception. In the MOSFET, souce anddain ae doped with the same type of dopants and the dopanttypes ae opposite to that of substate, while in a TFET, souceand dain ae of opposite doping types and the dain egion hasa doping type same as that of substate with highconcentation. Accoding to stuctual configuation, TFET isa combination of seveal devices []: 1) the evesed P-I- Ndiode at the off state, 2) Esaki tunnel diode at the on state, 3)the MOS diode to fom the invesion o accumulation laye when gate voltage is applied. In an NTFET, the substate is lightly doped with n-type dopants. The gate voltage-dain cuent (IDS VGS) chaacteistics of thentfet and PTFET ae shown in fig. 3. In the case of NTFET,the dain cuent inceases with inceasing gate voltage. Ifnegative gate voltage is applied, the NTFET will show a weakptfet behaviou.in case of PTFET, the dain cuent inceases with deceasingthe gate voltage. The weak NTFET behaviou can also beobseved hee when positive gate voltage is positive. It is cleafom the fig. 3 that, fo PTFETs, the cuent value is less whenpositive gate voltage is applied as compaed to the cuentvalues of NTFET when negative voltage is applied. This isdue the facts that the theshold voltage of PTFET is moe thanthat of NTFET and lage effective mass of caies in thepfet which educes the tunnelling pobability. Figue 3. Ids- Vgs chaacteisticsof a nm NTFET and PTFET IJRITCC Febuay, 74

3 As aleady mentioned in the model calibation pat, that using Enegy Balance Tanspot fo simulations does not bing a B=B3 B2B1 B0 significant change in the device chaacteitics. In this context, - Fig. 3(a) (inset) compaes the cuent voltage chaacteistics A+B= =CoutS3S2S1S0 obtained fom DD and EBT model and they ae found to be simila and in close poximity to each othe and thus validates Fom the example above it can be seen that we ae the choice of Dift Diffusion model. compaes the TFET adding 3 bits at a time sequentially until all bits ae achitectues fo thei Ids-Vgs chacteistics. The On cuent added. Afull adde is a combinational cicuit that (ION) fo a p-n-p-n achitectue is enhanced in compaison to pefoms the aithmeticsum of theeinput bits:augends p-i-n due to a heavily doped n+ pocket egion pesent at the Ai, addend Bi andcayinc in fomthe pevious souce channel junction, which helps in impoving the lateal adde.its esults contain the sum Si and the electic field appeaing at the tunneling junction and hence the cayout,c dive cuent. It has been obseved that the p-i-n and HG p-i-n out tothenextstage. stuctue and similaly p-n-p-n and HG p-n-p-n stuctue have identical I ds-vgs and Ids-Vds chaacteistics. So to design a 4-bit adde cicuit we stat by designing the 1 bit full adde then connecting the fou 1-bit full addes to get the 4-bit adde as shown in the diagam above. Fothe 1- bitfulladde, thedesignbegins bydawingthe Tuth Tablefothetheeinputand the coespondingoutput SUM and CARRY.TheBoolean Expession descibingthe binayadde cicuit is then deduced. The binayfulladde is atheeinput combinational cicuitwhich satisfies thetuth tablebelow. Figue 3(a) TFET tansfe chaacteistics (I DS VS V GS ) V. OVERVIEW OF RCA RippleCayAdde (RCA) is a basicadde which woks on basic addition pinciple. Theachitectue of RCAis shown in Fig4. Fig.5 Diagam and Tuth Table offulladde TheBoolean equations of a fulladde aegiven by: S out =ABC +AB C +A B C +BA C S out =A B C C out =AB +AC +BC C out =AB +C(A B) Fig.4 Block diagam of RCA RCAcontainsseiesstuctueofFullAddes(FA),eachFAisusedtoa ddtwobitsalongwithcaybit.thecaygeneated fom eachfulladdeisgivento nextfulladdeandso on.hence,thecayispopagatedin a seialcomputation.hence,delayismoeas thenumbeofbitsisinceasedinrca. Assumeyou want to addtwo opeands Aand B whee The cicuitdiagam is shown in Fig.6. A=A3 A2 A1A0 Fig. 6.TheGate level Diagam offulladde IJRITCC Febuay, 75

4 VI. EXPERIMENTAL RESULTS 8.86E- 2.71E- 5.78E- 6.52E- 3.77E- NOT 1.89E- 6.51E- 5.E- 2.82E- 1.50E- VDD Avgp Peakp XOR VD D AND VD D 5.E- 1.43E- 3.33E- 7.37E- 1.58E- 3.E- 6.94E- 1.46E- Avgpw 2.84E- 7.49E- 3.81E- 8.17E- 3.65E- 7.75E- Avgpw 6.84E- 1.78E- 4.E- Peakp 2.E- 4.37E- 4.96E- 2.E- 5.34E- 8.69E- 1.E E E- 2.33E- 2.33E- 8.97E- 1.88E- 2.91E- 6.94E- 4.17E- Peakpw 5.22E- 1.01E- 7.59E- 9.15E- 2.67E- 9.40E- 6.77E- 8.48E- 1.E- 2.24E- 4.E- 1.57E E- 2.66E E- 4.56E- 5.26E- 7.E- 1.14E E- 2.E- 7.82E- 4.28E- 3.87E- 4.97E- 7.59E- 1.29E- 1.E E E E 1.83E 1.43E 1.58E 2.15E 1.97E- 2.77E- 4.51E- 1.E- 4.73E- 2.87E- 2.E- 1.67E- 1.72E- 2.83E- 9.E- 5.37E- 3.98E- 3.22E- 2.79E- 7.69E- 2.84E- 1.E- 8.66E E E 1.13E- 1.60E- 2.61E- IJRITCC Febuay, OR VDD 3.95E- 8.24E- Avgp 9.93E E E E E E - 1.E E E- 2.E- 3.45E- Peakp 1.62E- 3.67E- 3.73E- 1.42E- 2.81E- 4.04E- 5.E- 6.72E- 6.90E- 1.E- 1.78E- 1.E- 1.34E- 1.83E- 1.75E- 1.28E- 1.03E- 1.E- 4.66E- 1.78E- 9.41E- 8.24E- 1.00E- 1.42E- 2.22E- VII. CONCLUSION 1.40E E E E- 2.58E- 1.89E- 2.31E- 1.E- 1.77E- 2.97E- 7.35E- 3.13E- 1.33E- 1.04E- In this wok pefomance of TFET is discussed. We popose an d discussed the basic static opeation, and studied by simulation the chaacteistics of tunnel FET as a bette than 60mV/dec cu ent switch. TFET has lowe sub-theshold slop than MOSFET. Tunnel FET isapplicable fo low powe devices as it gives low e off cuent. It is difficult achieve highi ON degading I OFF,and sub-theshold slop below 60mV/dec.TFET is one of the pomis ing device. The powe of TFET is vey low. The gate has been implementedusing TFET the obseved in shows TFET is low p owe as compaed to conventional MOSFET. REFERENCES [1] A. C. Seabaugh and Q. Zhang, Low-voltage Tunnel tansistos fo beyond CMOS logic, Poc. IEEE, vol. 98, no., pp. 25,Dec. [2] A. M. Ionescu and H. Riel, Tunnel field-effect tansistos a s enegy efficient electonic switches, Natue, vol. 479, no. 7373, pp , Nov.. [3] Aticles fom Geneal knowledge Today, Tunnel-FET tech nology, 76

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