Short-Circuit Fault Protection Strategy of Parallel Three-phase Inverters

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1 Shot-Cicuit Fault Potection Stategy of Paallel Thee-phase Invetes Hongliang Wang, Membe, IEEE, Xuejun Pei, Membe, IEEE, Yu Chen, Membe, IEEE,Yong Kang College of Electical and Electonics Engineeing Huazhong Univesity of Science and Technology Wuhan, China Abstact In this pape, a five-stage fault potection scheme against the shot-cicuit fault fo paallel high-powe thee-phase combined invete to achieve high eliability is poposed. Thee ae two contol modes, Voltage Contolled Mode (VCM) and Cuent Contolled Mode (CCM). VCM opeates unde nomal opeation to keep constant output voltage. CCM opeates unde fault opeation to limit the output cuent, which is combined with hadwae cuent limit cicuit and softwae cuent limit unit. Fo paallel invete system, the output voltage ecoves quickly and then switch fom CCM to VCM fo invete once the shot-cicuit fault is ecoveed. Howeve, A little time diffeence of switching mode between paallel invetes esults in the suge ciculating cuent, which educes the system eliability. Thus, the pesynchonized state is added to achieve the cuent shaing at any time and to achieve simultaneous mode change fo each invete. A pototype with two paallel thee-phase 400kVA/50HZ invetes is built to veify the eliability of the poposed method. I. INTRODUCTION High powe invete has played a key ole in industy application, such as uninteuptible powe supply (UPS), high-powe moto dive, flexible ac tansmission system (FACT), enegy stoage system and enewable geneation [1]. With the powe capacitances inceasing, the paallel technique is good choice to system eliability [2]. Distibuted logic contol [3] and doop contol has been mainly adopted because of high eliability. All units ae maste unit and the system can wok nomally if one unit fails. The doop contol does not need the communication line; howeve, inheent tade-off exists between the powe shaing accuacy and the output voltage egulation, such as fequency and magnitude offset with load changing [4]. The distibuted logic contol is adopted in this pape. Most abnomal situations, such as shot-cicuit fault is discussed in many liteatue [5-11]. The fault happens at switching devices o output side of the load. This pape only focuses on the load-side potection stategy. Yan-Fei iu, Fellow,IEEE Depatment of Electical and Compute Engineeing Queen s Univesity Kingston, Canada yanfei.liu@queensu.ca Nomally, a small oveload capability of high-powe invete is designed due to the limitation of the cost. Thus, the switching devices could be damaged without any potection method when the load side is shot cicuit. To cut off the shot-cicuit fault, cicuit beakes o fuses installed between invete and loads, which is only a nomal potection method fo powe system. Thee ae woking time equiements, such as the 20ms-100ms fo mico gid application o UPS application to fault ecovey [5]. Fo these situations, seveal shot-cicuit potection stategy wee developed fo invete [6-11]. To quickly potect the switching devices, the hadwae method to cut off the dive signal has fast cuent limit and high eliability [9], which might avoid the switching device damage. And then softwae method can wok to get equied limited cuent [11]. Unfotunately, no liteatue focus on the shot-cicuit potection stategy fo paallel system, thee ae lage diffeence between single invete and seveal paallel invetes, thee is the suge ciculated cuent between each invete at tansient opeation once they have a little time diffeence to switch mode. In this pape, A five-stage fault potection fo the shot-cicuit fault fo high-powe paallel invetes. The five stages ae nomal state, hysteesis contolled state, cuent-contolled state, pe-synchonized state and ecovey state. The invete woks in VCM at nomal state. Once the shot-cicuit fault happens, the invete is switched into CCM, which includes hysteesis contolled state and cuent contolled state by hadwae and softwae. And then, the output cuent is kept constant. When the fault point is cleaed, the output voltage inceases quickly, the paallel invetes come into pesynchonized state to pomise the synchonized time by /15/$ IEEE 1736

2 paallel communication, and then, the paallel invetes go back to VCM. This pape is oganized as follows: In Section II, the system stuctue and shot-cicuit issues of paallel invetes. Section III shows the poposed fault stategy. Section IV gives the expeiment esults to veify the feasibility of the poposed method. The conclusion is given in Section V. II. SYSTEM STRUCTURE AND SHORT-CIRCUIT ISSUE ISSUES Fig.1 shows the paallel system based on two combined thee-phase invetes. The combined theephase invete can povide the high powe and woks in unbalanced load compaed to the thee-phase H-bidge invete [12].The esiste is equivalent esistance of wies, satuation voltages of the switching devices and dead-time effect. and C is the second-ode filte to eliminate the high-fequency hamonic content [13]. The line-fequency tansfome is injected between the output filte C and the load to meet galvanic isolation and to educe instantaneous shot cicuit cuent thanks to the impedance of the leakage inductance. The paallel technique is used in distibuted logic contol. And thee is the communication signal of each othe; the detailed block diagam is show in next section. The shot-cicuit fault is cleaed by the beake. Usually, two stage potection beakes ae used accoding to powe equiement. The fist stage potection beake cleas the instantaneous shot-cicuit point; when the instantaneous fault cuent is exceed the instantaneous theshold value. Thee is almost not delay time, and it is called instantaneous fault in this pape. The second stage potection beake clea the shotcicuit point afte designed delay time, which is called time-limited fault in this pape [11]. Fo testing system, the diffeent ecovey time beakes ae used, Beake T 1 and T 2 imitate the situation in Fig.1, the shot-cicuit point is point A, the beake T 1 tips fault afte seveal milliseconds (ms), which is simila the opeation by themal tip. It ealizes the time-limited fault. When the shot cicuit point is point B, the beake T 2 tips, which is also no moes delay time to ecovey fault, and it ealizes the instantaneous fault. Fig. 1 paallel system based on two combined thee-phase invete III. PROPOSED FAUT PROTECTION STRATEGY FOR PARAE INVERTERS Fig.2 shows the poposed five-stage potection opeation fom the nomal state to the ecovey state. The invete is contolled in voltage contolled mode, which supplies the constant voltage fo all loads. 1737

3 Fig.2 poposed fault potection states In the nomal opeation, thee-phase invete is contolled in VCM as a constant ac voltage; PI contol can effectively follow the efeence voltage without steady state eo because it is woked based on synchonous otating efeence fame (dq) [14]. Once shot cicuit happens at load side, the output cuent inceased lagely as load impedance is vey small. To potect the switching devices, the system entes into CCM to keep the cuent within easonable scope. Thee is a state tansition fom VCM to CCM. Ideally, the tansition is vey fast and smooth. Howeve, a seies delay time, such the cuent sensing delay, calculation time, and digital contolled delay time, esults in the fault cuent, which might damage the switching devices duing the inteval of the mode tansition. The beake cleas the fault point. The output voltage inceases and meets the equiement efeence voltage as the output load impedance inceased at constant cuent opeation fo only one invete system. Howeve, the paallel invetes system, Thee ae a suge cuent when the switching time is diffeent fom CCM to VCM. Futhemoe, the system will be damaged as the lage ciculated cuent of each invete, which educes the system eliability. The hysteesis cuent state is based on the hadwae cicuit as shown in Fig.3 [10-11]. Fo the simple explanation, it is assumed that is phase a. The simila analysis and cicuit is implemented in othe phases. A hysteesis compaato is constituted in Fig.3 (a).the vaiable Vd (t) is the measued voltage value of dc-link cuent in phase a. Vs is the souce voltage. Seveal esistos, such as R1, R2, R3, R4, and R5 ae designed to meet two diffeent theshold values. Fig.3 (b) shows the key wavefom, the peak cuent is limited with in theshold cuent by hadwae cicuit. (a) Hysteesis (b) key wavefom Fig.3 Hysteesis compaato cicuit and key wavefom The theshold values ae expessed as (1) R2 // R3 Vth1 = Vs R1+ R2 // R3 R1// R2 R2 //( R3+ R4) Vth2 = ( + ) V R1// R2 + R3+ R4 R1+ R2 //( R3+ R4) s (1) Fig.4 shows five-stage stuctue of two paallel invetes. In nomal opeation, S 1 and S 2 is zeo. Thus, the system is woking in voltage contolled mode. Once 1738

4 shot cicuit fault happens, the mode is changed fom voltage contolled mode to cuent contolled mode. At fist, the hysteesis peak-cuent mode makes a function to limit the peak-cuent value as hadwae cicuit s esponse. And then the cuent loop is woking to keep the output cuent constant unde S 1 =0, S 2 =1. Once shot cicuit fault is cleaed, the system is switched into the pe-synchonized mode. And then the system tansited fom cuent contolled mode to voltage contolled mode at the same time fo all paallel invetes. To veify the feasible of poposed method, the expeiment will be done in next section Fig.4 five-stage contol and tansition stuctue fo paallel invetes IV. EXPERIMENT RESUTS The paallel system pototypes based on two invetes is built to veify the poposed method. Fig.5 shows the paallel invetes and inne stuctue. 1739

5 a two paallel invetes (b) Inne stuctue Fig.5 2*400KVA paallel invetes pototype Tab.1 shows the element paametes. The output cuents ae limited within 2400A due to the hysteesis cuent state. Fig.6 shows the conventional potection method without pe-synchonized mode. Fig.6 (a), (c) show the expeiment wavefoms unde instantaneous fault o time-limited fault. Thee ae lage ciculated cuent when the fault is cleaed. Fig.6 (b), (d) shows the diffeence of two cuent, thee ae lage scope at second o fouth quadant, which means the instantaneous cuents have an opposite diection. Tab.1 expeiment paamete i(1000a/ u(500v/ ) b Diffeence of two cuents unde instantaneous fault u1 u2 i1 i2 t(0.1s/div) c Expeiment wavefom unde time-limited fault i(1000a/div u(500v/div) u1 u2 i1 i2 t(0.1s/div) a Expeiment wavefom unde instantaneous fault d Diffeence of two cuents unde time-limited fault Fig.6 the expeiment esults of conventional method fo paallel invetes Ch1: Output voltage Vab of invete one; Ch2:Output voltage vab of invete two; Ch3:Output cuent ia of invete one; Ch4: Output cuent ia of invete two Fig.7 shows the poposed potection method including pe-synchonized mode. Fig.6 (a), (c) show the expeiment wavefom unde instantaneous fault o timelimited fault. They ae almost the same at total time. Fig.7 (b), (d) shows the diffeence of two cuent. Two 1740

6 cuent of invetes ae been shaed at any time whateve nomal opeation o fault opeation. Compaed with Fig.6 and Fig.7, The poposed method can achieve cuent shaing at steady state opeation and limit the suge cuent at tansition opeation fo paallel invetes. It enhances the system s eliability. d Diffeence of two cuents unde time-limited fault Fig.7 the expeiment esults of poposed method fo paallel invetes Ch1: Output voltage Vab of invete one; Ch2: Output voltage vab of invete two Ch3:Output cuent ia of invete one; Ch4: Output cuent ia of invete two V. CONCUSION a Expeiment wavefom unde instantaneous fault b Diffeence of two cuents unde instantaneous fault A five-stage shot-cicuit fault potection stategy is poposed fo paallel system of high-powe thee-phase invetes. The output cuent is quickly limited to easonable value based on hadwae cuent limiting cicuit and softwae cuent limiting method. Afte the fault point is cleaed. A pe-synchonized state is povided to keep the synchonized time and then go back to voltage contolled mode, which pevents the suge cuent fom CCM to VCM of each invete individual. 2*400KVA invete expeiment esults shows that the suge cuent is cancelled by the poposed method. And the output cuent is shaed at any steadystate time and tansition time. The system has an excellent eliability to wok shot cicuit fault. c Expeiment wavefom unde time-limited fault REFERENCES [1] E. P.Wiechmann, P. Aqueveque, R. Bugos, and J. Rodiguez, On the efficiency of voltage souce and cuent souce invetes fo high-powe dives, IEEE Tans. Ind. Electon., vol. 55, no. 4, pp , Ap [2] M. Peindl, E. Schaltz, and P. Thogesen, Switching fequency eduction using model pedictive diect cuent contol fo high-powe voltage souce invetes, IEEE Tans. Ind. Electon., vol. 58, no. 7, pp , Jul [3] F. uo, Y. Zhang, Y. Kang, B. Xie, "An potocol design fo distibuted logic contolled paallel opeation UPS system," in Poc. Electic Machines and Dives Confeence.(IEMDC 09), 2009, pp [4] Gueo. J. M, Gacia. D., Matas. J, Castilla. M and so on. Output impedance design of paallel-connected UPS invetes 1741

7 wihwieless load shaing contol, IEEE Tans. Ind. Electon., vol. 52, no. 4, pp , Ap [5] S. A. M. Javadian, M. R. Haghifam, and P. Baazandeh, An adaptive ove-cuent potection scheme fomvdistibution netwoks including DG, Poc. IEEE ISIE, pp , Jun [6] M. J. Newman and D. G. Holmes, An integated appoach fo the potection of seies injection invetes, IEEE Tans. Ind. Appl., vol. 38, no. 3, pp , May [7] Y. Du, X. Bian, S. ukic, B. S. Jacobson, and A. Q. Huang, A novel wide voltage ange bi-diectional seies esonant convete with clamped capacito voltage, Poc. IEEE IECON, pp , Nov [8] I. Axente, M. Basu, M. F. Conlon, and K. Gaughan, Potection of unified powe quality conditione against the load side shot cicuits, IET Powe Electon., vol. 3, no. 4, pp , [9] Alavi.M, D. Wang, M. uo, Shot-cicuit fault diagnosis fo thee-phase invetes based on voltage-space pattens, IEEE Tans. Ind. Electon., vol. 61, no. 10, pp , Oct [10] H. Wang, X. Yue, X. Pei, Y. Kang, "A cuent-limiting potection stategy fo the combined thee-phase invete," in Poc. Electic Machines and System Confeence.(IEMS 08), 2008, pp [11] X. Pei, Y. Kang, Shot-cicuit fault potection stategy fo high-powe thee-phase thee-wie invete, IEEE Tans. Ind. Infomat., vol. 8, no. 3, pp , Ma [12] D.. Chen, X. i, R. Zhang, and H. T. Zhang, Combined thee-phase invetes with high fequency pulse DC link, Poc. IEEE-PESC, pp , [13] P. Ranstad and H. P. Nee, On the distibution of ac and dc winding capacitances in high-fequency powe tansfomes with ectifie loads, IEEE Tans. Ind. Electon., vol. 58, no. 5, pp , May [14] X. i, Z. Deng, Z. Chen, and Q. Fei, Analysis and simplification of thee-dimensional space vecto PWM fo thee-phase fou-leg invetes, IEEE Tans. Ind. Electon., vol. 58, no. 2, pp , Feb

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